Add SYSCFG definitions for STM32L152; Add board support STM32L-Discovery

arch/arm/src/stm32/Kconfig

@@ -480,6 +480,11 @@ config STM32_ADC4
 	select STM32_ADC
 	depends on STM32_STM32F30XX
 
+config STM32_COMP
+	bool "COMP"
+	default n
+	depends on STM32_STM32L15XX
+
 config STM32_BKP
 	bool "BKP"
 	default n
@@ -626,7 +631,7 @@ config STM32_SPI2
 config STM32_SPI3
 	bool "SPI3"
 	default n
-	depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX || (STM32_VALUELINE && STM32_HIGHDENSITY)
+	depends on STM32_CONNECTIVITYLINE || STM32_STM32L15XX || STM32_STM32F20XX || STM32_STM32F40XX || (STM32_VALUELINE && STM32_HIGHDENSITY)
 	select SPI
 	select STM32_SPI
 
@@ -654,7 +659,7 @@ config STM32_SPI6
 config STM32_SYSCFG
 	bool "SYSCFG"
 	default y
-	depends on STM32_STM32F30XX || STM32_STM32F20XX || STM32_STM32F40XX
+	depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F20XX || STM32_STM32F40XX
 
 config STM32_TIM1
 	bool "TIM1"
@@ -693,17 +698,17 @@ config STM32_TIM8
 config STM32_TIM9
 	bool "TIM9"
 	default n
-	depends on STM32_STM32F20XX || STM32_STM32F40XX
+	depends on STM32_STM32L15XX || STM32_STM32F20XX || STM32_STM32F40XX
 
 config STM32_TIM10
 	bool "TIM10"
 	default n
-	depends on STM32_STM32F20XX || STM32_STM32F40XX
+	depends on STM32_STM32L15XX || STM32_STM32F20XX || STM32_STM32F40XX
 
 config STM32_TIM11
 	bool "TIM11"
 	default n
-	depends on STM32_STM32F20XX || STM32_STM32F40XX
+	depends on STM32_STM32L15XX || STM32_STM32F20XX || STM32_STM32F40XX
 
 config STM32_TIM12
 	bool "TIM12"
@@ -797,7 +802,7 @@ config STM32_UART8
 config STM32_USB
 	bool "USB Device"
 	default n
-	depends on (STM32_STM32F10XX && !STM32_VALUELINE) || STM32_STM32F30XX
+	depends on (STM32_STM32F10XX && !STM32_VALUELINE) || STM32_STM32L15XX || STM32_STM32F30XX
 	select USBDEV
 
 config STM32_WWDG

arch/arm/src/stm32/chip/stm32f30xxx_rcc.h

@@ -1,5 +1,7 @@
 /************************************************************************************
  * arch/arm/src/stm32/chip/stm32f30xx_rcc.h
+ * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
+ * 32-bit MCUs
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>

arch/arm/src/stm32/chip/stm32f30xxx_syscfg.h

@@ -80,10 +80,10 @@
 /* SYSCFG memory remap register */
 
 #define SYSCFG_CFGR1_MEMMODE_SHIFT     (0)       /* Bits 1:0 MEM_MODE: Memory mapping selection */
-#define SYSCFG_CFGR1_MEMMODE_MASK      (3 << SYSCFG_CFGR1_SHIFT)
+#define SYSCFG_CFGR1_MEMMODE_MASK      (3 << SYSCFG_CFGR1_MEMMODE_SHIFT)
-#  define SYSCFG_CFGR1_MEMMODE_FLASH   (0 << SYSCFG_CFGR1_SHIFT) /* 00: Main Flash at 0x00000000 */
+#  define SYSCFG_CFGR1_MEMMODE_FLASH   (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */
-#  define SYSCFG_CFGR1_MEMMODE_SYSTEM  (1 << SYSCFG_CFGR1_SHIFT) /* 01: System Flash at 0x00000000 */
+#  define SYSCFG_CFGR1_MEMMODE_SYSTEM  (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */
-#  define SYSCFG_CFGR1_MEMMODE_SRAM    (3 << SYSCFG_CFGR1_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
+#  define SYSCFG_CFGR1_MEMMODE_SRAM    (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
 #define SYSCFG_CFGR1_USB_ITRMP         (1 << 5)  /* Bit 5:  USB interrupt remap */
 #define SYSCFG_CFGR1_TIM1_ITR3RMP      (1 << 6)  /* Bit 6:  Timer 1 ITR3 selection */
 #define SYSCFG_CFGR1_DAC_TRIGRMP       (1 << 7)  /* Bit 7:  DAC trigger remap (when TSEL = 001) */

arch/arm/src/stm32/chip/stm32l15xxx_rcc.h

@@ -428,14 +428,18 @@
                                               /* Bits 2-7: Reserved */
 #define RCC_CSR_LSEON               (1 << 8)  /* Bit 8:  External Low Speed oscillator enable */
 #define RCC_CSR_LSERDY              (1 << 9)  /* Bit 9:  External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP              (1 << 10) /* Bit 10: External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP              (1 << 10) /* Bit 10: External low-speed oscillator bypass */
-#define RCC_CSR_LSECSSON            (1 << 11) /* Bit 11: External Low Speed oscillator Ready */
+#define RCC_CSR_LSECSSON            (1 << 11) /* Bit 11: CSS on LSE enable */
-#define RCC_CSR_LSECSSD             (1 << 12) /* Bit 12: External Low Speed oscillator Ready */
+#define RCC_CSR_LSECSSD             (1 << 12) /* Bit 12: CSS on LSE failure Detection */
                                               /* Bits 13-15: Reserved */
-#define RCC_CSR_RTCSEL_SHIFT        (16)      /* Bits 16-17:  */
+#define RCC_CSR_RTCSEL_SHIFT        (16)      /* Bits 16-17: RTC and LCD clock source selection */
 #define RCC_CSR_RTCSEL_MASK         (3 << RCC_CSR_RTCSEL_SHIFT)
-#define RCC_CSR_RTCEN               (1 << 22) /* Bit 22:  */
+#  define RCC_CSR_RTCSEL_NONE       (0 << RCC_CSR_RTCSEL_SHIFT) /* 00: No clock */
-#define RCC_CSR_RTCRST              (1 << 23) /* Bit 23:  */
+#  define RCC_CSR_RTCSEL_LSE        (1 << RCC_CSR_RTCSEL_SHIFT) /* 01: LSE oscillator clock is RTC/LCD clock */
+#  define RCC_CSR_RTCSEL_LSI        (2 << RCC_CSR_RTCSEL_SHIFT) /* 10: LSI oscillator clock is RTC/LCD clock */
+#  define RCC_CSR_RTCSEL_HSE        (3 << RCC_CSR_RTCSEL_SHIFT) /* 11: Divided HSE oscillator clock is RTC/LCD clock */
+#define RCC_CSR_RTCEN               (1 << 22) /* Bit 22: RTC clock enable */
+#define RCC_CSR_RTCRST              (1 << 23) /* Bit 23: RTC software reset */
 #define RCC_CSR_RMVF                (1 << 24) /* Bit 24: Remove reset flag */
 #define RCC_CSR_OBLRSTF             (1 << 25) /* Bit 25: Option byte loader reset flag */
 #define RCC_CSR_PINRSTF             (1 << 26) /* Bit 26: PIN reset flag */

arch/arm/src/stm32/chip/stm32l15xxx_syscfg.h

@@ -0,0 +1,159 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/chip/stm32l15xxx_syscfg.h
+ * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
+ * 32-bit MCUs
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_SYSCFG_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+#define STM32_SYSCFG_MEMRMP_OFFSET     0x0000 /* SYSCFG memory remap register */
+#define STM32_SYSCFG_PMC_OFFSET        0x0004 /* SYSCFG peripheral mode configuration register */
+
+#define STM32_SYSCFG_EXTICR_OFFSET(p)  (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
+#define STM32_SYSCFG_EXTICR1_OFFSET    0x0008 /* SYSCFG external interrupt configuration register 1 */
+#define STM32_SYSCFG_EXTICR2_OFFSET    0x000c /* SYSCFG external interrupt configuration register 2 */
+#define STM32_SYSCFG_EXTICR3_OFFSET    0x0010 /* SYSCFG external interrupt configuration register 3 */
+#define STM32_SYSCFG_EXTICR4_OFFSET    0x0014 /* SYSCFG external interrupt configuration register 4 */
+
+/* Register Addresses *******************************************************************************/
+
+#define STM32_SYSCFG_MEMRMP            (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
+#define STM32_SYSCFG_PMC               (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
+
+#define STM32_SYSCFG_EXTICR(p)         (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
+#define STM32_SYSCFG_EXTICR1           (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
+#define STM32_SYSCFG_EXTICR2           (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
+#define STM32_SYSCFG_EXTICR3           (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
+#define STM32_SYSCFG_EXTICR4           (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
+
+/* Register Bitfield Definitions ********************************************************************/
+
+/* SYSCFG memory remap register */
+
+#define SYSCFG_MEMRMP_MEMMODE_SHIFT     (0)       /* Bits 0-1: Memory mapping selection */
+#define SYSCFG_MEMRMP_MEMMODE_MASK      (3 << SYSCFG_MEMRMP_MEMMODE_SHIFT)
+#  define SYSCFG_MEMRMP_MEMMODE_FLASH   (0 << SYSCFG_MEMRMP_MEMMODE_SHIFT) /* 00: Main Flash memory mapped at 0x00000000 */
+#  define SYSCFG_MEMRMP_MEMMODE_SYSTEM  (1 << SYSCFG_MEMRMP_MEMMODE_SHIFT) /* 01: System Flash memory mapped at 0x00000000 */
+#  define SYSCFG_MEMRMP_MEMMODE_FSMC    (2 << SYSCFG_MEMRMP_MEMMODE_SHIFT) /* 10: FSMC */
+#  define SYSCFG_MEMRMP_MEMMODE_SRAM    (3 << SYSCFG_MEMRMP_MEMMODE_SHIFT) /* 11: SRAM mapped at 0x00000000 */
+                                                  /* Bits 2-7: Reserved */
+#define SYSCFG_MEMRMP_BOOTMODE_SHIFT    (0)       /* Bits 8-9: Boot mode selected by the boot pins */
+#define SYSCFG_MEMRMP_BOOTMODE_MASK     (3 << SYSCFG_MEMRMP_BOOTMODE_SHIFT)
+#  define SYSCFG_MEMRMP_BOOTMODE_FLASH  (0 << SYSCFG_MEMRMP_BOOTMODE_SHIFT) /* 00: Main Flash memory boot mode */
+#  define SYSCFG_MEMRMP_BOOTMODE_SYSTEM (1 << SYSCFG_MEMRMP_BOOTMODE_SHIFT) /* 01: System Flash memory boot mode */
+#  define SYSCFG_MEMRMP_BOOTMODE_SRAM   (3 << SYSCFG_MEMRMP_BOOTMODE_SHIFT) /* 11: Embedded SRAM boot mode */
+                                                  /* Bits 10-31: Reserved */
+
+/* SYSCFG peripheral mode configuration register */
+
+#define SYSCFG_PMC_USBPU                (1 << 0)  /* Bit 0: USB pull-up enable on DP line */
+#define SYSCFG_PMC_LCDCAPA_SHIFT        (1)       /* Bits 1-5: LCD  decoupling capacitance connection */
+#define SYSCFG_PMC_LCDCAPA_MASK         (0x1f << SYSCFG_PMC_LCDCAPA_SHIFT)
+#  define SYSCFG_PMC_LCDCAPA_PB2        (0x01 << SYSCFG_PMC_LCDCAPA_SHIFT) /* Bit 1: Controls VLCDrail2 on PB2/LCD_VCAP2 */
+#  define SYSCFG_PMC_LCDCAPA_PB12       (0x02 << SYSCFG_PMC_LCDCAPA_SHIFT) /* Bit 2: Controls VLCDrail1 on PB12/LCD_VCAP1 */
+#  define SYSCFG_PMC_LCDCAPA_PB0        (0x04 << SYSCFG_PMC_LCDCAPA_SHIFT) /* Bit 3: Controls VLCDrail3 on PB0/LCD_VCAP3 */
+#  define SYSCFG_PMC_LCDCAPA_PE11       (0x08 << SYSCFG_PMC_LCDCAPA_SHIFT) /* Bit 4: Controls VLCDrail1 on PE11/LCD_VCAP1 */
+#  define SYSCFG_PMC_LCDCAPA_PE12       (0x10 << SYSCFG_PMC_LCDCAPA_SHIFT) /* Bit 5: Controls VLCDrail3 on PE12/LCD_VCAP3 */
+                                                  /* Bits 6-31: Reserved */
+
+/* SYSCFG external interrupt configuration register 1-4 */
+
+#define SYSCFG_EXTICR_PORTA           (0)       /* 0000: PA[x] pin */
+#define SYSCFG_EXTICR_PORTB           (1)       /* 0001: PB[x] pin */
+#define SYSCFG_EXTICR_PORTC           (2)       /* 0010: PC[x] pin */
+#define SYSCFG_EXTICR_PORTD           (3)       /* 0011: PD[x] pin */
+#define SYSCFG_EXTICR_PORTE           (4)       /* 0100: PE[x] pin */
+#define SYSCFG_EXTICR_PORTH           (5)       /* 0101: PH[x] pin */
+#define SYSCFG_EXTICR_PORTF           (6)       /* 0110: PF[x] pin */
+#define SYSCFG_EXTICR_PORTG           (7)       /* 0111: PG[x] pin */
+
+#define SYSCFG_EXTICR_PORT_MASK       (15)
+#define SYSCFG_EXTICR_EXTI_SHIFT(g)   (((g) & 3) << 2)
+#define SYSCFG_EXTICR_EXTI_MASK(g)    (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
+
+#define SYSCFG_EXTICR1_EXTI0_SHIFT    (0)       /* Bits 0-3: EXTI 0 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI0_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
+#define SYSCFG_EXTICR1_EXTI1_SHIFT    (4)       /* Bits 4-7: EXTI 1 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI1_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
+#define SYSCFG_EXTICR1_EXTI2_SHIFT    (8)       /* Bits 8-11: EXTI 2 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI2_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
+#define SYSCFG_EXTICR1_EXTI3_SHIFT    (12)      /* Bits 12-15: EXTI 3 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI3_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
+                                                /* Bits 16-31: Reserved */
+
+#define SYSCFG_EXTICR2_EXTI4_SHIFT    (0)       /* Bits 0-3: EXTI 4 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI4_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
+#define SYSCFG_EXTICR2_EXTI5_SHIFT    (4)       /* Bits 4-7: EXTI 5 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI5_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
+#define SYSCFG_EXTICR2_EXTI6_SHIFT    (8)       /* Bits 8-11: EXTI 6 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI6_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
+#define SYSCFG_EXTICR2_EXTI7_SHIFT    (12)      /* Bits 12-15: EXTI 7 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI7_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
+                                                /* Bits 16-31: Reserved */
+
+#define SYSCFG_EXTICR3_EXTI8_SHIFT    (0)       /* Bits 0-3: EXTI 8 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI8_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
+#define SYSCFG_EXTICR3_EXTI9_SHIFT    (4)       /* Bits 4-7: EXTI 9 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI9_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
+#define SYSCFG_EXTICR3_EXTI10_SHIFT   (8)       /* Bits 8-11: EXTI 10 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI10_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
+#define SYSCFG_EXTICR3_EXTI11_SHIFT   (12)      /* Bits 12-15: EXTI 11 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI11_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
+                                                /* Bits 16-31: Reserved */
+
+#define SYSCFG_EXTICR4_EXTI12_SHIFT   (0)       /* Bits 0-3: EXTI 12 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI12_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
+#define SYSCFG_EXTICR4_EXTI13_SHIFT   (4)       /* Bits 4-7: EXTI 13 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI13_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
+#define SYSCFG_EXTICR4_EXTI14_SHIFT   (8)       /* Bits 8-11: EXTI 14 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI14_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
+#define SYSCFG_EXTICR4_EXTI15_SHIFT   (12)      /* Bits 12-15: EXTI 15 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI15_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
+                                                /* Bits 16-31: Reserved */
+
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_SYSCFG_H */

arch/arm/src/stm32/stm32_gpio.h

@@ -291,7 +291,7 @@
 
 #define GPIO_SPEED_SHIFT              (10)                       /* Bits 10-11: GPIO frequency selection */
 #define GPIO_SPEED_MASK               (3 << GPIO_SPEED_SHIFT)
-#if define(CONFIG_STM32_STM32L15XX)
+#if defined(CONFIG_STM32_STM32L15XX)
 #  define GPIO_SPEED_400KHz           (0 << GPIO_SPEED_SHIFT)     /* 400 kHz Very low speed output */
 #  define GPIO_SPEED_2MHz             (1 << GPIO_SPEED_SHIFT)     /* 2 MHz Low speed output */
 #  define GPIO_SPEED_10MHz            (2 << GPIO_SPEED_SHIFT)     /* 10 MHz Medium speed output */

arch/arm/src/stm32/stm32_syscfg.h

@@ -43,7 +43,9 @@
 #include <nuttx/config.h>
 #include "chip.h"
 
-#if defined(CONFIG_STM32_STM32F20XX)
+#if defined(CONFIG_STM32_STM32L15XX)
+#  include "chip/stm32l15xxx_syscfg.h"
+#elif defined(CONFIG_STM32_STM32F20XX)
 #  include "chip/stm32f20xxx_syscfg.h"
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include "chip/stm32f30xxx_syscfg.h"

arch/arm/src/stm32/stm32_uart.h

@@ -53,7 +53,7 @@
 #elif defined(CONFIG_STM32_STM32F40XX)
 #  include "chip/stm32f40xxx_uart.h"
 #else
-#  error "Unsupported STM32 memory map"
+#  error "Unsupported STM32 UART"
 #endif
 
 /************************************************************************************