SAMA5: More cache and mmu inline utility functions
This commit is contained in:
Gregory Nutt
parent
36b1cd0a6b
commit
413aba0bf5
@ -193,6 +193,27 @@
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#ifdef __ASSEMBLY__
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/************************************************************************************
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* Name: cp15_disable_caches
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*
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* Description:
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* Disable L1 Caches
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_invalidate_icache_inner_sharable, tmp
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mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
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bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */
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bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */
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mcr p15, 0, \tmp, c1, c0, 0 /* Updagte the SCTLR */
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.endm
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/************************************************************************************
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* Name: cp15_invalidate_icache_inner_sharable
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*
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@ -440,6 +461,34 @@
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Name: cp15_disable_caches
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*
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* Description:
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* Disable L1 Caches
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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static inline void cp15_disable_caches(void)
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{
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__asm__ __volatile__
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(
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"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
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"\tbic r0, r0, #(0x1 << 12)\n" /* Disable I cache */
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"\tbic r0, r0, #(0x1 << 2)\n" /* Disable D cache */
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"\tmcr p15, 0, r0, c1, c0, 0\n" /* Updagte the SCTLR */
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:
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:
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: "r0", "memory"
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);
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}
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/************************************************************************************
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* Name: cp15_invalidate_icache_inner_sharable
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*
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@ -833,6 +882,22 @@ void cp15_coherent_dcache(uintptr_t start, uintptr_t end);
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void cp15_invalidate_dcache(uintptr_t start, uintptr_t end);
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/****************************************************************************
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* Name: cp15_invalidate_dcache_all
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*
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* Description:
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* Invalidate the entire contents of D cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void cp15_invalidate_dcache_all(void);
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/****************************************************************************
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* Name: cp15_clean_dcache
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*
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114
arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
Executable file
114
arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
Executable file
@ -0,0 +1,114 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
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* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
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* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
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* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
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* DDI 0406C.b (ID072512)
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*
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* Portions of this file derive from Atmel sample code for the SAMA5D3 Cortex-A5
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* which also has a modified BSD-style license:
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*
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* Copyright (c) 2012, Atmel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
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* be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "cp15.h"
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.file "cp15_invalidate_dcache_all.S"
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/****************************************************************************
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* Preprocessor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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.globl cp15_invalidate_dcache_all
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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.text
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/****************************************************************************
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* Name: cp15_invalidate_dcache_all
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*
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* Description:
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* Invalidate the entire contents of D cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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.globl cp15_invalidate_dcache_all
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.type cp15_invalidate_dcache_all, function
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cp15_invalidate_dcache_all:
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mrc CP15_CCSIDR(r0) /* Read the Cache Size Identification Register */
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ldr r3, =0xffff /* Isolate the NumSets field (bits 13-27) */
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and r0, r3, r0, lsr #13 /* r0=NumSets (number of sets - 1) */
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mov r1, #0 /* r1 = way loop counter */
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way_loop:
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mov r3, #0 /* r3 = set loop counter */
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set_loop:
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mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
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orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
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mcr CP15_DCISW(r2) /* Data Cache Invalidate by Set/Way */
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add r3, r3, #1 /* Increment set counter */
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cmp r0, r3 /* Last set? */
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bne set_loop /* Keep looping if not */
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add r1, r1, #1 /* Increment the way counter */
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cmp r1, #4 /* Last way? (four ways assumed) */
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bne way_loop /* Keep looping if not */
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dsb
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bx lr
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.size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all
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.end
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@ -793,6 +793,38 @@
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#ifdef __ASSEMBLY__
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/************************************************************************************
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* Name: cp15_disable_mmu
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*
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* Description:
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* Disable the MMU
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*
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* Inputs:
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* None
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*
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************************************************************************************/
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.macro cp15_disable_mmu, scratch
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mrc p15, 0, \scratch, c1, c0, 0
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bic \scratch, \scratch, #1
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mcr p15, 0, \scratch, c1, c0, 0
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.endm
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/************************************************************************************
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* Name: cp15_invalidate_tlbs
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*
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* Description:
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* Invalidate TLBs
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*
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* Inputs:
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* None
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*
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************************************************************************************/
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.macro cp15_invalidate_tlbs, scratch
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mcr p15, 0, \scratch, c8, c7, 0 /* TLBIALL */
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.endm
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/************************************************************************************
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* Name: cp15_wrdacr
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*
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@ -1000,13 +1032,51 @@
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#ifndef __ASSEMBLY__
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#endif /* __ASSEMBLY__ */
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/********************************************************************************************
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* Inline Functions
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/************************************************************************************
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* Name: cp15_disable_mmu
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*
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* Description:
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* Disable the MMU
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*
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* Inputs:
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* None
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*
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************************************************************************************/
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#ifndef __ASSEMBLY__
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static inline void cp15_disable_mmu(void)
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{
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__asm__ __volatile__
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(
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"\tmrc p15, 0, r0, c1, c0, 0\n"
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"\tbic r0, r0, #1\n"
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"\tmcr p15, 0, r0, c1, c0, 0\n"
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:
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:
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: "r0", "memory"
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);
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}
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/************************************************************************************
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* Name: cp15_invalidate_tlbs
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*
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* Description:
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* Invalidate TLBs
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*
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* Inputs:
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* None
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*
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************************************************************************************/
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static inline void cp15_invalidate_tlbs(void)
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{
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__asm__ __volatile__
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(
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"\tmcr p15, 0, r0, c8, c7, 0\n" /* TLBIALL */
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:
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:
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: "r0", "memory"
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);
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}
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/************************************************************************************
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* Name: cp15_wrdacr
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@ -39,7 +39,7 @@ CMN_ASRCS = arm_head.S
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CMN_ASRCS += arm_vectors.S arm_fpuconfig.S arm_fullcontextrestore.S
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CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S
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CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
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CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S
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CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
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CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c
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CMN_CSRCS += up_createstack.c up_releasestack.c up_usestack.c up_vfork.c
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@ -43,7 +43,8 @@
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#include <debug.h>
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#include "up_arch.h"
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#include "sctlr.h"
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#include "mmu.h"
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#include "cache.h"
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#include "sam_periphclks.h"
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#include "chip/sam_hsmc.h"
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@ -120,11 +121,15 @@ int nor_main(int argc, char *argv)
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* virtual addressing.
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*/
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#if 0 /* Causes a crash */
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printf("Disabling the caches and the MMU\n");
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regval = cp15_rdsctlr();
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regval &= ~(SCTLR_M | SCTLR_C | SCTLR_I);
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cp15_wrsctlr(regval);
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#if 0 /* Causes crashes */
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cp15_disable_mmu();
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cp15_disable_caches();
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/* Invalidate caches and TLBs */
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cp15_invalidate_icache();
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cp15_invalidate_dcache_all();
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cp15_invalidate_tlbs();
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#endif
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#ifdef SAMA5_NOR_START
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