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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3154 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-12-01 01:57:28 +00:00
parent 0bf49338d8
commit 41acdc6f92
2 changed files with 12 additions and 8 deletions
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10
configs/nucleus2g/include/board.h
View File

@ -64,10 +64,10 @@
* CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6
*/ */
#define LPC17_CCLK 80000000 /* 80Mhz*/ #define LPC17_CCLK 80000000 /* 80Mhz */
/* Select the main oscillator as the frequency source. SYSCLK is then the frequency /* Select the main oscillator as the frequency source. SYSCLK is then the frequency
* of the main osciallator. * of the main oscillator.
*/ */
#undef CONFIG_LPC17_MAINOSC #undef CONFIG_LPC17_MAINOSC
@ -86,6 +86,8 @@
* Source clock: Main oscillator * Source clock: Main oscillator
* PLL0 Multiplier value (M): 20 * PLL0 Multiplier value (M): 20
* PLL0 Pre-divider value (N): 1 * PLL0 Pre-divider value (N): 1
*
* PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz
*/ */
#undef CONFIG_LPC17_PLL0 #undef CONFIG_LPC17_PLL0
@ -107,8 +109,8 @@
(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \ (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \
((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT)) ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT))
/* USB divider. This divder is used when PLL1 is not enabled to get the USB clock /* USB divider. This divider is used when PLL1 is not enabled to get the
* from PLL0: * USB clock from PLL0:
* *
* USBCLK = PLL0CLK / 10 = 48MHz * USBCLK = PLL0CLK / 10 = 48MHz
*/ */

10
configs/olimex-lpc1766stk/include/board.h
View File

@ -65,10 +65,10 @@
* CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6
*/ */
#define LPC17_CCLK 80000000 /* 80Mhz*/ #define LPC17_CCLK 80000000 /* 80Mhz */
/* Select the main oscillator as the frequency source. SYSCLK is then the frequency /* Select the main oscillator as the frequency source. SYSCLK is then the frequency
* of the main osciallator. * of the main oscillator.
*/ */
#undef CONFIG_LPC17_MAINOSC #undef CONFIG_LPC17_MAINOSC
@ -87,6 +87,8 @@
* Source clock: Main oscillator * Source clock: Main oscillator
* PLL0 Multiplier value (M): 20 * PLL0 Multiplier value (M): 20
* PLL0 Pre-divider value (N): 1 * PLL0 Pre-divider value (N): 1
*
* PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz
*/ */
#undef CONFIG_LPC17_PLL0 #undef CONFIG_LPC17_PLL0
@ -108,8 +110,8 @@
(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \ (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \
((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT)) ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT))
/* USB divider. This divder is used when PLL1 is not enabled to get the USB clock /* USB divider. This divider is used when PLL1 is not enabled to get the
* from PLL0: * USB clock from PLL0:
* *
* USBCLK = PLL0CLK / 10 = 48MHz * USBCLK = PLL0CLK / 10 = 48MHz
*/ */