From 41b4af1ec31e430bcfa330e1aa6ab2d0405d86e6 Mon Sep 17 00:00:00 2001 From: Fotis Panagiotopoulos Date: Tue, 27 Sep 2022 17:24:21 +0300 Subject: [PATCH] Style fixes. --- boards/arm/lpc31xx/ea3131/src/lpc31_mem.c | 12 ++++++------ boards/arm/lpc31xx/ea3152/src/lpc31_mem.c | 12 ++++++------ boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c | 4 ++-- boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c | 4 ++-- boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c | 4 ++-- 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c b/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c index 5c235d3cfb..edd0bdcdb3 100644 --- a/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c +++ b/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c @@ -103,12 +103,12 @@ * pin), the SDRAM requires a 100µs delay prior to issuing any command * other than a COMMAND INHIBIT or NOP. * - * "Starting at some point during this 100µs period and continuing at least - * through the end of this period, COMMAND INHIBIT or NOP commands should - * be applied. Once the 100µs delay has been satisfied with at least one - * COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command - * should be applied. All banks must then be precharged, thereby placing - * the device in the all banks idle state. + * "Starting at some point during this 100µs period and continuing at + * least through the end of this period, COMMAND INHIBIT or NOP commands + * should be applied. Once the 100µs delay has been satisfied with at + * least one COMMAND INHIBIT or NOP command having been applied, a + * PRECHARGE command should be applied. All banks must then be precharged, + * thereby placing the device in the all banks idle state. * * "Once in the idle state, two AUTO REFRESH cycles must be performed. * After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode diff --git a/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c b/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c index 7e9eca4867..b7b94cf60b 100644 --- a/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c +++ b/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c @@ -103,12 +103,12 @@ * pin), the SDRAM requires a 100µs delay prior to issuing any command * other than a COMMAND INHIBIT or NOP. * - * "Starting at some point during this 100µs period and continuing at least - * through the end of this period, COMMAND INHIBIT or NOP commands should - * be applied. Once the 100µs delay has been satisfied with at least one - * COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command - * should be applied. All banks must then be precharged, thereby placing - * the device in the all banks idle state. + * "Starting at some point during this 100µs period and continuing at + * least through the end of this period, COMMAND INHIBIT or NOP commands + * should be applied. Once the 100µs delay has been satisfied with at + * least one COMMAND INHIBIT or NOP command having been applied, a + * PRECHARGE command should be applied. All banks must then be precharged, + * thereby placing the device in the all banks idle state. * * "Once in the idle state, two AUTO REFRESH cycles must be performed. * After the AUTO REFRESH cycles are complete, the SDRAM is ready for diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c b/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c index c2f971d96c..39bd08c6dd 100644 --- a/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c +++ b/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c @@ -166,8 +166,8 @@ void weak_function sam_netinitialize(void) * (MICREL KSZ9021/31) operating at 10/100/1000 Mbps. * The board supports RGMII interface mode. * The Ethernet interface consists of 4 pairs of low voltage differential - * pair signals designated from GRX± and GTx± plus control signals for link - * activity indicators. These signals can be used to connect to a + * pair signals designated from GRX± and GTx± plus control signals for + * link activity indicators. These signals can be used to connect to a * 10/100/1000 BaseT RJ45 connector integrated on the main board. * * The KSZ9021/31 interrupt is available on PB35 INT_GETH0 diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c b/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c index ae3250e0fe..c272fb23e2 100644 --- a/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c +++ b/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c @@ -137,8 +137,8 @@ static inline void sam_sdram_delay(unsigned int loops) * Per the SAMA5D3-Xplained User guide: * "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte). * The board includes 2 Gbits of on-board soldered DDR2 (double data rate) - * SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from Micron® - * for a total of 512 MBytes of DDR2 memory. + * SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from + * Micron® for a total of 512 MBytes of DDR2 memory. * The memory bus is 32 bits wide and operates with a frequency of up * to 166 MHz." * diff --git a/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c b/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c index 85008aab2f..4223f03dfb 100644 --- a/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c +++ b/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c @@ -166,8 +166,8 @@ void weak_function sam_netinitialize(void) * (MICREL KSZ9021/31) operating at 10/100/1000 Mbps. * The board supports RGMII interface mode. * The Ethernet interface consists of 4 pairs of low voltage differential - * pair signals designated from GRX± and GTx± plus control signals for link - * activity indicators. These signals can be used to connect to a + * pair signals designated from GRX± and GTx± plus control signals for + * link activity indicators. These signals can be used to connect to a * 10/100/1000 BaseT RJ45 connector integrated on the main board. * * The KSZ9021/31 interrupt is available on PB35 INT_GETH0