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Style fixes.

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Fotis Panagiotopoulos 2022-09-27 17:24:21 +03:00 committed by Xiang Xiao
parent bbf3f2866d
commit 41b4af1ec3
5 changed files with 18 additions and 18 deletions
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12
boards/arm/lpc31xx/ea3131/src/lpc31_mem.c
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@ -103,12 +103,12 @@
* pin), the SDRAM requires a 100µs delay prior to issuing any command * pin), the SDRAM requires a 100µs delay prior to issuing any command
* other than a COMMAND INHIBIT or NOP. * other than a COMMAND INHIBIT or NOP.
* *
* "Starting at some point during this 100µs period and continuing at least * "Starting at some point during this 100µs period and continuing at
* through the end of this period, COMMAND INHIBIT or NOP commands should * least through the end of this period, COMMAND INHIBIT or NOP commands
* be applied. Once the 100µs delay has been satisfied with at least one * should be applied. Once the 100µs delay has been satisfied with at
* COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command * least one COMMAND INHIBIT or NOP command having been applied, a
* should be applied. All banks must then be precharged, thereby placing * PRECHARGE command should be applied. All banks must then be precharged,
* the device in the all banks idle state. * thereby placing the device in the all banks idle state.
* *
* "Once in the idle state, two AUTO REFRESH cycles must be performed. * "Once in the idle state, two AUTO REFRESH cycles must be performed.
* After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode * After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode

12
boards/arm/lpc31xx/ea3152/src/lpc31_mem.c
View File

@ -103,12 +103,12 @@
* pin), the SDRAM requires a 100µs delay prior to issuing any command * pin), the SDRAM requires a 100µs delay prior to issuing any command
* other than a COMMAND INHIBIT or NOP. * other than a COMMAND INHIBIT or NOP.
* *
* "Starting at some point during this 100µs period and continuing at least * "Starting at some point during this 100µs period and continuing at
* through the end of this period, COMMAND INHIBIT or NOP commands should * least through the end of this period, COMMAND INHIBIT or NOP commands
* be applied. Once the 100µs delay has been satisfied with at least one * should be applied. Once the 100µs delay has been satisfied with at
* COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command * least one COMMAND INHIBIT or NOP command having been applied, a
* should be applied. All banks must then be precharged, thereby placing * PRECHARGE command should be applied. All banks must then be precharged,
* the device in the all banks idle state. * thereby placing the device in the all banks idle state.
* *
* "Once in the idle state, two AUTO REFRESH cycles must be performed. * "Once in the idle state, two AUTO REFRESH cycles must be performed.
* After the AUTO REFRESH cycles are complete, the SDRAM is ready for * After the AUTO REFRESH cycles are complete, the SDRAM is ready for

4
boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c
View File

@ -166,8 +166,8 @@ void weak_function sam_netinitialize(void)
* (MICREL KSZ9021/31) operating at 10/100/1000 Mbps. * (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
* The board supports RGMII interface mode. * The board supports RGMII interface mode.
* The Ethernet interface consists of 4 pairs of low voltage differential * The Ethernet interface consists of 4 pairs of low voltage differential
* pair signals designated from GRX± and GTx± plus control signals for link * pair signals designated from GRX± and GTx± plus control signals for
* activity indicators. These signals can be used to connect to a * link activity indicators. These signals can be used to connect to a
* 10/100/1000 BaseT RJ45 connector integrated on the main board. * 10/100/1000 BaseT RJ45 connector integrated on the main board.
* *
* The KSZ9021/31 interrupt is available on PB35 INT_GETH0 * The KSZ9021/31 interrupt is available on PB35 INT_GETH0

4
boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c
View File

@ -137,8 +137,8 @@ static inline void sam_sdram_delay(unsigned int loops)
* Per the SAMA5D3-Xplained User guide: * Per the SAMA5D3-Xplained User guide:
* "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte). * "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte).
* The board includes 2 Gbits of on-board soldered DDR2 (double data rate) * The board includes 2 Gbits of on-board soldered DDR2 (double data rate)
* SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from Micron® * SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from
* for a total of 512 MBytes of DDR2 memory. * Micron® for a total of 512 MBytes of DDR2 memory.
* The memory bus is 32 bits wide and operates with a frequency of up * The memory bus is 32 bits wide and operates with a frequency of up
* to 166 MHz." * to 166 MHz."
* *

4
boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c
View File

@ -166,8 +166,8 @@ void weak_function sam_netinitialize(void)
* (MICREL KSZ9021/31) operating at 10/100/1000 Mbps. * (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
* The board supports RGMII interface mode. * The board supports RGMII interface mode.
* The Ethernet interface consists of 4 pairs of low voltage differential * The Ethernet interface consists of 4 pairs of low voltage differential
* pair signals designated from GRX± and GTx± plus control signals for link * pair signals designated from GRX± and GTx± plus control signals for
* activity indicators. These signals can be used to connect to a * link activity indicators. These signals can be used to connect to a
* 10/100/1000 BaseT RJ45 connector integrated on the main board. * 10/100/1000 BaseT RJ45 connector integrated on the main board.
* *
* The KSZ9021/31 interrupt is available on PB35 INT_GETH0 * The KSZ9021/31 interrupt is available on PB35 INT_GETH0