From 41b56a5f099b685345fa8671b4a91c515fd94b33 Mon Sep 17 00:00:00 2001 From: Dave Marples Date: Thu, 18 Feb 2016 19:07:33 -0600 Subject: [PATCH] Enable the Ethernet for the LPC4330 and autonegotiation when the MAC is a LAN8720. --- arch/arm/src/lpc43xx/Kconfig | 10 + arch/arm/src/lpc43xx/Make.defs | 12 +- .../lpc43xx/chip/lpc4310203050_pinconfig.h | 64 +- arch/arm/src/lpc43xx/chip/lpc43_ccu.h | 554 +++++++++--------- arch/arm/src/lpc43xx/lpc43_cgu.c | 32 + arch/arm/src/lpc43xx/lpc43_config.h | 6 +- arch/arm/src/lpc43xx/lpc43_ethernet.c | 81 ++- arch/arm/src/lpc43xx/lpc43_serial.c | 2 + arch/arm/src/lpc43xx/lpc43_ssp.c | 5 +- arch/arm/src/lpc43xx/lpc43_uart.c | 4 + arch/arm/src/lpc43xx/lpc43_usb0dev.c | 7 + arch/arm/src/lpc43xx/lpc43_usb0dev.h | 1 - 12 files changed, 442 insertions(+), 336 deletions(-) diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig index e3655a47b2..dc38841309 100644 --- a/arch/arm/src/lpc43xx/Kconfig +++ b/arch/arm/src/lpc43xx/Kconfig @@ -488,10 +488,20 @@ config LPC43_USB0 bool "USB0" default n +config LPC43_USB0DEV_NOVBUS + bool "No USB0 VBUS sensing" + default n + depends on LPC43_USB0 + config LPC43_USB1 bool "USB1" default n +config LPC43_USB1DEV_NOVBUS + bool "No USB1 VBUS sensing" + default n + depends on LPC43_USB1 + config LPC43_USB1_ULPI bool "USB1 with ULPI" default n diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs index 29bf2e316f..2ec9699554 100644 --- a/arch/arm/src/lpc43xx/Make.defs +++ b/arch/arm/src/lpc43xx/Make.defs @@ -128,6 +128,14 @@ endif ifeq ($(CONFIG_LPC43_SPI),y) CHIP_CSRCS += lpc43_spi.c +else +ifeq ($(CONFIG_LPC43_SSP0),y) +CHIP_CSRCS += lpc43_spi.c +else +ifeq ($(CONFIG_LPC43_SSP1),y) +CHIP_CSRCS += lpc43_spi.c +endif +endif endif ifeq ($(CONFIG_LPC43_SPIFI),y) @@ -135,10 +143,10 @@ CHIP_CSRCS += lpc43_spifi.c endif ifeq ($(CONFIG_LPC43_SSP0),y) -CHIP_CSRCS += lpc43_ssp.c lpc43_spi.c +CHIP_CSRCS += lpc43_ssp.c else ifeq ($(CONFIG_LPC43_SSP1),y) -CHIP_CSRCS += lpc43_ssp.c lpc43_spi.c +CHIP_CSRCS += lpc43_ssp.c endif endif diff --git a/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h index 118acebec6..708ecfa862 100644 --- a/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h +++ b/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h @@ -271,38 +271,38 @@ #define PINCONF_EMC_RAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_5) #define PINCONF_EMC_WE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_6) -#define PINCONF_ENET_COL_1 (PINCONF_FUNC2|PINCONF_PINS0|PINCONF_PIN_1) -#define PINCONF_ENET_COL_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_6) -#define PINCONF_ENET_COL_3 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_1) -#define PINCONF_ENET_CRS_1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_16) -#define PINCONF_ENET_CRS_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_0) -#define PINCONF_ENET_MDC_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_1) -#define PINCONF_ENET_MDC_2 (PINCONF_FUNC6|PINCONF_PINS7|PINCONF_PIN_7) -#define PINCONF_ENET_MDC_3 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_0) -#define PINCONF_ENET_MDIO (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_17) -#define PINCONF_ENET_REF_CLK (PINCONF_FUNC0|PINCONF_PINS1|PINCONF_PIN_19) -#define PINCONF_ENET_RXD0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_15) -#define PINCONF_ENET_RXD1 (PINCONF_FUNC2|PINCONF_PINS0|PINCONF_PIN_0) -#define PINCONF_ENET_RXD2_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_6) -#define PINCONF_ENET_RXD2_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_3) -#define PINCONF_ENET_RXD3_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_7) -#define PINCONF_ENET_RXD3_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_2) -#define PINCONF_ENET_RX_CLK (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_0) -#define PINCONF_ENET_RX_DV_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_8) -#define PINCONF_ENET_RX_DV_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_16) -#define PINCONF_ENET_RX_ER_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_9) -#define PINCONF_ENET_RX_ER_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_1) -#define PINCONF_ENET_TXD0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_18) -#define PINCONF_ENET_TXD1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_20) -#define PINCONF_ENET_TXD2_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_2) -#define PINCONF_ENET_TXD2_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_4) -#define PINCONF_ENET_TXD3_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_3) -#define PINCONF_ENET_TXD3_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_5) -#define PINCONF_ENET_TXEN (PINCONF_FUNC6|PINCONF_PINS0|PINCONF_PIN_1) -#define PINCONF_ENET_TX_CLK (PINCONF_FUNC0|PINCONF_PINS1|PINCONF_PIN_19) -#define PINCONF_ENET_TX_EN (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_4) -#define PINCONF_ENET_TX_ER_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_5) -#define PINCONF_ENET_TX_ER_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_14) +#define PINCONF_ENET_COL_1 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS0|PINCONF_PIN_1) +#define PINCONF_ENET_COL_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_6) +#define PINCONF_ENET_COL_3 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS4|PINCONF_PIN_1) +#define PINCONF_ENET_CRS_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_16) +#define PINCONF_ENET_CRS_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_0) +#define PINCONF_ENET_MDC_1 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_1) +#define PINCONF_ENET_MDC_2 (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_PINS7|PINCONF_PIN_7) +#define PINCONF_ENET_MDC_3 (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_0) +#define PINCONF_ENET_MDIO (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_17) +#define PINCONF_ENET_REF_CLK (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_19) +#define PINCONF_ENET_RXD0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_15) +#define PINCONF_ENET_RXD1 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS0|PINCONF_PIN_0) +#define PINCONF_ENET_RXD2_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_6) +#define PINCONF_ENET_RXD2_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_3) +#define PINCONF_ENET_RXD3_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_7) +#define PINCONF_ENET_RXD3_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_2) +#define PINCONF_ENET_RX_CLK (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_0) +#define PINCONF_ENET_RX_DV_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_8) +#define PINCONF_ENET_RX_DV_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_16) +#define PINCONF_ENET_RX_ER_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_9) +#define PINCONF_ENET_RX_ER_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_1) +#define PINCONF_ENET_TXD0 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_18) +#define PINCONF_ENET_TXD1 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_20) +#define PINCONF_ENET_TXD2_1 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_2) +#define PINCONF_ENET_TXD2_2 (PINCONF_FUNC5|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_4) +#define PINCONF_ENET_TXD3_1 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_3) +#define PINCONF_ENET_TXD3_2 (PINCONF_FUNC5|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_5) +#define PINCONF_ENET_TXEN (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_PINS0|PINCONF_PIN_1) +#define PINCONF_ENET_TX_CLK (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_19) +#define PINCONF_ENET_TX_EN (PINCONF_FUNC3|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_4) +#define PINCONF_ENET_TX_ER_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_5) +#define PINCONF_ENET_TX_ER_2 (PINCONF_FUNC6|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_14) #define PINCONF_GPIO0p0 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_0) #define PINCONF_GPIO0p1 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_1) diff --git a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h b/arch/arm/src/lpc43xx/chip/lpc43_ccu.h index ff7b4c9ab7..a2cb20ca62 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_ccu.h @@ -47,299 +47,301 @@ ****************************************************************************************************/ /* Register Offsets *********************************************************************************/ -#define LPC43_CCU1_PM_OFFSET 0x0000 /* CCU1 power mode register */ -#define LPC43_CCU1_BASE_STAT_OFFSET 0x0004 /* CCU1 base clock status register */ -#define LPC43_CCU1_APB3_BUS_CFG_OFFSET 0x0100 /* CLK_APB3_BUS clock configuration register */ -#define LPC43_CCU1_APB3_BUS_STAT_OFFSET 0x0104 /* CLK_APB3_BUS clock status register */ -#define LPC43_CCU1_APB3_I2C1_CFG_OFFSET 0x0108 /* CLK_APB3_I2C1 configuration register */ -#define LPC43_CCU1_APB3_I2C1_STAT_OFFSET 0x010c /* CLK_APB3_I2C1 status register */ -#define LPC43_CCU1_APB3_DAC_CFG_OFFSET 0x0110 /* CLK_APB3_DAC configuration register */ -#define LPC43_CCU1_APB3_DAC_STAT_OFFSET 0x0114 /* CLK_APB3_DAC status register */ -#define LPC43_CCU1_APB3_ADC0_CFG_OFFSET 0x0118 /* CLK_APB3_ADC0 configuration register */ -#define LPC43_CCU1_APB3_ADC0_STAT_OFFSET 0x011c /* CLK_APB3_ADC0 status register */ -#define LPC43_CCU1_APB3_ADC1_CFG_OFFSET 0x0120 /* CLK_APB3_ADC1 configuration register */ -#define LPC43_CCU1_APB3_ADC1_STAT_OFFSET 0x0124 /* CLK_APB3_ADC1 status register */ -#define LPC43_CCU1_APB3_CAN0_CFG_OFFSET 0x0128 /* CLK_APB3_CAN0 configuration register */ -#define LPC43_CCU1_APB3_CAN0_STAT_OFFSET 0x012c /* CLK_APB3_CAN0 status register */ -#define LPC43_CCU1_APB1_BUS_CFG_OFFSET 0x0200 /* CLK_APB1_BUS configuration register */ -#define LPC43_CCU1_APB1_BUS_STAT_OFFSET 0x0204 /* CLK_APB1_BUS status register */ -#define LPC43_CCU1_APB1_MCPWM_CFG_OFFSET 0x0208 /* CLK_APB1_MOTOCON configuration register */ -#define LPC43_CCU1_APB1_MCPWM_STAT_OFFSET 0x020c /* CLK_APB1_MOTOCON status register */ -#define LPC43_CCU1_APB1_I2C0_CFG_OFFSET 0x0210 /* CLK_APB1_I2C0 configuration register */ -#define LPC43_CCU1_APB1_I2C0_STAT_OFFSET 0x0214 /* CLK_APB1_I2C0 status register */ -#define LPC43_CCU1_APB1_I2S_CFG_OFFSET 0x0218 /* CLK_APB1_I2S configuration register */ -#define LPC43_CCU1_APB1_I2S_STAT_OFFSET 0x021c /* CLK_APB1_I2S status register */ -#define LPC43_CCU1_APB1_CAN1_CFG_OFFSET 0x0220 /* CLK_APB3_CAN1 configuration register */ -#define LPC43_CCU1_APB1_CAN1_STAT_OFFSET 0x0224 /* CLK_APB3_CAN1 status register */ -#define LPC43_CCU1_SPIFI_CFG_OFFSET 0x0300 /* CLK_SPIFI configuration register */ -#define LPC43_CCU1_SPIFI_STAT_OFFSET 0x0304 /* CLK_SPIFI status register */ -#define LPC43_CCU1_M4_BUS_CFG_OFFSET 0x0400 /* CLK_M4_BUS configuration register */ -#define LPC43_CCU1_M4_BUS_STAT_OFFSET 0x0404 /* CLK_M4_BUS status register */ -#define LPC43_CCU1_M4_SPIFI_CFG_OFFSET 0x0408 /* CLK_M4_SPIFI configuration register */ -#define LPC43_CCU1_M4_SPIFI_STAT_OFFSET 0x040c /* CLK_M4_SPIFI status register */ -#define LPC43_CCU1_M4_GPIO_CFG_OFFSET 0x0410 /* CLK_M4_GPIO configuration register */ -#define LPC43_CCU1_M4_GPIO_STAT_OFFSET 0x0414 /* CLK_M4_GPIO status register */ -#define LPC43_CCU1_M4_LCD_CFG_OFFSET 0x0418 /* CLK_M4_LCD configuration register */ -#define LPC43_CCU1_M4_LCD_STAT_OFFSET 0x041c /* CLK_M4_LCD status register */ -#define LPC43_CCU1_M4_ETHERNET_CFG_OFFSET 0x0420 /* CLK_M4_ETHERNET configuration register */ -#define LPC43_CCU1_M4_ETHERNET_STAT_OFFSET 0x0424 /* CLK_M4_ETHERNET status register */ -#define LPC43_CCU1_M4_USB0_CFG_OFFSET 0x0428 /* CLK_M4_USB0 configuration register */ -#define LPC43_CCU1_M4_USB0_STAT_OFFSET 0x042c /* CLK_M4_USB0 status register */ -#define LPC43_CCU1_M4_EMC_CFG_OFFSET 0x0430 /* CLK_M4_EMC configuration register */ -#define LPC43_CCU1_M4_EMC_STAT_OFFSET 0x0434 /* CLK_M4_EMC status register */ -#define LPC43_CCU1_M4_SDIO_CFG_OFFSET 0x0438 /* CLK_M4_SDIO configuration register */ -#define LPC43_CCU1_M4_SDIO_STAT_OFFSET 0x043c /* CLK_M4_SDIO status register */ -#define LPC43_CCU1_M4_DMA_CFG_OFFSET 0x0440 /* CLK_M4_DMA configuration register */ -#define LPC43_CCU1_M4_DMA_STAT_OFFSET 0x0444 /* CLK_M4_DMA status register */ -#define LPC43_CCU1_M4_M4CORE_CFG_OFFSET 0x0448 /* CLK_M4_M4CORE configuration register */ -#define LPC43_CCU1_M4_M4CORE_STAT_OFFSET 0x044c /* CLK_M4_M4CORE status register */ -#define LPC43_CCU1_M4_SCT_CFG_OFFSET 0x0468 /* CLK_M4_SCT configuration register */ -#define LPC43_CCU1_M4_SCT_STAT_OFFSET 0x046c /* CLK_M4_SCT status register */ -#define LPC43_CCU1_M4_USB1_CFG_OFFSET 0x0470 /* CLK_M4_USB1 configuration register */ -#define LPC43_CCU1_M4_USB1_STAT_OFFSET 0x0474 /* CLK_M4_USB1 status register */ -#define LPC43_CCU1_M4_EMCDIV_CFG_OFFSET 0x0478 /* CLK_M4_EMCDIV configuration register */ -#define LPC43_CCU1_M4_EMCDIV_STAT_OFFSET 0x047c /* CLK_M4_EMCDIV status register */ -#define LPC43_CCU1_M4_FLASHA_CFG_OFFSET 0x0480 /* CLK_M4_FLASHA configuration register */ -#define LPC43_CCU1_M4_FLASHA_STAT_OFFSET 0x0484 /* CLK_M4_FLASHA status register */ -#define LPC43_CCU1_M4_FLASHB_CFG_OFFSET 0x0488 /* CLK_M4_FLASHB configuration register */ -#define LPC43_CCU1_M4_FLASHB_STAT_OFFSET 0x048c /* CLK_M4_FLASHB status register */ -#define LPC43_CCU1_M4_M0APP_CFG_OFFSET 0x0490 /* CLK_M4_M0_CFG configuration register */ -#define LPC43_CCU1_M4_M0APP_STAT_OFFSET 0x0494 /* CLK_M4_M0_STAT status register */ -#define LPC43_CCU1_M4_VADC_CFG_OFFSET 0x0498 /* CLK_M4_VADC_CFG configuration register */ -#define LPC43_CCU1_M4_VADC_STAT_OFFSET 0x049c /* CLK_M4_VADC_STAT configuration register */ -#define LPC43_CCU1_M4_EEPROM_CFG_OFFSET 0x04a0 /* CLK_M4_EEPROM configuration register */ -#define LPC43_CCU1_M4_EEPROM_STAT_OFFSET 0x04a4 /* CLK_M4_EEPROM status register */ -#define LPC43_CCU1_M4_WWDT_CFG_OFFSET 0x0500 /* CLK_M4_WWDT configuration register */ -#define LPC43_CCU1_M4_WWDT_STAT_OFFSET 0x0504 /* CLK_M4_WWDT status register */ -#define LPC43_CCU1_M4_USART0_CFG_OFFSET 0x0508 /* CLK_M4_USART0 configuration register */ -#define LPC43_CCU1_M4_USART0_STAT_OFFSET 0x050c /* CLK_M4_USART0 status register */ -#define LPC43_CCU1_M4_UART1_CFG_OFFSET 0x0510 /* CLK_M4_UART1 configuration register */ -#define LPC43_CCU1_M4_UART1_STAT_OFFSET 0x0514 /* CLK_M4_UART1 status register */ -#define LPC43_CCU1_M4_SSP0_CFG_OFFSET 0x0518 /* CLK_M4_SSP0 configuration register */ -#define LPC43_CCU1_M4_SSP0_STAT_OFFSET 0x051c /* CLK_M4_SSP0 status register */ -#define LPC43_CCU1_M4_TIMER0_CFG_OFFSET 0x0520 /* CLK_M4_TIMER0 configuration register */ -#define LPC43_CCU1_M4_TIMER0_STAT_OFFSET 0x0524 /* CLK_M4_TIMER0 status register */ -#define LPC43_CCU1_M4_TIMER1_CFG_OFFSET 0x0528 /* CLK_M4_TIMER1 configuration register */ -#define LPC43_CCU1_M4_TIMER1_STAT_OFFSET 0x052c /* CLK_M4_TIMER1 status register */ -#define LPC43_CCU1_M4_SCU_CFG_OFFSET 0x0530 /* CLK_M4_SCU configuration register */ -#define LPC43_CCU1_M4_SCU_STAT_OFFSET 0x0534 /* CLK_M4_SCU status register */ -#define LPC43_CCU1_M4_CREG_CFG_OFFSET 0x0538 /* CLK_M4_CREG configuration register */ -#define LPC43_CCU1_M4_CREG_STAT_OFFSET 0x053c /* CLK_M4_CREG status register */ -#define LPC43_CCU1_M4_RITIMER_CFG_OFFSET 0x0600 /* CLK_M4_RITIMER configuration register */ -#define LPC43_CCU1_M4_RITIMER_STAT_OFFSET 0x0604 /* CLK_M4_RITIMER status register */ -#define LPC43_CCU1_M4_USART2_CFG_OFFSET 0x0608 /* CLK_M4_USART2 configuration register */ -#define LPC43_CCU1_M4_USART2_STAT_OFFSET 0x060c /* CLK_M4_USART2 status register */ -#define LPC43_CCU1_M4_USART3_CFG_OFFSET 0x0610 /* CLK_M4_USART3 configuration register */ -#define LPC43_CCU1_M4_USART3_STAT_OFFSET 0x0614 /* CLK_M4_USART3 status register */ -#define LPC43_CCU1_M4_TIMER2_CFG_OFFSET 0x0618 /* CLK_M4_TIMER2 configuration register */ -#define LPC43_CCU1_M4_TIMER2_STAT_OFFSET 0x061c /* CLK_M4_TIMER2 status register */ -#define LPC43_CCU1_M4_TIMER3_CFG_OFFSET 0x0620 /* CLK_M4_TIMER3 configuration register */ -#define LPC43_CCU1_M4_TIMER3_STAT_OFFSET 0x0624 /* CLK_M4_TIMER3 status register */ -#define LPC43_CCU1_M4_SSP1_CFG_OFFSET 0x0628 /* CLK_M4_SSP1 configuration register */ -#define LPC43_CCU1_M4_SSP1_STAT_OFFSET 0x062c /* CLK_M4_SSP1 status register */ -#define LPC43_CCU1_M4_QEI_CFG_OFFSET 0x0630 /* CLK_M4_QEI configuration register */ -#define LPC43_CCU1_M4_QEI_STAT_OFFSET 0x0634 /* CLK_M4_QEI status register */ -#define LPC43_CCU1_PERIPH_BUS_CFG_OFFSET 0x0700 /* CLK_PERIPH_BUS configuration register */ -#define LPC43_CCU1_PERIPH_BUS_STAT_OFFSET 0x0704 /* CLK_PERIPH_BUS status register */ -#define LPC43_CCU1_PERIPH_CORE_CFG_OFFSET 0x0710 /* CLK_PERIPH_CORE configuration register */ -#define LPC43_CCU1_PERIPH_CORE_STAT_OFFSET 0x0714 /* CLK_PERIPH_CORE status register */ -#define LPC43_CCU1_PERIPH_SGPIO_CFG_OFFSET 0x0718 /* CLK_PERIPH_SGPIO configuration register */ -#define LPC43_CCU1_PERIPH_SGPIO_STAT_OFFSET 0x071c /* CLK_PERIPH_SGPIO status register */ -#define LPC43_CCU1_USB0_CFG_OFFSET 0x0800 /* CLK_USB0 configuration register */ -#define LPC43_CCU1_USB0_STAT_OFFSET 0x0804 /* CLK_USB0 status register */ -#define LPC43_CCU1_USB1_CFG_OFFSET 0x0900 /* CLK_USB1 configuration register */ -#define LPC43_CCU1_USB1_STAT_OFFSET 0x0904 /* CLK_USB1 status register */ -#define LPC43_CCU1_SPI_CFG_OFFSET 0x0a00 /* CLK_SPI configuration register */ -#define LPC43_CCU1_SPI_STAT_OFFSET 0x0a04 /* CLK_SPI status register */ -#define LPC43_CCU1_VADC_CFG_OFFSET 0x0b00 /* CLK_VADC configuration register */ -#define LPC43_CCU1_VADC_STAT_OFFSET 0x0b04 /* CLK_VADC status register */ +#define LPC43_CCU1_PM_OFFSET 0x0000 /* CCU1 power mode register */ +#define LPC43_CCU1_BASE_STAT_OFFSET 0x0004 /* CCU1 base clock status register */ +#define LPC43_CCU1_APB3_BUS_CFG_OFFSET 0x0100 /* CLK_APB3_BUS clock configuration register */ +#define LPC43_CCU1_APB3_BUS_STAT_OFFSET 0x0104 /* CLK_APB3_BUS clock status register */ +#define LPC43_CCU1_APB3_I2C1_CFG_OFFSET 0x0108 /* CLK_APB3_I2C1 configuration register */ +#define LPC43_CCU1_APB3_I2C1_STAT_OFFSET 0x010c /* CLK_APB3_I2C1 status register */ +#define LPC43_CCU1_APB3_DAC_CFG_OFFSET 0x0110 /* CLK_APB3_DAC configuration register */ +#define LPC43_CCU1_APB3_DAC_STAT_OFFSET 0x0114 /* CLK_APB3_DAC status register */ +#define LPC43_CCU1_APB3_ADC0_CFG_OFFSET 0x0118 /* CLK_APB3_ADC0 configuration register */ +#define LPC43_CCU1_APB3_ADC0_STAT_OFFSET 0x011c /* CLK_APB3_ADC0 status register */ +#define LPC43_CCU1_APB3_ADC1_CFG_OFFSET 0x0120 /* CLK_APB3_ADC1 configuration register */ +#define LPC43_CCU1_APB3_ADC1_STAT_OFFSET 0x0124 /* CLK_APB3_ADC1 status register */ +#define LPC43_CCU1_APB3_CAN0_CFG_OFFSET 0x0128 /* CLK_APB3_CAN0 configuration register */ +#define LPC43_CCU1_APB3_CAN0_STAT_OFFSET 0x012c /* CLK_APB3_CAN0 status register */ +#define LPC43_CCU1_APB1_BUS_CFG_OFFSET 0x0200 /* CLK_APB1_BUS configuration register */ +#define LPC43_CCU1_APB1_BUS_STAT_OFFSET 0x0204 /* CLK_APB1_BUS status register */ +#define LPC43_CCU1_APB1_MCPWM_CFG_OFFSET 0x0208 /* CLK_APB1_MOTOCON configuration register */ +#define LPC43_CCU1_APB1_MCPWM_STAT_OFFSET 0x020c /* CLK_APB1_MOTOCON status register */ +#define LPC43_CCU1_APB1_I2C0_CFG_OFFSET 0x0210 /* CLK_APB1_I2C0 configuration register */ +#define LPC43_CCU1_APB1_I2C0_STAT_OFFSET 0x0214 /* CLK_APB1_I2C0 status register */ +#define LPC43_CCU1_APB1_I2S_CFG_OFFSET 0x0218 /* CLK_APB1_I2S configuration register */ +#define LPC43_CCU1_APB1_I2S_STAT_OFFSET 0x021c /* CLK_APB1_I2S status register */ +#define LPC43_CCU1_APB1_CAN1_CFG_OFFSET 0x0220 /* CLK_APB3_CAN1 configuration register */ +#define LPC43_CCU1_APB1_CAN1_STAT_OFFSET 0x0224 /* CLK_APB3_CAN1 status register */ +#define LPC43_CCU1_SPIFI_CFG_OFFSET 0x0300 /* CLK_SPIFI configuration register */ +#define LPC43_CCU1_SPIFI_STAT_OFFSET 0x0304 /* CLK_SPIFI status register */ +#define LPC43_CCU1_M4_BUS_CFG_OFFSET 0x0400 /* CLK_M4_BUS configuration register */ +#define LPC43_CCU1_M4_BUS_STAT_OFFSET 0x0404 /* CLK_M4_BUS status register */ +#define LPC43_CCU1_M4_SPIFI_CFG_OFFSET 0x0408 /* CLK_M4_SPIFI configuration register */ +#define LPC43_CCU1_M4_SPIFI_STAT_OFFSET 0x040c /* CLK_M4_SPIFI status register */ +#define LPC43_CCU1_M4_GPIO_CFG_OFFSET 0x0410 /* CLK_M4_GPIO configuration register */ +#define LPC43_CCU1_M4_GPIO_STAT_OFFSET 0x0414 /* CLK_M4_GPIO status register */ +#define LPC43_CCU1_M4_LCD_CFG_OFFSET 0x0418 /* CLK_M4_LCD configuration register */ +#define LPC43_CCU1_M4_LCD_STAT_OFFSET 0x041c /* CLK_M4_LCD status register */ +#define LPC43_CCU1_M4_ETHERNET_CFG_OFFSET 0x0420 /* CLK_M4_ETHERNET configuration register */ +#define LPC43_CCU1_M4_ETHERNET_STAT_OFFSET 0x0424 /* CLK_M4_ETHERNET status register */ +#define LPC43_CCU1_M4_USB0_CFG_OFFSET 0x0428 /* CLK_M4_USB0 configuration register */ +#define LPC43_CCU1_M4_USB0_STAT_OFFSET 0x042c /* CLK_M4_USB0 status register */ +#define LPC43_CCU1_M4_EMC_CFG_OFFSET 0x0430 /* CLK_M4_EMC configuration register */ +#define LPC43_CCU1_M4_EMC_STAT_OFFSET 0x0434 /* CLK_M4_EMC status register */ +#define LPC43_CCU1_M4_SDIO_CFG_OFFSET 0x0438 /* CLK_M4_SDIO configuration register */ +#define LPC43_CCU1_M4_SDIO_STAT_OFFSET 0x043c /* CLK_M4_SDIO status register */ +#define LPC43_CCU1_M4_DMA_CFG_OFFSET 0x0440 /* CLK_M4_DMA configuration register */ +#define LPC43_CCU1_M4_DMA_STAT_OFFSET 0x0444 /* CLK_M4_DMA status register */ +#define LPC43_CCU1_M4_M4CORE_CFG_OFFSET 0x0448 /* CLK_M4_M4CORE configuration register */ +#define LPC43_CCU1_M4_M4CORE_STAT_OFFSET 0x044c /* CLK_M4_M4CORE status register */ +#define LPC43_CCU1_M4_SCT_CFG_OFFSET 0x0468 /* CLK_M4_SCT configuration register */ +#define LPC43_CCU1_M4_SCT_STAT_OFFSET 0x046c /* CLK_M4_SCT status register */ +#define LPC43_CCU1_M4_USB1_CFG_OFFSET 0x0470 /* CLK_M4_USB1 configuration register */ +#define LPC43_CCU1_M4_USB1_STAT_OFFSET 0x0474 /* CLK_M4_USB1 status register */ +#define LPC43_CCU1_M4_EMCDIV_CFG_OFFSET 0x0478 /* CLK_M4_EMCDIV configuration register */ +#define LPC43_CCU1_M4_EMCDIV_STAT_OFFSET 0x047c /* CLK_M4_EMCDIV status register */ +#define LPC43_CCU1_M4_FLASHA_CFG_OFFSET 0x0480 /* CLK_M4_FLASHA configuration register */ +#define LPC43_CCU1_M4_FLASHA_STAT_OFFSET 0x0484 /* CLK_M4_FLASHA status register */ +#define LPC43_CCU1_M4_FLASHB_CFG_OFFSET 0x0488 /* CLK_M4_FLASHB configuration register */ +#define LPC43_CCU1_M4_FLASHB_STAT_OFFSET 0x048c /* CLK_M4_FLASHB status register */ +#define LPC43_CCU1_M4_M0APP_CFG_OFFSET 0x0490 /* CLK_M4_M0_CFG configuration register */ +#define LPC43_CCU1_M4_M0APP_STAT_OFFSET 0x0494 /* CLK_M4_M0_STAT status register */ +#define LPC43_CCU1_M4_VADC_CFG_OFFSET 0x0498 /* CLK_M4_VADC_CFG configuration register */ +#define LPC43_CCU1_M4_VADC_STAT_OFFSET 0x049c /* CLK_M4_VADC_STAT configuration register */ +#define LPC43_CCU1_M4_EEPROM_CFG_OFFSET 0x04a0 /* CLK_M4_EEPROM configuration register */ +#define LPC43_CCU1_M4_EEPROM_STAT_OFFSET 0x04a4 /* CLK_M4_EEPROM status register */ +#define LPC43_CCU1_M4_WWDT_CFG_OFFSET 0x0500 /* CLK_M4_WWDT configuration register */ +#define LPC43_CCU1_M4_WWDT_STAT_OFFSET 0x0504 /* CLK_M4_WWDT status register */ +#define LPC43_CCU1_M4_USART0_CFG_OFFSET 0x0508 /* CLK_M4_USART0 configuration register */ +#define LPC43_CCU1_M4_USART0_STAT_OFFSET 0x050c /* CLK_M4_USART0 status register */ +#define LPC43_CCU1_M4_UART1_CFG_OFFSET 0x0510 /* CLK_M4_UART1 configuration register */ +#define LPC43_CCU1_M4_UART1_STAT_OFFSET 0x0514 /* CLK_M4_UART1 status register */ +#define LPC43_CCU1_M4_SSP0_CFG_OFFSET 0x0518 /* CLK_M4_SSP0 configuration register */ +#define LPC43_CCU1_M4_SSP0_STAT_OFFSET 0x051c /* CLK_M4_SSP0 status register */ +#define LPC43_CCU1_M4_TIMER0_CFG_OFFSET 0x0520 /* CLK_M4_TIMER0 configuration register */ +#define LPC43_CCU1_M4_TIMER0_STAT_OFFSET 0x0524 /* CLK_M4_TIMER0 status register */ +#define LPC43_CCU1_M4_TIMER1_CFG_OFFSET 0x0528 /* CLK_M4_TIMER1 configuration register */ +#define LPC43_CCU1_M4_TIMER1_STAT_OFFSET 0x052c /* CLK_M4_TIMER1 status register */ +#define LPC43_CCU1_M4_SCU_CFG_OFFSET 0x0530 /* CLK_M4_SCU configuration register */ +#define LPC43_CCU1_M4_SCU_STAT_OFFSET 0x0534 /* CLK_M4_SCU status register */ +#define LPC43_CCU1_M4_CREG_CFG_OFFSET 0x0538 /* CLK_M4_CREG configuration register */ +#define LPC43_CCU1_M4_CREG_STAT_OFFSET 0x053c /* CLK_M4_CREG status register */ +#define LPC43_CCU1_M4_UART1_RS485CTRL_OFFSET 0x054c /* CLK_M4_UART1 RS485 Control register */ +#define LPC43_CCU1_M4_RITIMER_CFG_OFFSET 0x0600 /* CLK_M4_RITIMER configuration register */ +#define LPC43_CCU1_M4_RITIMER_STAT_OFFSET 0x0604 /* CLK_M4_RITIMER status register */ +#define LPC43_CCU1_M4_USART2_CFG_OFFSET 0x0608 /* CLK_M4_USART2 configuration register */ +#define LPC43_CCU1_M4_USART2_STAT_OFFSET 0x060c /* CLK_M4_USART2 status register */ +#define LPC43_CCU1_M4_USART3_CFG_OFFSET 0x0610 /* CLK_M4_USART3 configuration register */ +#define LPC43_CCU1_M4_USART3_STAT_OFFSET 0x0614 /* CLK_M4_USART3 status register */ +#define LPC43_CCU1_M4_TIMER2_CFG_OFFSET 0x0618 /* CLK_M4_TIMER2 configuration register */ +#define LPC43_CCU1_M4_TIMER2_STAT_OFFSET 0x061c /* CLK_M4_TIMER2 status register */ +#define LPC43_CCU1_M4_TIMER3_CFG_OFFSET 0x0620 /* CLK_M4_TIMER3 configuration register */ +#define LPC43_CCU1_M4_TIMER3_STAT_OFFSET 0x0624 /* CLK_M4_TIMER3 status register */ +#define LPC43_CCU1_M4_SSP1_CFG_OFFSET 0x0628 /* CLK_M4_SSP1 configuration register */ +#define LPC43_CCU1_M4_SSP1_STAT_OFFSET 0x062c /* CLK_M4_SSP1 status register */ +#define LPC43_CCU1_M4_QEI_CFG_OFFSET 0x0630 /* CLK_M4_QEI configuration register */ +#define LPC43_CCU1_M4_QEI_STAT_OFFSET 0x0634 /* CLK_M4_QEI status register */ +#define LPC43_CCU1_PERIPH_BUS_CFG_OFFSET 0x0700 /* CLK_PERIPH_BUS configuration register */ +#define LPC43_CCU1_PERIPH_BUS_STAT_OFFSET 0x0704 /* CLK_PERIPH_BUS status register */ +#define LPC43_CCU1_PERIPH_CORE_CFG_OFFSET 0x0710 /* CLK_PERIPH_CORE configuration register */ +#define LPC43_CCU1_PERIPH_CORE_STAT_OFFSET 0x0714 /* CLK_PERIPH_CORE status register */ +#define LPC43_CCU1_PERIPH_SGPIO_CFG_OFFSET 0x0718 /* CLK_PERIPH_SGPIO configuration register */ +#define LPC43_CCU1_PERIPH_SGPIO_STAT_OFFSET 0x071c /* CLK_PERIPH_SGPIO status register */ +#define LPC43_CCU1_USB0_CFG_OFFSET 0x0800 /* CLK_USB0 configuration register */ +#define LPC43_CCU1_USB0_STAT_OFFSET 0x0804 /* CLK_USB0 status register */ +#define LPC43_CCU1_USB1_CFG_OFFSET 0x0900 /* CLK_USB1 configuration register */ +#define LPC43_CCU1_USB1_STAT_OFFSET 0x0904 /* CLK_USB1 status register */ +#define LPC43_CCU1_SPI_CFG_OFFSET 0x0a00 /* CLK_SPI configuration register */ +#define LPC43_CCU1_SPI_STAT_OFFSET 0x0a04 /* CLK_SPI status register */ +#define LPC43_CCU1_VADC_CFG_OFFSET 0x0b00 /* CLK_VADC configuration register */ +#define LPC43_CCU1_VADC_STAT_OFFSET 0x0b04 /* CLK_VADC status register */ -#define LPC43_CCU2_PM_OFFSET 0x0000 /* CCU2 power mode register */ -#define LPC43_CCU2_BASE_STAT_OFFSET 0x0004 /* CCU2 base clocks status register */ -#define LPC43_CCU2_APLL_CFG_OFFSET 0x0100 /* CLK_APLL configuration register */ -#define LPC43_CCU2_APLL_STAT_OFFSET 0x0104 /* CLK_APLL status register */ -#define LPC43_CCU2_APB2_USART3_CFG_OFFSET 0x0200 /* CLK_APB2_USART3 configuration register */ -#define LPC43_CCU2_APB2_USART3_STAT_OFFSET 0x0204 /* CLK_APB2_USART3 status register */ -#define LPC43_CCU2_APB2_USART2_CFG_OFFSET 0x0300 /* CLK_APB2_USART2 configuration register */ -#define LPC43_CCU2_APB2_USART2_STAT_OFFSET 0x0304 /* CLK_APB2_USART2 status register */ -#define LPC43_CCU2_APB0_UART1_CFG_OFFSET 0x0400 /* CLK_APB0_UART1 configuration register */ -#define LPC43_CCU2_APB0_UART1_STAT_OFFSET 0x0404 /* CLK_APB0_UART1 status register */ -#define LPC43_CCU2_APB0_USART0_CFG_OFFSET 0x0500 /* CLK_APB0_USART0 configuration register */ -#define LPC43_CCU2_APB0_USART0_STAT_OFFSET 0x0504 /* CLK_APB0_USART0 status register */ -#define LPC43_CCU2_APB2_SSP1_CFG_OFFSET 0x0600 /* CLK_APB2_SSP1 configuration register */ -#define LPC43_CCU2_APB2_SSP1_STAT_OFFSET 0x0604 /* CLK_APB2_SSP1 status register */ -#define LPC43_CCU2_APB0_SSP0_CFG_OFFSET 0x0700 /* CLK_APB0_SSP0 configuration register */ -#define LPC43_CCU2_APB0_SSP0_STAT_OFFSET 0x0704 /* CLK_APB0_SSP0 status register */ -#define LPC43_CCU2_SDIO_CFG_OFFSET 0x0800 /* CLK_SDIO configuration register (for SD/MMC) */ -#define LPC43_CCU2_SDIO_STAT_OFFSET 0x0804 /* CLK_SDIO status register (for SD/MMC) */ +#define LPC43_CCU2_PM_OFFSET 0x0000 /* CCU2 power mode register */ +#define LPC43_CCU2_BASE_STAT_OFFSET 0x0004 /* CCU2 base clocks status register */ +#define LPC43_CCU2_APLL_CFG_OFFSET 0x0100 /* CLK_APLL configuration register */ +#define LPC43_CCU2_APLL_STAT_OFFSET 0x0104 /* CLK_APLL status register */ +#define LPC43_CCU2_APB2_USART3_CFG_OFFSET 0x0200 /* CLK_APB2_USART3 configuration register */ +#define LPC43_CCU2_APB2_USART3_STAT_OFFSET 0x0204 /* CLK_APB2_USART3 status register */ +#define LPC43_CCU2_APB2_USART2_CFG_OFFSET 0x0300 /* CLK_APB2_USART2 configuration register */ +#define LPC43_CCU2_APB2_USART2_STAT_OFFSET 0x0304 /* CLK_APB2_USART2 status register */ +#define LPC43_CCU2_APB0_UART1_CFG_OFFSET 0x0400 /* CLK_APB0_UART1 configuration register */ +#define LPC43_CCU2_APB0_UART1_STAT_OFFSET 0x0404 /* CLK_APB0_UART1 status register */ +#define LPC43_CCU2_APB0_USART0_CFG_OFFSET 0x0500 /* CLK_APB0_USART0 configuration register */ +#define LPC43_CCU2_APB0_USART0_STAT_OFFSET 0x0504 /* CLK_APB0_USART0 status register */ +#define LPC43_CCU2_APB2_SSP1_CFG_OFFSET 0x0600 /* CLK_APB2_SSP1 configuration register */ +#define LPC43_CCU2_APB2_SSP1_STAT_OFFSET 0x0604 /* CLK_APB2_SSP1 status register */ +#define LPC43_CCU2_APB0_SSP0_CFG_OFFSET 0x0700 /* CLK_APB0_SSP0 configuration register */ +#define LPC43_CCU2_APB0_SSP0_STAT_OFFSET 0x0704 /* CLK_APB0_SSP0 status register */ +#define LPC43_CCU2_SDIO_CFG_OFFSET 0x0800 /* CLK_SDIO configuration register (for SD/MMC) */ +#define LPC43_CCU2_SDIO_STAT_OFFSET 0x0804 /* CLK_SDIO status register (for SD/MMC) */ /* Register Addresses *******************************************************************************/ -#define LPC43_CCU1_PM (LPC43_CCU1_BASE+LPC43_CCU1_PM_OFFSET) -#define LPC43_CCU1_BASE_STAT (LPC43_CCU1_BASE+LPC43_CCU1_BASE_STAT_OFFSET) -#define LPC43_CCU1_APB3_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_BUS_CFG_OFFSET) -#define LPC43_CCU1_APB3_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_BUS_STAT_OFFSET) -#define LPC43_CCU1_APB3_I2C1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_I2C1_CFG_OFFSET) -#define LPC43_CCU1_APB3_I2C1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_I2C1_STAT_OFFSET) -#define LPC43_CCU1_APB3_DAC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_DAC_CFG_OFFSET) -#define LPC43_CCU1_APB3_DAC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_DAC_STAT_OFFSET) -#define LPC43_CCU1_APB3_ADC0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC0_CFG_OFFSET) -#define LPC43_CCU1_APB3_ADC0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC0_STAT_OFFSET) -#define LPC43_CCU1_APB3_ADC1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC1_CFG_OFFSET) -#define LPC43_CCU1_APB3_ADC1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC1_STAT_OFFSET) -#define LPC43_CCU1_APB3_CAN0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_CAN0_CFG_OFFSET) -#define LPC43_CCU1_APB3_CAN0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_CAN0_STAT_OFFSET) -#define LPC43_CCU1_APB1_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_BUS_CFG_OFFSET) -#define LPC43_CCU1_APB1_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_BUS_STAT_OFFSET) -#define LPC43_CCU1_APB1_MCPWM_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_MCPWM_CFG_OFFSET) -#define LPC43_CCU1_APB1_MCPWM_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_MCPWM_STAT_OFFSET) -#define LPC43_CCU1_APB1_I2C0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2C0_CFG_OFFSET) -#define LPC43_CCU1_APB1_I2C0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2C0_STAT_OFFSET) -#define LPC43_CCU1_APB1_I2S_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2S_CFG_OFFSET) -#define LPC43_CCU1_APB1_I2S_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2S_STAT_OFFSET) -#define LPC43_CCU1_APB1_CAN1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_CAN1_CFG_OFFSET) -#define LPC43_CCU1_APB1_CAN1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_CAN1_STAT_OFFSET) -#define LPC43_CCU1_SPIFI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_SPIFI_CFG_OFFSET) -#define LPC43_CCU1_SPIFI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_SPIFI_STAT_OFFSET) -#define LPC43_CCU1_M4_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_BUS_CFG_OFFSET) -#define LPC43_CCU1_M4_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_BUS_STAT_OFFSET) -#define LPC43_CCU1_M4_SPIFI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SPIFI_CFG_OFFSET) -#define LPC43_CCU1_M4_SPIFI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SPIFI_STAT_OFFSET) -#define LPC43_CCU1_M4_GPIO_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_GPIO_CFG_OFFSET) -#define LPC43_CCU1_M4_GPIO_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_GPIO_STAT_OFFSET) -#define LPC43_CCU1_M4_LCD_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_LCD_CFG_OFFSET) -#define LPC43_CCU1_M4_LCD_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_LCD_STAT_OFFSET) -#define LPC43_CCU1_M4_ETHERNET_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_ETHERNET_CFG_OFFSET) -#define LPC43_CCU1_M4_ETHERNET_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_ETHERNET_STAT_OFFSET) -#define LPC43_CCU1_M4_USB0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB0_CFG_OFFSET) -#define LPC43_CCU1_M4_USB0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB0_STAT_OFFSET) -#define LPC43_CCU1_M4_EMC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMC_CFG_OFFSET) -#define LPC43_CCU1_M4_EMC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMC_STAT_OFFSET) -#define LPC43_CCU1_M4_SDIO_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SDIO_CFG_OFFSET) -#define LPC43_CCU1_M4_SDIO_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SDIO_STAT_OFFSET) -#define LPC43_CCU1_M4_DMA_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_DMA_CFG_OFFSET) -#define LPC43_CCU1_M4_DMA_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_DMA_STAT_OFFSET) -#define LPC43_CCU1_M4_M4CORE_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_M4CORE_CFG_OFFSET) -#define LPC43_CCU1_M4_M4CORE_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_M4CORE_STAT_OFFSET) -#define LPC43_CCU1_M4_SCT_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCT_CFG_OFFSET) -#define LPC43_CCU1_M4_SCT_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCT_STAT_OFFSET) -#define LPC43_CCU1_M4_USB1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB1_CFG_OFFSET) -#define LPC43_CCU1_M4_USB1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB1_STAT_OFFSET) -#define LPC43_CCU1_M4_EMCDIV_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMCDIV_CFG_OFFSET) -#define LPC43_CCU1_M4_EMCDIV_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMCDIV_STAT_OFFSET) -#define LPC43_CCU1_M4_FLASHA_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHA_CFG_OFFSET) -#define LPC43_CCU1_M4_FLASHA_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHA_STAT_OFFSET) -#define LPC43_CCU1_M4_FLASHB_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHB_CFG_OFFSET) -#define LPC43_CCU1_M4_FLASHB_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHB_STAT_OFFSET) -#define LPC43_CCU1_M4_M0APP_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_M0APP_CFG_OFFSET) -#define LPC43_CCU1_M4_M0APP_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_M0APP_STAT_OFFSET) -#define LPC43_CCU1_M4_VADC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_VADC_CFG_OFFSET) -#define LPC43_CCU1_M4_VADC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_VADC_STAT_OFFSET) -#define LPC43_CCU1_M4_EEPROM_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_EEPROM_CFG_OFFSET) -#define LPC43_CCU1_M4_EEPROM_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_EEPROM_STAT_OFFSET) -#define LPC43_CCU1_M4_WWDT_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_WWDT_CFG_OFFSET) -#define LPC43_CCU1_M4_WWDT_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_WWDT_STAT_OFFSET) -#define LPC43_CCU1_M4_USART0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART0_CFG_OFFSET) -#define LPC43_CCU1_M4_USART0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART0_STAT_OFFSET) -#define LPC43_CCU1_M4_UART1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_UART1_CFG_OFFSET) -#define LPC43_CCU1_M4_UART1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_UART1_STAT_OFFSET) -#define LPC43_CCU1_M4_SSP0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP0_CFG_OFFSET) -#define LPC43_CCU1_M4_SSP0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP0_STAT_OFFSET) -#define LPC43_CCU1_M4_TIMER0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER0_CFG_OFFSET) -#define LPC43_CCU1_M4_TIMER0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER0_STAT_OFFSET) -#define LPC43_CCU1_M4_TIMER1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER1_CFG_OFFSET) -#define LPC43_CCU1_M4_TIMER1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER1_STAT_OFFSET) -#define LPC43_CCU1_M4_SCU_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCU_CFG_OFFSET) -#define LPC43_CCU1_M4_SCU_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCU_STAT_OFFSET) -#define LPC43_CCU1_M4_CREG_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_CFG_OFFSET) -#define LPC43_CCU1_M4_CREG_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_STAT_OFFSET) -#define LPC43_CCU1_M4_RITIMER_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_CFG_OFFSET) -#define LPC43_CCU1_M4_RITIMER_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_STAT_OFFSET) -#define LPC43_CCU1_M4_USART2_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART2_CFG_OFFSET) -#define LPC43_CCU1_M4_USART2_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART2_STAT_OFFSET) -#define LPC43_CCU1_M4_USART3_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART3_CFG_OFFSET) -#define LPC43_CCU1_M4_USART3_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART3_STAT_OFFSET) -#define LPC43_CCU1_M4_TIMER2_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER2_CFG_OFFSET) -#define LPC43_CCU1_M4_TIMER2_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER2_STAT_OFFSET) -#define LPC43_CCU1_M4_TIMER3_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER3_CFG_OFFSET) -#define LPC43_CCU1_M4_TIMER3_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER3_STAT_OFFSET) -#define LPC43_CCU1_M4_SSP1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP1_CFG_OFFSET) -#define LPC43_CCU1_M4_SSP1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP1_STAT_OFFSET) -#define LPC43_CCU1_M4_QEI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_QEI_CFG_OFFSET) -#define LPC43_CCU1_M4_QEI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_QEI_STAT_OFFSET) -#define LPC43_CCU1_PERIPH_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_BUS_CFG_OFFSET) -#define LPC43_CCU1_PERIPH_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_BUS_STAT_OFFSET) -#define LPC43_CCU1_PERIPH_CORE_CFG (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_CORE_CFG_OFFSET) -#define LPC43_CCU1_PERIPH_CORE_STAT (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_CORE_STAT_OFFSET) -#define LPC43_CCU1_PERIPH_SGPIO_CFG (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_SGPIO_CFG_OFFSET) -#define LPC43_CCU1_PERIPH_SGPIO_STAT (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_SGPIO_STAT_OFFSET) -#define LPC43_CCU1_USB0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_USB0_CFG_OFFSET) -#define LPC43_CCU1_USB0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_USB0_STAT_OFFSET) -#define LPC43_CCU1_USB1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_USB1_CFG_OFFSET) -#define LPC43_CCU1_USB1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_USB1_STAT_OFFSET) -#define LPC43_CCU1_SPI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_SPI_CFG_OFFSET) -#define LPC43_CCU1_SPI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_SPI_STAT_OFFSET) -#define LPC43_CCU1_VADC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_VADC_CFG_OFFSET) -#define LPC43_CCU1_VADC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_VADC_STAT_OFFSET) +#define LPC43_CCU1_PM (LPC43_CCU1_BASE+LPC43_CCU1_PM_OFFSET) +#define LPC43_CCU1_BASE_STAT (LPC43_CCU1_BASE+LPC43_CCU1_BASE_STAT_OFFSET) +#define LPC43_CCU1_APB3_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_BUS_CFG_OFFSET) +#define LPC43_CCU1_APB3_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_BUS_STAT_OFFSET) +#define LPC43_CCU1_APB3_I2C1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_I2C1_CFG_OFFSET) +#define LPC43_CCU1_APB3_I2C1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_I2C1_STAT_OFFSET) +#define LPC43_CCU1_APB3_DAC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_DAC_CFG_OFFSET) +#define LPC43_CCU1_APB3_DAC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_DAC_STAT_OFFSET) +#define LPC43_CCU1_APB3_ADC0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC0_CFG_OFFSET) +#define LPC43_CCU1_APB3_ADC0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC0_STAT_OFFSET) +#define LPC43_CCU1_APB3_ADC1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC1_CFG_OFFSET) +#define LPC43_CCU1_APB3_ADC1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC1_STAT_OFFSET) +#define LPC43_CCU1_APB3_CAN0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_CAN0_CFG_OFFSET) +#define LPC43_CCU1_APB3_CAN0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_CAN0_STAT_OFFSET) +#define LPC43_CCU1_APB1_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_BUS_CFG_OFFSET) +#define LPC43_CCU1_APB1_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_BUS_STAT_OFFSET) +#define LPC43_CCU1_APB1_MCPWM_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_MCPWM_CFG_OFFSET) +#define LPC43_CCU1_APB1_MCPWM_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_MCPWM_STAT_OFFSET) +#define LPC43_CCU1_APB1_I2C0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2C0_CFG_OFFSET) +#define LPC43_CCU1_APB1_I2C0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2C0_STAT_OFFSET) +#define LPC43_CCU1_APB1_I2S_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2S_CFG_OFFSET) +#define LPC43_CCU1_APB1_I2S_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2S_STAT_OFFSET) +#define LPC43_CCU1_APB1_CAN1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_CAN1_CFG_OFFSET) +#define LPC43_CCU1_APB1_CAN1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_CAN1_STAT_OFFSET) +#define LPC43_CCU1_SPIFI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_SPIFI_CFG_OFFSET) +#define LPC43_CCU1_SPIFI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_SPIFI_STAT_OFFSET) +#define LPC43_CCU1_M4_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_BUS_CFG_OFFSET) +#define LPC43_CCU1_M4_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_BUS_STAT_OFFSET) +#define LPC43_CCU1_M4_SPIFI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SPIFI_CFG_OFFSET) +#define LPC43_CCU1_M4_SPIFI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SPIFI_STAT_OFFSET) +#define LPC43_CCU1_M4_GPIO_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_GPIO_CFG_OFFSET) +#define LPC43_CCU1_M4_GPIO_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_GPIO_STAT_OFFSET) +#define LPC43_CCU1_M4_LCD_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_LCD_CFG_OFFSET) +#define LPC43_CCU1_M4_LCD_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_LCD_STAT_OFFSET) +#define LPC43_CCU1_M4_ETHERNET_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_ETHERNET_CFG_OFFSET) +#define LPC43_CCU1_M4_ETHERNET_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_ETHERNET_STAT_OFFSET) +#define LPC43_CCU1_M4_USB0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB0_CFG_OFFSET) +#define LPC43_CCU1_M4_USB0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB0_STAT_OFFSET) +#define LPC43_CCU1_M4_EMC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMC_CFG_OFFSET) +#define LPC43_CCU1_M4_EMC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMC_STAT_OFFSET) +#define LPC43_CCU1_M4_SDIO_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SDIO_CFG_OFFSET) +#define LPC43_CCU1_M4_SDIO_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SDIO_STAT_OFFSET) +#define LPC43_CCU1_M4_DMA_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_DMA_CFG_OFFSET) +#define LPC43_CCU1_M4_DMA_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_DMA_STAT_OFFSET) +#define LPC43_CCU1_M4_M4CORE_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_M4CORE_CFG_OFFSET) +#define LPC43_CCU1_M4_M4CORE_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_M4CORE_STAT_OFFSET) +#define LPC43_CCU1_M4_SCT_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCT_CFG_OFFSET) +#define LPC43_CCU1_M4_SCT_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCT_STAT_OFFSET) +#define LPC43_CCU1_M4_USB1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB1_CFG_OFFSET) +#define LPC43_CCU1_M4_USB1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB1_STAT_OFFSET) +#define LPC43_CCU1_M4_EMCDIV_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMCDIV_CFG_OFFSET) +#define LPC43_CCU1_M4_EMCDIV_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMCDIV_STAT_OFFSET) +#define LPC43_CCU1_M4_FLASHA_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHA_CFG_OFFSET) +#define LPC43_CCU1_M4_FLASHA_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHA_STAT_OFFSET) +#define LPC43_CCU1_M4_FLASHB_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHB_CFG_OFFSET) +#define LPC43_CCU1_M4_FLASHB_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHB_STAT_OFFSET) +#define LPC43_CCU1_M4_M0APP_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_M0APP_CFG_OFFSET) +#define LPC43_CCU1_M4_M0APP_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_M0APP_STAT_OFFSET) +#define LPC43_CCU1_M4_VADC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_VADC_CFG_OFFSET) +#define LPC43_CCU1_M4_VADC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_VADC_STAT_OFFSET) +#define LPC43_CCU1_M4_EEPROM_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_EEPROM_CFG_OFFSET) +#define LPC43_CCU1_M4_EEPROM_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_EEPROM_STAT_OFFSET) +#define LPC43_CCU1_M4_WWDT_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_WWDT_CFG_OFFSET) +#define LPC43_CCU1_M4_WWDT_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_WWDT_STAT_OFFSET) +#define LPC43_CCU1_M4_USART0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART0_CFG_OFFSET) +#define LPC43_CCU1_M4_USART0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART0_STAT_OFFSET) +#define LPC43_CCU1_M4_UART1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_UART1_CFG_OFFSET) +#define LPC43_CCU1_M4_UART1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_UART1_STAT_OFFSET) +#define LPC43_CCU1_M4_SSP0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP0_CFG_OFFSET) +#define LPC43_CCU1_M4_SSP0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP0_STAT_OFFSET) +#define LPC43_CCU1_M4_TIMER0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER0_CFG_OFFSET) +#define LPC43_CCU1_M4_TIMER0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER0_STAT_OFFSET) +#define LPC43_CCU1_M4_TIMER1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER1_CFG_OFFSET) +#define LPC43_CCU1_M4_TIMER1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER1_STAT_OFFSET) +#define LPC43_CCU1_M4_SCU_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCU_CFG_OFFSET) +#define LPC43_CCU1_M4_SCU_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCU_STAT_OFFSET) +#define LPC43_CCU1_M4_CREG_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_CFG_OFFSET) +#define LPC43_CCU1_M4_CREG_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_STAT_OFFSET) +#define LPC43_CCU1_M4_UART1_RS485CTRL (LPC43_CCU1_BASE+LPC43_CCU1_M4_UART1_RS485CTRL_OFFSET) +#define LPC43_CCU1_M4_RITIMER_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_CFG_OFFSET) +#define LPC43_CCU1_M4_RITIMER_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_STAT_OFFSET) +#define LPC43_CCU1_M4_USART2_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART2_CFG_OFFSET) +#define LPC43_CCU1_M4_USART2_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART2_STAT_OFFSET) +#define LPC43_CCU1_M4_USART3_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART3_CFG_OFFSET) +#define LPC43_CCU1_M4_USART3_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART3_STAT_OFFSET) +#define LPC43_CCU1_M4_TIMER2_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER2_CFG_OFFSET) +#define LPC43_CCU1_M4_TIMER2_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER2_STAT_OFFSET) +#define LPC43_CCU1_M4_TIMER3_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER3_CFG_OFFSET) +#define LPC43_CCU1_M4_TIMER3_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER3_STAT_OFFSET) +#define LPC43_CCU1_M4_SSP1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP1_CFG_OFFSET) +#define LPC43_CCU1_M4_SSP1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP1_STAT_OFFSET) +#define LPC43_CCU1_M4_QEI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_QEI_CFG_OFFSET) +#define LPC43_CCU1_M4_QEI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_QEI_STAT_OFFSET) +#define LPC43_CCU1_PERIPH_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_BUS_CFG_OFFSET) +#define LPC43_CCU1_PERIPH_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_BUS_STAT_OFFSET) +#define LPC43_CCU1_PERIPH_CORE_CFG (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_CORE_CFG_OFFSET) +#define LPC43_CCU1_PERIPH_CORE_STAT (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_CORE_STAT_OFFSET) +#define LPC43_CCU1_PERIPH_SGPIO_CFG (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_SGPIO_CFG_OFFSET) +#define LPC43_CCU1_PERIPH_SGPIO_STAT (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_SGPIO_STAT_OFFSET) +#define LPC43_CCU1_USB0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_USB0_CFG_OFFSET) +#define LPC43_CCU1_USB0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_USB0_STAT_OFFSET) +#define LPC43_CCU1_USB1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_USB1_CFG_OFFSET) +#define LPC43_CCU1_USB1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_USB1_STAT_OFFSET) +#define LPC43_CCU1_SPI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_SPI_CFG_OFFSET) +#define LPC43_CCU1_SPI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_SPI_STAT_OFFSET) +#define LPC43_CCU1_VADC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_VADC_CFG_OFFSET) +#define LPC43_CCU1_VADC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_VADC_STAT_OFFSET) -#define LPC43_CCU2_PM (LPC43_CCU2_BASE+LPC43_CCU2_PM_OFFSET) -#define LPC43_CCU2_BASE_STAT (LPC43_CCU2_BASE+LPC43_CCU2_BASE_STAT_OFFSET) -#define LPC43_CCU2_APLL_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APLL_CFG_OFFSET) -#define LPC43_CCU2_APLL_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APLL_STAT_OFFSET) -#define LPC43_CCU2_APB2_USART3_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART3_CFG_OFFSET) -#define LPC43_CCU2_APB2_USART3_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART3_STAT_OFFSET) -#define LPC43_CCU2_APB2_USART2_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART2_CFG_OFFSET) -#define LPC43_CCU2_APB2_USART2_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART2_STAT_OFFSET) -#define LPC43_CCU2_APB0_UART1_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB0_UART1_CFG_OFFSET) -#define LPC43_CCU2_APB0_UART1_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB0_UART1_STAT_OFFSET) -#define LPC43_CCU2_APB0_USART0_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB0_USART0_CFG_OFFSET) -#define LPC43_CCU2_APB0_USART0_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB0_USART0_STAT_OFFSET) -#define LPC43_CCU2_APB2_SSP1_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB2_SSP1_CFG_OFFSET) -#define LPC43_CCU2_APB2_SSP1_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB2_SSP1_STAT_OFFSET) -#define LPC43_CCU2_APB0_SSP0_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB0_SSP0_CFG_OFFSET) -#define LPC43_CCU2_APB0_SSP0_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB0_SSP0_STAT_OFFSET) -#define LPC43_CCU2_SDIO_CFG (LPC43_CCU2_BASE+LPC43_CCU2_SDIO_CFG_OFFSET) -#define LPC43_CCU2_SDIO_STAT (LPC43_CCU2_BASE+LPC43_CCU2_SDIO_STAT_OFFSET) +#define LPC43_CCU2_PM (LPC43_CCU2_BASE+LPC43_CCU2_PM_OFFSET) +#define LPC43_CCU2_BASE_STAT (LPC43_CCU2_BASE+LPC43_CCU2_BASE_STAT_OFFSET) +#define LPC43_CCU2_APLL_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APLL_CFG_OFFSET) +#define LPC43_CCU2_APLL_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APLL_STAT_OFFSET) +#define LPC43_CCU2_APB2_USART3_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART3_CFG_OFFSET) +#define LPC43_CCU2_APB2_USART3_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART3_STAT_OFFSET) +#define LPC43_CCU2_APB2_USART2_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART2_CFG_OFFSET) +#define LPC43_CCU2_APB2_USART2_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART2_STAT_OFFSET) +#define LPC43_CCU2_APB0_UART1_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB0_UART1_CFG_OFFSET) +#define LPC43_CCU2_APB0_UART1_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB0_UART1_STAT_OFFSET) +#define LPC43_CCU2_APB0_USART0_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB0_USART0_CFG_OFFSET) +#define LPC43_CCU2_APB0_USART0_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB0_USART0_STAT_OFFSET) +#define LPC43_CCU2_APB2_SSP1_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB2_SSP1_CFG_OFFSET) +#define LPC43_CCU2_APB2_SSP1_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB2_SSP1_STAT_OFFSET) +#define LPC43_CCU2_APB0_SSP0_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB0_SSP0_CFG_OFFSET) +#define LPC43_CCU2_APB0_SSP0_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB0_SSP0_STAT_OFFSET) +#define LPC43_CCU2_SDIO_CFG (LPC43_CCU2_BASE+LPC43_CCU2_SDIO_CFG_OFFSET) +#define LPC43_CCU2_SDIO_STAT (LPC43_CCU2_BASE+LPC43_CCU2_SDIO_STAT_OFFSET) /* Register Bit Definitions *************************************************************************/ /* CCU1/2 Power Mode Register */ -#define CCU_PM_PD (1 << 0) /* Bit 0: Initiate power-down mode */ - /* Bits 1-31: Reserved */ +#define CCU_PM_PD (1 << 0) /* Bit 0: Initiate power-down mode */ + /* Bits 1-31: Reserved */ /* CCU1 Base Clock Status Register */ -#define CCU1_BASE_STAT_AB3 (1 << 0) /* Bit 0: Base clock indicator for BASE_APB3_CLK */ -#define CCU1_BASE_STAT_APB1 (1 << 1) /* Bit 1: Base clock indicator for BASE_APB1_CLK */ -#define CCU1_BASE_STAT_SPIFI (1 << 2) /* Bit 2: Base clock indicator for BASE_SPIFI_CLK */ -#define CCU1_BASE_STAT_M4 (1 << 3) /* Bit 3: Base clock indicator for BASE_M4_CLK */ - /* Bits 4-5: Reserved */ -#define CCU1_BASE_STAT_PERIPH (1 << 6) /* Bit 6: Base clock indicator for BASE_PERIPH_CLK */ -#define CCU1_BASE_STAT_USB0 (1 << 7) /* Bit 7: Base clock indicator for BASE_USB0_CLK */ -#define CCU1_BASE_STAT_USB1 (1 << 8) /* Bit 8: Base clock indicator for BASE_USB1_CLK */ -#define CCU1_BASE_STAT_SPI (1 << 9) /* Bit 9: Base clock indicator for BASE_SPI_CLK */ - /* Bits 10-31: Reserved */ +#define CCU1_BASE_STAT_AB3 (1 << 0) /* Bit 0: Base clock indicator for BASE_APB3_CLK */ +#define CCU1_BASE_STAT_APB1 (1 << 1) /* Bit 1: Base clock indicator for BASE_APB1_CLK */ +#define CCU1_BASE_STAT_SPIFI (1 << 2) /* Bit 2: Base clock indicator for BASE_SPIFI_CLK */ +#define CCU1_BASE_STAT_M4 (1 << 3) /* Bit 3: Base clock indicator for BASE_M4_CLK */ + /* Bits 4-5: Reserved */ +#define CCU1_BASE_STAT_PERIPH (1 << 6) /* Bit 6: Base clock indicator for BASE_PERIPH_CLK */ +#define CCU1_BASE_STAT_USB0 (1 << 7) /* Bit 7: Base clock indicator for BASE_USB0_CLK */ +#define CCU1_BASE_STAT_USB1 (1 << 8) /* Bit 8: Base clock indicator for BASE_USB1_CLK */ +#define CCU1_BASE_STAT_SPI (1 << 9) /* Bit 9: Base clock indicator for BASE_SPI_CLK */ + /* Bits 10-31: Reserved */ /* CCU2 Base Clock Status Register */ - /* Bit 0: Reserved */ -#define CCU2_BASE_STAT_USART3 (1 << 1) /* Bit 1: Base clock indicator for BASE_USART3_CLK */ -#define CCU2_BASE_STAT_USART2 (1 << 2) /* Bit 2: Base clock indicator for BASE_USART2_CLK */ -#define CCU2_BASE_STAT_UART1 (1 << 3) /* Bit 3: Base clock indicator for BASE_UART1_CLK */ -#define CCU2_BASE_STAT_USART0 (1 << 4) /* Bit 4: Base clock indicator for BASE_USART0_CLK */ -#define CCU2_BASE_STAT_SSP1 (1 << 5) /* Bit 5: Base clock indicator for BASE_SSP1_CLK */ -#define CCU2_BASE_STAT_SSP0 (1 << 6) /* Bit 6: Base clock indicator for BASE_SSP0_CLK */ - /* Bits 7-31: Reserved */ + /* Bit 0: Reserved */ +#define CCU2_BASE_STAT_USART3 (1 << 1) /* Bit 1: Base clock indicator for BASE_USART3_CLK */ +#define CCU2_BASE_STAT_USART2 (1 << 2) /* Bit 2: Base clock indicator for BASE_USART2_CLK */ +#define CCU2_BASE_STAT_UART1 (1 << 3) /* Bit 3: Base clock indicator for BASE_UART1_CLK */ +#define CCU2_BASE_STAT_USART0 (1 << 4) /* Bit 4: Base clock indicator for BASE_USART0_CLK */ +#define CCU2_BASE_STAT_SSP1 (1 << 5) /* Bit 5: Base clock indicator for BASE_SSP1_CLK */ +#define CCU2_BASE_STAT_SSP0 (1 << 6) /* Bit 6: Base clock indicator for BASE_SSP0_CLK */ + /* Bits 7-31: Reserved */ /* CCU1/2 Branch Clock Configuration/Status Registers */ -#define CCU_CLK_CFG_RUN (1 << 0) /* Bit 0: Run enable */ -#define CCU_CLK_CFG_AUTO (1 << 1) /* Bit 1: Auto (AHB disable mechanism) enable */ -#define CCU_CLK_CFG_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable */ - /* Bits 3-31: Reserved */ +#define CCU_CLK_CFG_RUN (1 << 0) /* Bit 0: Run enable */ +#define CCU_CLK_CFG_AUTO (1 << 1) /* Bit 1: Auto (AHB disable mechanism) enable */ +#define CCU_CLK_CFG_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable */ + /* Bits 3-31: Reserved */ /* CCU1/2 Branch Clock Status Registers */ -#define CCU_CLK_STAT_RUN (1 << 0) /* Bit 0: Run enable status */ -#define CCU_CLK_STAT_AUTO (1 << 1) /* Bit 1: Auto (AHB disable mechanism) enable status */ -#define CCU_CLK_STAT_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable status */ - /* Bits 3-31: Reserved */ +#define CCU_CLK_STAT_RUN (1 << 0) /* Bit 0: Run enable status */ +#define CCU_CLK_STAT_AUTO (1 << 1) /* Bit 1: Auto (AHB disable mechanism) enable status */ +#define CCU_CLK_STAT_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable status */ + /* Bits 3-31: Reserved */ /**************************************************************************************************** * Public Types diff --git a/arch/arm/src/lpc43xx/lpc43_cgu.c b/arch/arm/src/lpc43xx/lpc43_cgu.c index fc1eda7321..74668fcd65 100644 --- a/arch/arm/src/lpc43xx/lpc43_cgu.c +++ b/arch/arm/src/lpc43xx/lpc43_cgu.c @@ -436,6 +436,32 @@ void lpc43_pll0usbconfig(void) putreg32(BOARD_USB0_NP_DIV, LPC43_PLL0USB_NP_DIV); } +/**************************************************************************** + * Name: lpc43_enetclkconfig(void) + * + * Description: + * Initialise ethernet clock block to take clock from ENET_TX_CLK. + * + ****************************************************************************/ + +#if defined(CONFIG_LPC43_ETHERNET) +void lpc43_enetclkconfig(void) + +{ + /* Note that using TXCLK for RX implies use of RMII */ + +#if defined(CONFIG_LPC43_RMII) + putreg32((BASE_LCD_CLKSEL_ENET_TXCLK | BASE_LCD_CLK_AUTOBLOCK), + LPC43_BASE_PHYRX_CLK); +#else + putreg32((BASE_LCD_CLKSEL_ENET_RXCLK | BASE_LCD_CLK_AUTOBLOCK), + LPC43_BASE_PHYRX_CLK); +#endif + putreg32((BASE_LCD_CLKSEL_ENET_TXCLK | BASE_LCD_CLK_AUTOBLOCK), + LPC43_BASE_PHYTX_CLK); +} +#endif + /**************************************************************************** * Name: lpc43_pll0usbenable * @@ -681,4 +707,10 @@ void lpc43_clockconfig(void) #if defined(BOARD_ABP3_CLKSRC) lpc43_abp3(); #endif + +#if defined(CONFIG_LPC43_ETHERNET) + /* Configure ethernet */ + + lpc43_enetclkconfig(); +#endif } diff --git a/arch/arm/src/lpc43xx/lpc43_config.h b/arch/arm/src/lpc43xx/lpc43_config.h index fb57736826..1e7c5c84a3 100644 --- a/arch/arm/src/lpc43xx/lpc43_config.h +++ b/arch/arm/src/lpc43xx/lpc43_config.h @@ -130,11 +130,11 @@ # undef CONFIG_UART1_FLOWCONTROL #endif -/* Check for RS-485 support (USART0,2,3 only) */ +/* Check for RS-485 support (All USARTS & UART1) */ #undef HAVE_RS485 -#if defined(CONFIG_USART0_RS485MODE) || defined(CONFIG_USART2_RS485MODE) || \ - defined(CONFIG_USART3_RS485MODE) +#if defined(CONFIG_USART0_RS485MODE) || defined(CONFIG_UART1_RS485MODE) || \ + defined(CONFIG_USART2_RS485MODE) || defined(CONFIG_USART3_RS485MODE) # define HAVE_RS485 1 #endif diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index 2eab571ead..733a161c2b 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -72,7 +72,9 @@ #include "lpc43_ethernet.h" #include "chip/lpc43_creg.h" #include "chip/lpc43_cgu.h" +#include "chip/lpc43_ccu.h" #include "lpc43_rgu.h" +#include "lpc43_gpio.h" #include "up_arch.h" #include @@ -101,10 +103,11 @@ # error "Both CONFIG_LPC43_MII and CONFIG_LPC43_RMII defined" #endif -#ifdef CONFIG_LPC43_AUTONEG # ifndef CONFIG_LPC43_PHYSR # error "CONFIG_LPC43_PHYSR must be defined in the NuttX configuration" # endif + +#ifndef CONFIG_LPC43_AUTONEG # ifdef CONFIG_LPC43_PHYSR_ALTCONFIG # ifndef CONFIG_LPC43_PHYSR_ALTMODE # error "CONFIG_LPC43_PHYSR_ALTMODE must be defined in the NuttX configuration" @@ -407,7 +410,7 @@ * checksum is OK the DMA can handle the frame otherwise the frame is dropped */ -#if CONFIG_LPC43_ETH_HWCHECKSUM +#ifdef CONFIG_LPC43_ETH_HWCHECKSUM # define DMAOMR_SET_MASK \ (ETH_DMAOPMODE_OSF | ETH_DMAOPMODE_RTC_64 | ETH_DMAOPMODE_TTC_64 | \ ETH_DMAOPMODE_TSF | ETH_DMAOPMODE_RSF) @@ -3329,6 +3332,18 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) nvdbg("PHYSR[%d]: %04x\n", CONFIG_LPC43_PHYSR, phyval); +#ifdef CONFIG_ETH0_PHY_LAN8720 + if ((phyval & (MII_MSR_100BASETXHALF | MII_MSR_100BASETXFULL)) != 0) + { + priv->mbps100 = 1; + } + + if ((phyval & (MII_MSR_100BASETXFULL | MII_MSR_10BASETXFULL)) != 0) + { + priv->fduplex = 1; + } + +#else /* Different PHYs present speed and mode information in different ways. IF * This CONFIG_LPC43_PHYSR_ALTCONFIG is selected, this indicates that the PHY * represents speed and mode information are combined, for example, with @@ -3338,10 +3353,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) #ifdef CONFIG_LPC43_PHYSR_ALTCONFIG switch (phyval & CONFIG_LPC43_PHYSR_ALTMODE) { - default: - case CONFIG_LPC43_PHYSR_10HD: - priv->fduplex = 0; - priv->mbps100 = 0; + case CONFIG_LPC43_PHYSR_100FD: + priv->fduplex = 1; + priv->mbps100 = 1; break; case CONFIG_LPC43_PHYSR_100HD: @@ -3354,9 +3368,10 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) priv->mbps100 = 0; break; - case CONFIG_LPC43_PHYSR_100FD: - priv->fduplex = 1; - priv->mbps100 = 1; + default: + case CONFIG_LPC43_PHYSR_10HD: + priv->fduplex = 0; + priv->mbps100 = 0; break; } @@ -3378,15 +3393,27 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) } #endif -#else /* Auto-negotion not selected */ +#ifdef CONFIG_LPC43_ETHFD + priv->mbps100 = 1; +#endif + +#ifdef CONFIG_LPC43_ETH100MBPS + priv->fduplex = 1; +#endif +#endif + + /* However we got here, commit to the hardware */ phyval = 0; -#ifdef CONFIG_LPC43_ETHFD - phyval |= MII_MCR_FULLDPLX; -#endif -#ifdef CONFIG_LPC43_ETH100MBPS - phyval |= MII_MCR_SPEED100; -#endif + if (priv->mbps100) + { + phyval |= MII_MCR_FULLDPLX; + } + + if (priv->fduplex) + { + phyval |= MII_MCR_SPEED100; + } ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, phyval); if (ret < 0) @@ -3394,6 +3421,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) ndbg("Failed to write the PHY MCR: %d\n", ret); return ret; } + up_mdelay(PHY_CONFIG_DELAY); /* Remember the selected speed and duplex modes */ @@ -3537,6 +3565,14 @@ static inline void lpc43_ethgpioconfig(FAR struct lpc43_ethmac_s *priv) lpc43_pin_config(PINCONF_ENET_TXD1); lpc43_pin_config(PINCONF_ENET_TXEN); +#ifdef PINCONF_ENET_RESET + lpc43_pin_config(PINCONF_ENET_RESET); + lpc43_gpio_config(GPIO_ENET_RESET); + lpc43_gpio_write(GPIO_ENET_RESET, 0); + up_mdelay(5); + lpc43_gpio_write(GPIO_ENET_RESET, 1); + up_mdelay(5); +#endif #endif #endif } @@ -3561,15 +3597,12 @@ static void lpc43_ethreset(FAR struct lpc43_ethmac_s *priv) { uint32_t regval; + lpc43_putreg(CCU_CLK_CFG_RUN|CCU_CLK_CFG_AUTO|CCU_CLK_CFG_WAKEUP,LPC43_CCU1_M4_ETHERNET_CFG); + /* Reset the Ethernet */ lpc43_putreg(RGU_CTRL0_ETHERNET_RST, LPC43_RGU_CTRL0); - /* Perform a software reset by setting the SR bit in the DMABMR register. - * This Resets all MAC subsystem internal registers and logic. After this - * reset all the registers holds their reset values. - */ - regval = lpc43_getreg(LPC43_ETH_DMABMODE); regval |= ETH_DMABMODE_SWR; lpc43_putreg(regval, LPC43_ETH_DMABMODE); @@ -3904,6 +3937,12 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv) return ret; } + /* Perform a software reset by setting the SR bit in the DMABMR register. + * This Resets all MAC subsystem internal registers and logic. After this + * reset all the registers holds their reset values. + */ + + /* Initialize the MAC and DMA */ nllvdbg("Initialize the MAC and DMA\n"); diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index 12896bf620..5ac9d0c158 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -1334,6 +1334,7 @@ static bool up_txempty(struct uart_dev_s *dev) * ****************************************************************************/ +#ifdef USE_EARLYSERIALINIT void up_earlyserialinit(void) { /* Configure all UARTs (except the CONSOLE UART) and disable interrupts */ @@ -1373,6 +1374,7 @@ void up_earlyserialinit(void) up_setup(&CONSOLE_DEV); #endif } +#endif /**************************************************************************** * Name: up_serialinit diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c index be4172c8a5..0d227fa8fa 100644 --- a/arch/arm/src/lpc43xx/lpc43_ssp.c +++ b/arch/arm/src/lpc43xx/lpc43_ssp.c @@ -770,12 +770,15 @@ static inline FAR struct lpc43_sspdev_s *lpc43_ssp1initialize(void) /* Pins configuration */ +#ifdef PINCONF_SSP1_SCK + /* It is possible this is not configured if CLK0 is being used for clocking SPI */ + lpc43_pin_config(PINCONF_SSP1_SCK); +#endif lpc43_pin_config(PINCONF_SSP1_MISO); lpc43_pin_config(PINCONF_SSP1_MOSI); leave_critical_section(flags); - return &g_ssp1dev; } #endif diff --git a/arch/arm/src/lpc43xx/lpc43_uart.c b/arch/arm/src/lpc43xx/lpc43_uart.c index bfa881817c..1806333979 100644 --- a/arch/arm/src/lpc43xx/lpc43_uart.c +++ b/arch/arm/src/lpc43xx/lpc43_uart.c @@ -415,6 +415,10 @@ void lpc43_uart1_setup(void) #endif #endif +#ifdef CONFIG_UART1_RS485MODE + lpc43_pin_config(PINCONF_U1_DIR); +#endif + leave_critical_section(flags); }; #endif diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c index 36be49a807..57e3ef2c8c 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -2582,6 +2582,13 @@ static int lpc43_pullup(struct usbdev_s *dev, bool enable) if (enable) { lpc43_setbits (USBDEV_USBCMD_RS, LPC43_USBDEV_USBCMD); + +#ifdef CONFIG_LPC43_USB0DEV_NOVBUS + /* Create a 'false' power event on the USB port so the MAC connects */ + + lpc43_clrbits (USBOTG_OTGSC_VD, LPC43_USBOTG_OTGSC); + lpc43_setbits (USBOTG_OTGSC_VC, LPC43_USBOTG_OTGSC); +#endif } else { diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.h b/arch/arm/src/lpc43xx/lpc43_usb0dev.h index be9b96f9fd..d941632013 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.h +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.h @@ -94,4 +94,3 @@ void lpc43_usbsuspend(FAR struct usbdev_s *dev, bool resume); #endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_USB0DEV_H */ -