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Enable the Ethernet for the LPC4330 and autonegotiation when the MAC is a LAN8720.

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This commit is contained in:
Dave Marples 2016-02-18 19:07:33 -06:00 committed by Gregory Nutt
parent de885064d2
commit 41b56a5f09
12 changed files with 442 additions and 336 deletions
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10
arch/arm/src/lpc43xx/Kconfig
View File

@ -488,10 +488,20 @@ config LPC43_USB0
bool "USB0" bool "USB0"
default n default n
config LPC43_USB0DEV_NOVBUS
bool "No USB0 VBUS sensing"
default n
depends on LPC43_USB0
config LPC43_USB1 config LPC43_USB1
bool "USB1" bool "USB1"
default n default n
config LPC43_USB1DEV_NOVBUS
bool "No USB1 VBUS sensing"
default n
depends on LPC43_USB1
config LPC43_USB1_ULPI config LPC43_USB1_ULPI
bool "USB1 with ULPI" bool "USB1 with ULPI"
default n default n

12
arch/arm/src/lpc43xx/Make.defs
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@ -128,6 +128,14 @@ endif
ifeq ($(CONFIG_LPC43_SPI),y) ifeq ($(CONFIG_LPC43_SPI),y)
CHIP_CSRCS += lpc43_spi.c CHIP_CSRCS += lpc43_spi.c
else
ifeq ($(CONFIG_LPC43_SSP0),y)
CHIP_CSRCS += lpc43_spi.c
else
ifeq ($(CONFIG_LPC43_SSP1),y)
CHIP_CSRCS += lpc43_spi.c
endif
endif
endif endif
ifeq ($(CONFIG_LPC43_SPIFI),y) ifeq ($(CONFIG_LPC43_SPIFI),y)
@ -135,10 +143,10 @@ CHIP_CSRCS += lpc43_spifi.c
endif endif
ifeq ($(CONFIG_LPC43_SSP0),y) ifeq ($(CONFIG_LPC43_SSP0),y)
CHIP_CSRCS += lpc43_ssp.c lpc43_spi.c CHIP_CSRCS += lpc43_ssp.c
else else
ifeq ($(CONFIG_LPC43_SSP1),y) ifeq ($(CONFIG_LPC43_SSP1),y)
CHIP_CSRCS += lpc43_ssp.c lpc43_spi.c CHIP_CSRCS += lpc43_ssp.c
endif endif
endif endif

64
arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h
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@ -271,38 +271,38 @@
#define PINCONF_EMC_RAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_5) #define PINCONF_EMC_RAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_5)
#define PINCONF_EMC_WE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_6) #define PINCONF_EMC_WE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_6)
#define PINCONF_ENET_COL_1 (PINCONF_FUNC2|PINCONF_PINS0|PINCONF_PIN_1) #define PINCONF_ENET_COL_1 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS0|PINCONF_PIN_1)
#define PINCONF_ENET_COL_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_6) #define PINCONF_ENET_COL_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_6)
#define PINCONF_ENET_COL_3 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_1) #define PINCONF_ENET_COL_3 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS4|PINCONF_PIN_1)
#define PINCONF_ENET_CRS_1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_16) #define PINCONF_ENET_CRS_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_16)
#define PINCONF_ENET_CRS_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_0) #define PINCONF_ENET_CRS_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_0)
#define PINCONF_ENET_MDC_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_1) #define PINCONF_ENET_MDC_1 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_1)
#define PINCONF_ENET_MDC_2 (PINCONF_FUNC6|PINCONF_PINS7|PINCONF_PIN_7) #define PINCONF_ENET_MDC_2 (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_PINS7|PINCONF_PIN_7)
#define PINCONF_ENET_MDC_3 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_0) #define PINCONF_ENET_MDC_3 (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_0)
#define PINCONF_ENET_MDIO (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_17) #define PINCONF_ENET_MDIO (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_17)
#define PINCONF_ENET_REF_CLK (PINCONF_FUNC0|PINCONF_PINS1|PINCONF_PIN_19) #define PINCONF_ENET_REF_CLK (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_19)
#define PINCONF_ENET_RXD0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_15) #define PINCONF_ENET_RXD0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_15)
#define PINCONF_ENET_RXD1 (PINCONF_FUNC2|PINCONF_PINS0|PINCONF_PIN_0) #define PINCONF_ENET_RXD1 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS0|PINCONF_PIN_0)
#define PINCONF_ENET_RXD2_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_6) #define PINCONF_ENET_RXD2_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_6)
#define PINCONF_ENET_RXD2_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_3) #define PINCONF_ENET_RXD2_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_3)
#define PINCONF_ENET_RXD3_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_7) #define PINCONF_ENET_RXD3_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_7)
#define PINCONF_ENET_RXD3_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_2) #define PINCONF_ENET_RXD3_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_2)
#define PINCONF_ENET_RX_CLK (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_0) #define PINCONF_ENET_RX_CLK (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_0)
#define PINCONF_ENET_RX_DV_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_8) #define PINCONF_ENET_RX_DV_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_8)
#define PINCONF_ENET_RX_DV_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_16) #define PINCONF_ENET_RX_DV_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_16)
#define PINCONF_ENET_RX_ER_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_9) #define PINCONF_ENET_RX_ER_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_9)
#define PINCONF_ENET_RX_ER_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_1) #define PINCONF_ENET_RX_ER_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_1)
#define PINCONF_ENET_TXD0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_18) #define PINCONF_ENET_TXD0 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_18)
#define PINCONF_ENET_TXD1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_20) #define PINCONF_ENET_TXD1 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_20)
#define PINCONF_ENET_TXD2_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_2) #define PINCONF_ENET_TXD2_1 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_2)
#define PINCONF_ENET_TXD2_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_4) #define PINCONF_ENET_TXD2_2 (PINCONF_FUNC5|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_4)
#define PINCONF_ENET_TXD3_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_3) #define PINCONF_ENET_TXD3_1 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_3)
#define PINCONF_ENET_TXD3_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_5) #define PINCONF_ENET_TXD3_2 (PINCONF_FUNC5|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_5)
#define PINCONF_ENET_TXEN (PINCONF_FUNC6|PINCONF_PINS0|PINCONF_PIN_1) #define PINCONF_ENET_TXEN (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_PINS0|PINCONF_PIN_1)
#define PINCONF_ENET_TX_CLK (PINCONF_FUNC0|PINCONF_PINS1|PINCONF_PIN_19) #define PINCONF_ENET_TX_CLK (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_19)
#define PINCONF_ENET_TX_EN (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_4) #define PINCONF_ENET_TX_EN (PINCONF_FUNC3|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_4)
#define PINCONF_ENET_TX_ER_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_5) #define PINCONF_ENET_TX_ER_1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_5)
#define PINCONF_ENET_TX_ER_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_14) #define PINCONF_ENET_TX_ER_2 (PINCONF_FUNC6|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_14)
#define PINCONF_GPIO0p0 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_0) #define PINCONF_GPIO0p0 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_0)
#define PINCONF_GPIO0p1 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_1) #define PINCONF_GPIO0p1 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_1)

2
arch/arm/src/lpc43xx/chip/lpc43_ccu.h
View File

@ -125,6 +125,7 @@
#define LPC43_CCU1_M4_SCU_STAT_OFFSET 0x0534 /* CLK_M4_SCU status register */ #define LPC43_CCU1_M4_SCU_STAT_OFFSET 0x0534 /* CLK_M4_SCU status register */
#define LPC43_CCU1_M4_CREG_CFG_OFFSET 0x0538 /* CLK_M4_CREG configuration register */ #define LPC43_CCU1_M4_CREG_CFG_OFFSET 0x0538 /* CLK_M4_CREG configuration register */
#define LPC43_CCU1_M4_CREG_STAT_OFFSET 0x053c /* CLK_M4_CREG status register */ #define LPC43_CCU1_M4_CREG_STAT_OFFSET 0x053c /* CLK_M4_CREG status register */
#define LPC43_CCU1_M4_UART1_RS485CTRL_OFFSET 0x054c /* CLK_M4_UART1 RS485 Control register */
#define LPC43_CCU1_M4_RITIMER_CFG_OFFSET 0x0600 /* CLK_M4_RITIMER configuration register */ #define LPC43_CCU1_M4_RITIMER_CFG_OFFSET 0x0600 /* CLK_M4_RITIMER configuration register */
#define LPC43_CCU1_M4_RITIMER_STAT_OFFSET 0x0604 /* CLK_M4_RITIMER status register */ #define LPC43_CCU1_M4_RITIMER_STAT_OFFSET 0x0604 /* CLK_M4_RITIMER status register */
#define LPC43_CCU1_M4_USART2_CFG_OFFSET 0x0608 /* CLK_M4_USART2 configuration register */ #define LPC43_CCU1_M4_USART2_CFG_OFFSET 0x0608 /* CLK_M4_USART2 configuration register */
@ -253,6 +254,7 @@
#define LPC43_CCU1_M4_SCU_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCU_STAT_OFFSET) #define LPC43_CCU1_M4_SCU_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCU_STAT_OFFSET)
#define LPC43_CCU1_M4_CREG_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_CFG_OFFSET) #define LPC43_CCU1_M4_CREG_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_CFG_OFFSET)
#define LPC43_CCU1_M4_CREG_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_STAT_OFFSET) #define LPC43_CCU1_M4_CREG_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_STAT_OFFSET)
#define LPC43_CCU1_M4_UART1_RS485CTRL (LPC43_CCU1_BASE+LPC43_CCU1_M4_UART1_RS485CTRL_OFFSET)
#define LPC43_CCU1_M4_RITIMER_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_CFG_OFFSET) #define LPC43_CCU1_M4_RITIMER_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_CFG_OFFSET)
#define LPC43_CCU1_M4_RITIMER_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_STAT_OFFSET) #define LPC43_CCU1_M4_RITIMER_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_STAT_OFFSET)
#define LPC43_CCU1_M4_USART2_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART2_CFG_OFFSET) #define LPC43_CCU1_M4_USART2_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART2_CFG_OFFSET)

32
arch/arm/src/lpc43xx/lpc43_cgu.c
View File

@ -436,6 +436,32 @@ void lpc43_pll0usbconfig(void)
putreg32(BOARD_USB0_NP_DIV, LPC43_PLL0USB_NP_DIV); putreg32(BOARD_USB0_NP_DIV, LPC43_PLL0USB_NP_DIV);
} }
/****************************************************************************
* Name: lpc43_enetclkconfig(void)
*
* Description:
* Initialise ethernet clock block to take clock from ENET_TX_CLK.
*
****************************************************************************/
#if defined(CONFIG_LPC43_ETHERNET)
void lpc43_enetclkconfig(void)
{
/* Note that using TXCLK for RX implies use of RMII */
#if defined(CONFIG_LPC43_RMII)
putreg32((BASE_LCD_CLKSEL_ENET_TXCLK | BASE_LCD_CLK_AUTOBLOCK),
LPC43_BASE_PHYRX_CLK);
#else
putreg32((BASE_LCD_CLKSEL_ENET_RXCLK | BASE_LCD_CLK_AUTOBLOCK),
LPC43_BASE_PHYRX_CLK);
#endif
putreg32((BASE_LCD_CLKSEL_ENET_TXCLK | BASE_LCD_CLK_AUTOBLOCK),
LPC43_BASE_PHYTX_CLK);
}
#endif
/**************************************************************************** /****************************************************************************
* Name: lpc43_pll0usbenable * Name: lpc43_pll0usbenable
* *
@ -681,4 +707,10 @@ void lpc43_clockconfig(void)
#if defined(BOARD_ABP3_CLKSRC) #if defined(BOARD_ABP3_CLKSRC)
lpc43_abp3(); lpc43_abp3();
#endif #endif
#if defined(CONFIG_LPC43_ETHERNET)
/* Configure ethernet */
lpc43_enetclkconfig();
#endif
} }

6
arch/arm/src/lpc43xx/lpc43_config.h
View File

@ -130,11 +130,11 @@
# undef CONFIG_UART1_FLOWCONTROL # undef CONFIG_UART1_FLOWCONTROL
#endif #endif
/* Check for RS-485 support (USART0,2,3 only) */ /* Check for RS-485 support (All USARTS & UART1) */
#undef HAVE_RS485 #undef HAVE_RS485
#if defined(CONFIG_USART0_RS485MODE) || defined(CONFIG_USART2_RS485MODE) || \ #if defined(CONFIG_USART0_RS485MODE) || defined(CONFIG_UART1_RS485MODE) || \
defined(CONFIG_USART3_RS485MODE) defined(CONFIG_USART2_RS485MODE) || defined(CONFIG_USART3_RS485MODE)
# define HAVE_RS485 1 # define HAVE_RS485 1
#endif #endif

77
arch/arm/src/lpc43xx/lpc43_ethernet.c
View File

@ -72,7 +72,9 @@
#include "lpc43_ethernet.h" #include "lpc43_ethernet.h"
#include "chip/lpc43_creg.h" #include "chip/lpc43_creg.h"
#include "chip/lpc43_cgu.h" #include "chip/lpc43_cgu.h"
#include "chip/lpc43_ccu.h"
#include "lpc43_rgu.h" #include "lpc43_rgu.h"
#include "lpc43_gpio.h"
#include "up_arch.h" #include "up_arch.h"
#include <arch/board/board.h> #include <arch/board/board.h>
@ -101,10 +103,11 @@
# error "Both CONFIG_LPC43_MII and CONFIG_LPC43_RMII defined" # error "Both CONFIG_LPC43_MII and CONFIG_LPC43_RMII defined"
#endif #endif
#ifdef CONFIG_LPC43_AUTONEG
# ifndef CONFIG_LPC43_PHYSR # ifndef CONFIG_LPC43_PHYSR
# error "CONFIG_LPC43_PHYSR must be defined in the NuttX configuration" # error "CONFIG_LPC43_PHYSR must be defined in the NuttX configuration"
# endif # endif
#ifndef CONFIG_LPC43_AUTONEG
# ifdef CONFIG_LPC43_PHYSR_ALTCONFIG # ifdef CONFIG_LPC43_PHYSR_ALTCONFIG
# ifndef CONFIG_LPC43_PHYSR_ALTMODE # ifndef CONFIG_LPC43_PHYSR_ALTMODE
# error "CONFIG_LPC43_PHYSR_ALTMODE must be defined in the NuttX configuration" # error "CONFIG_LPC43_PHYSR_ALTMODE must be defined in the NuttX configuration"
@ -407,7 +410,7 @@
* checksum is OK the DMA can handle the frame otherwise the frame is dropped * checksum is OK the DMA can handle the frame otherwise the frame is dropped
*/ */
#if CONFIG_LPC43_ETH_HWCHECKSUM #ifdef CONFIG_LPC43_ETH_HWCHECKSUM
# define DMAOMR_SET_MASK \ # define DMAOMR_SET_MASK \
(ETH_DMAOPMODE_OSF | ETH_DMAOPMODE_RTC_64 | ETH_DMAOPMODE_TTC_64 | \ (ETH_DMAOPMODE_OSF | ETH_DMAOPMODE_RTC_64 | ETH_DMAOPMODE_TTC_64 | \
ETH_DMAOPMODE_TSF | ETH_DMAOPMODE_RSF) ETH_DMAOPMODE_TSF | ETH_DMAOPMODE_RSF)
@ -3329,6 +3332,18 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
nvdbg("PHYSR[%d]: %04x\n", CONFIG_LPC43_PHYSR, phyval); nvdbg("PHYSR[%d]: %04x\n", CONFIG_LPC43_PHYSR, phyval);
#ifdef CONFIG_ETH0_PHY_LAN8720
if ((phyval & (MII_MSR_100BASETXHALF | MII_MSR_100BASETXFULL)) != 0)
{
priv->mbps100 = 1;
}
if ((phyval & (MII_MSR_100BASETXFULL | MII_MSR_10BASETXFULL)) != 0)
{
priv->fduplex = 1;
}
#else
/* Different PHYs present speed and mode information in different ways. IF /* Different PHYs present speed and mode information in different ways. IF
* This CONFIG_LPC43_PHYSR_ALTCONFIG is selected, this indicates that the PHY * This CONFIG_LPC43_PHYSR_ALTCONFIG is selected, this indicates that the PHY
* represents speed and mode information are combined, for example, with * represents speed and mode information are combined, for example, with
@ -3338,10 +3353,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_LPC43_PHYSR_ALTCONFIG #ifdef CONFIG_LPC43_PHYSR_ALTCONFIG
switch (phyval & CONFIG_LPC43_PHYSR_ALTMODE) switch (phyval & CONFIG_LPC43_PHYSR_ALTMODE)
{ {
default: case CONFIG_LPC43_PHYSR_100FD:
case CONFIG_LPC43_PHYSR_10HD: priv->fduplex = 1;
priv->fduplex = 0; priv->mbps100 = 1;
priv->mbps100 = 0;
break; break;
case CONFIG_LPC43_PHYSR_100HD: case CONFIG_LPC43_PHYSR_100HD:
@ -3354,9 +3368,10 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
priv->mbps100 = 0; priv->mbps100 = 0;
break; break;
case CONFIG_LPC43_PHYSR_100FD: default:
priv->fduplex = 1; case CONFIG_LPC43_PHYSR_10HD:
priv->mbps100 = 1; priv->fduplex = 0;
priv->mbps100 = 0;
break; break;
} }
@ -3378,15 +3393,27 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
} }
#endif #endif
#else /* Auto-negotion not selected */ #ifdef CONFIG_LPC43_ETHFD
priv->mbps100 = 1;
#endif
#ifdef CONFIG_LPC43_ETH100MBPS
priv->fduplex = 1;
#endif
#endif
/* However we got here, commit to the hardware */
phyval = 0; phyval = 0;
#ifdef CONFIG_LPC43_ETHFD if (priv->mbps100)
{
phyval |= MII_MCR_FULLDPLX; phyval |= MII_MCR_FULLDPLX;
#endif }
#ifdef CONFIG_LPC43_ETH100MBPS
if (priv->fduplex)
{
phyval |= MII_MCR_SPEED100; phyval |= MII_MCR_SPEED100;
#endif }
ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, phyval); ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, phyval);
if (ret < 0) if (ret < 0)
@ -3394,6 +3421,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
ndbg("Failed to write the PHY MCR: %d\n", ret); ndbg("Failed to write the PHY MCR: %d\n", ret);
return ret; return ret;
} }
up_mdelay(PHY_CONFIG_DELAY); up_mdelay(PHY_CONFIG_DELAY);
/* Remember the selected speed and duplex modes */ /* Remember the selected speed and duplex modes */
@ -3537,6 +3565,14 @@ static inline void lpc43_ethgpioconfig(FAR struct lpc43_ethmac_s *priv)
lpc43_pin_config(PINCONF_ENET_TXD1); lpc43_pin_config(PINCONF_ENET_TXD1);
lpc43_pin_config(PINCONF_ENET_TXEN); lpc43_pin_config(PINCONF_ENET_TXEN);
#ifdef PINCONF_ENET_RESET
lpc43_pin_config(PINCONF_ENET_RESET);
lpc43_gpio_config(GPIO_ENET_RESET);
lpc43_gpio_write(GPIO_ENET_RESET, 0);
up_mdelay(5);
lpc43_gpio_write(GPIO_ENET_RESET, 1);
up_mdelay(5);
#endif
#endif #endif
#endif #endif
} }
@ -3561,15 +3597,12 @@ static void lpc43_ethreset(FAR struct lpc43_ethmac_s *priv)
{ {
uint32_t regval; uint32_t regval;
lpc43_putreg(CCU_CLK_CFG_RUN|CCU_CLK_CFG_AUTO|CCU_CLK_CFG_WAKEUP,LPC43_CCU1_M4_ETHERNET_CFG);
/* Reset the Ethernet */ /* Reset the Ethernet */
lpc43_putreg(RGU_CTRL0_ETHERNET_RST, LPC43_RGU_CTRL0); lpc43_putreg(RGU_CTRL0_ETHERNET_RST, LPC43_RGU_CTRL0);
/* Perform a software reset by setting the SR bit in the DMABMR register.
* This Resets all MAC subsystem internal registers and logic. After this
* reset all the registers holds their reset values.
*/
regval = lpc43_getreg(LPC43_ETH_DMABMODE); regval = lpc43_getreg(LPC43_ETH_DMABMODE);
regval |= ETH_DMABMODE_SWR; regval |= ETH_DMABMODE_SWR;
lpc43_putreg(regval, LPC43_ETH_DMABMODE); lpc43_putreg(regval, LPC43_ETH_DMABMODE);
@ -3904,6 +3937,12 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
return ret; return ret;
} }
/* Perform a software reset by setting the SR bit in the DMABMR register.
* This Resets all MAC subsystem internal registers and logic. After this
* reset all the registers holds their reset values.
*/
/* Initialize the MAC and DMA */ /* Initialize the MAC and DMA */
nllvdbg("Initialize the MAC and DMA\n"); nllvdbg("Initialize the MAC and DMA\n");

2
arch/arm/src/lpc43xx/lpc43_serial.c
View File

@ -1334,6 +1334,7 @@ static bool up_txempty(struct uart_dev_s *dev)
* *
****************************************************************************/ ****************************************************************************/
#ifdef USE_EARLYSERIALINIT
void up_earlyserialinit(void) void up_earlyserialinit(void)
{ {
/* Configure all UARTs (except the CONSOLE UART) and disable interrupts */ /* Configure all UARTs (except the CONSOLE UART) and disable interrupts */
@ -1373,6 +1374,7 @@ void up_earlyserialinit(void)
up_setup(&CONSOLE_DEV); up_setup(&CONSOLE_DEV);
#endif #endif
} }
#endif
/**************************************************************************** /****************************************************************************
* Name: up_serialinit * Name: up_serialinit

5
arch/arm/src/lpc43xx/lpc43_ssp.c
View File

@ -770,12 +770,15 @@ static inline FAR struct lpc43_sspdev_s *lpc43_ssp1initialize(void)
/* Pins configuration */ /* Pins configuration */
#ifdef PINCONF_SSP1_SCK
/* It is possible this is not configured if CLK0 is being used for clocking SPI */
lpc43_pin_config(PINCONF_SSP1_SCK); lpc43_pin_config(PINCONF_SSP1_SCK);
#endif
lpc43_pin_config(PINCONF_SSP1_MISO); lpc43_pin_config(PINCONF_SSP1_MISO);
lpc43_pin_config(PINCONF_SSP1_MOSI); lpc43_pin_config(PINCONF_SSP1_MOSI);
leave_critical_section(flags); leave_critical_section(flags);
return &g_ssp1dev; return &g_ssp1dev;
} }
#endif #endif

4
arch/arm/src/lpc43xx/lpc43_uart.c
View File

@ -415,6 +415,10 @@ void lpc43_uart1_setup(void)
#endif #endif
#endif #endif
#ifdef CONFIG_UART1_RS485MODE
lpc43_pin_config(PINCONF_U1_DIR);
#endif
leave_critical_section(flags); leave_critical_section(flags);
}; };
#endif #endif

7
arch/arm/src/lpc43xx/lpc43_usb0dev.c
View File

@ -2582,6 +2582,13 @@ static int lpc43_pullup(struct usbdev_s *dev, bool enable)
if (enable) if (enable)
{ {
lpc43_setbits (USBDEV_USBCMD_RS, LPC43_USBDEV_USBCMD); lpc43_setbits (USBDEV_USBCMD_RS, LPC43_USBDEV_USBCMD);
#ifdef CONFIG_LPC43_USB0DEV_NOVBUS
/* Create a 'false' power event on the USB port so the MAC connects */
lpc43_clrbits (USBOTG_OTGSC_VD, LPC43_USBOTG_OTGSC);
lpc43_setbits (USBOTG_OTGSC_VC, LPC43_USBOTG_OTGSC);
#endif
} }
else else
{ {

1
arch/arm/src/lpc43xx/lpc43_usb0dev.h
View File

@ -94,4 +94,3 @@ void lpc43_usbsuspend(FAR struct usbdev_s *dev, bool resume);
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_USB0DEV_H */ #endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_USB0DEV_H */