From 41ce419ebc919e818764d2f21127d666e6ba017b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 13 Dec 2013 12:42:26 -0600 Subject: [PATCH] A10: Timer interrupt handler --- arch/arm/include/a1x/a10_irq.h | 2 +- arch/arm/src/a1x/Kconfig | 6 +- arch/arm/src/a1x/Make.defs | 6 +- arch/arm/src/a1x/a1x_pio.c | 4 +- arch/arm/src/a1x/a1x_timerisr.c | 156 ++++++++++++++++++++++++++++++ arch/arm/src/a1x/chip/a1x_timer.h | 32 +++--- 6 files changed, 177 insertions(+), 29 deletions(-) create mode 100644 arch/arm/src/a1x/a1x_timerisr.c diff --git a/arch/arm/include/a1x/a10_irq.h b/arch/arm/include/a1x/a10_irq.h index 23259db97d..4cd291d205 100644 --- a/arch/arm/include/a1x/a10_irq.h +++ b/arch/arm/include/a1x/a10_irq.h @@ -78,7 +78,7 @@ #define A1X_IRQ_TIMER0 22 /* Timer port 0 */ #define A1X_IRQ_TIMER1 23 /* Timer port 1 */ #define A1X_IRQ_TIMER2 24 /* Timer 2 */ -# define A1X_IRQ_Alarm 24 /* Alarm */ +# define A1X_IRQ_ALARM 24 /* Alarm */ # define A1X_IRQ_WD 24 /* Watchdog */ #define A1X_IRQ_TIMER3 25 /* Timer 3 interrupt */ #define A1X_IRQ_CAN 26 /* CAN Bus controller interrupt */ diff --git a/arch/arm/src/a1x/Kconfig b/arch/arm/src/a1x/Kconfig index d50ba159c3..adac98922c 100644 --- a/arch/arm/src/a1x/Kconfig +++ b/arch/arm/src/a1x/Kconfig @@ -114,12 +114,8 @@ config A1X_KEYPAD bool "Keypad" default n -config A1X_TIMER0 - bool "Timer port 0" - default n - config A1X_TIMER1 - bool "Timer port 1" + bool "Timer 1" default n config A1X_TIMER2 diff --git a/arch/arm/src/a1x/Make.defs b/arch/arm/src/a1x/Make.defs index ba487f209d..5e05df1029 100644 --- a/arch/arm/src/a1x/Make.defs +++ b/arch/arm/src/a1x/Make.defs @@ -67,6 +67,10 @@ CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c +# Use common heap allocation for now (may need to be customized later) + +CMN_CSRCS += up_allocateheap.c + # Configuration dependent C and assembly language files ifeq ($(CONFIG_PAGING),y) @@ -93,4 +97,4 @@ CHIP_ASRCS = # A1x-specific C source files -CHIP_CSRCS = a1x_boot.c a1x_irq.c a1x_pio.c +CHIP_CSRCS = a1x_boot.c a1x_irq.c a1x_pio.c a1x_timerisr.c diff --git a/arch/arm/src/a1x/a1x_pio.c b/arch/arm/src/a1x/a1x_pio.c index 32084dc336..8ec0350959 100644 --- a/arch/arm/src/a1x/a1x_pio.c +++ b/arch/arm/src/a1x/a1x_pio.c @@ -218,8 +218,8 @@ void a1x_pio_irqinitialize(void) int a1x_configpio(pio_pinset_t cfgset) { - unsigned int port = a1x_pioport(cfgset); - unsigned int pin = a1x_piopin(cfgset); + unsigned int port = a1x_pio_port(cfgset); + unsigned int pin = a1x_pio_pin(cfgset); unsigned int shift; unsigned int value; uintptr_t cfgaddr; diff --git a/arch/arm/src/a1x/a1x_timerisr.c b/arch/arm/src/a1x/a1x_timerisr.c new file mode 100644 index 0000000000..4e35af9d41 --- /dev/null +++ b/arch/arm/src/a1x/a1x_timerisr.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * arch/arm/src/a1x/a1x_timerisr.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "chip/a1x_timer.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ +/* Timer 0 will run at the rate of OSC24M with no division */ + +#define TMR0_CLOCK (24000000) + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * Timer 0 counts down from the interval reload value to zero, generating + * an interrupt (and reload) when the counts decrements to zero. + */ + +#define TMR_INTERVAL ((TMR0_CLOCK + (CLK_TCK >> 1)) / CLK_TCK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +int up_timerisr(int irq, uint32_t *regs) +{ + /* Only a TIMER0 interrupt is expected here */ + + DEBUGASSERT((getreg32(A1X_TMR_IRQ_STA) & TMR_IRQ_TMR0) != 0); + + /* Clear the pending interrupt by writing a '1' to the status register */ + + putreg32(TMR_IRQ_TMR0, A1X_TMR_IRQ_STA); + + /* Process timer interrupt */ + + sched_process_timer(); + return OK; +} + +/**************************************************************************** + * Function: up_timerinit + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timerinit(void) +{ + uint32_t regval; + + /* Set the timer reload interval value */ + + putreg32(TMR_INTERVAL, A1X_TMR0_INTV_VALUE); + + /* Configure timer 0: + * + * ENABLE - Enable counting + * RELOAD - Reload timer interval value + * CLKSRC - OSC24M + * PRESCALER - No division + * MODE - Continuous mode + */ + + regval = (TMR_CTRL_EN | TMR_CTRL_RELOAD | TMR_CTRL_SRC_OSC24M | + TMR_CTRL_CLK_PRES_DIV1 | TMR_CTRL_MODE_CONTINUOUS); + putreg32(regval, A1X_TMR0_CTRL); + + /* Make sure that interrupts from the Timer 0 are disabled */ + + up_disable_irq(A1X_IRQ_TIMER0); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(A1X_IRQ_TIMER0, (xcpt_t)up_timerisr); + + /* Enable interrupts from the TIMER 0 port */ + + regval = getreg32(A1X_TMR_IRQ_EN); + regval |= TMR_IRQ_TMR0; + putreg32(regval, A1X_TMR_IRQ_EN); + + /* And enable the timer interrupt */ + + up_enable_irq(A1X_IRQ_TIMER0); +} diff --git a/arch/arm/src/a1x/chip/a1x_timer.h b/arch/arm/src/a1x/chip/a1x_timer.h index a6e24fcec5..afe3603057 100644 --- a/arch/arm/src/a1x/chip/a1x_timer.h +++ b/arch/arm/src/a1x/chip/a1x_timer.h @@ -173,25 +173,15 @@ /* Register bit field definitions ***************************************************/ -/* Timer IRQ Enable */ +/* Timer IRQ Enable and Timer Status */ -#define TMR_IRQ_EN_TMR0 (1 << 0) /* Bit 0: Timer 0 Interrupt Enable */ -#define TMR_IRQ_EN_TMR1 (1 << 1) /* Bit 1: Timer 1 Interrupt Enable */ -#define TMR_IRQ_EN_TMR2 (1 << 2) /* Bit 2: Timer 2 Interrupt Enable */ -#define TMR_IRQ_EN_TMR3 (1 << 3) /* Bit 3: Timer 3 Interrupt Enable */ -#define TMR_IRQ_EN_TMR4 (1 << 4) /* Bit 4: Timer 4 Interrupt Enable */ -#define TMR_IRQ_EN_TMR5 (1 << 5) /* Bit 5: Timer 5 Interrupt Enable */ -#define TMR_IRQ_EN_WDOG (1 << 8) /* Bit 8: Watchdog Interrupt Enable */ - -/* Timer Status */ - -#define TMR_IRQ_STA_TMR0 (1 << 0) /* Bit 0: Timer 0 Interrupt Pending */ -#define TMR_IRQ_STA_TMR1 (1 << 1) /* Bit 1: Timer 1 Interrupt Pending */ -#define TMR_IRQ_STA_TMR2 (1 << 2) /* Bit 2: Timer 2 Interrupt Pending */ -#define TMR_IRQ_STA_TMR3 (1 << 3) /* Bit 3: Timer 3 Interrupt Pending */ -#define TMR_IRQ_STA_TMR4 (1 << 4) /* Bit 4: Timer 4 Interrupt Pending */ -#define TMR_IRQ_STA_TMR5 (1 << 5) /* Bit 5: Timer 5 Interrupt Pending */ -#define TMR_IRQ_STA_WDOG (1 << 8) /* Bit 8: Watchdog Interrupt Pending */ +#define TMR_IRQ_TMR0 (1 << 0) /* Bit 0: Timer 0 Interrupt */ +#define TMR_IRQ_TMR1 (1 << 1) /* Bit 1: Timer 1 Interrupt */ +#define TMR_IRQ_TMR2 (1 << 2) /* Bit 2: Timer 2 Interrupt */ +#define TMR_IRQ_TMR3 (1 << 3) /* Bit 3: Timer 3 Interrupt */ +#define TMR_IRQ_TMR4 (1 << 4) /* Bit 4: Timer 4 Interrupt */ +#define TMR_IRQ_TMR5 (1 << 5) /* Bit 5: Timer 5 Interrupt */ +#define TMR_IRQ_WDOG (1 << 8) /* Bit 8: Watchdog Interrupt */ /* Timer 0-2,/4-5 Control */ @@ -214,7 +204,9 @@ # define TMR_CTRL_CLK_PRES_DIV32 (5 << TMR_CTRL_CLK_PRES_SHIFT) /* /32 (Not Timer 0) */ # define TMR_CTRL_CLK_PRES_DIV64 (6 << TMR_CTRL_CLK_PRES_SHIFT) /* /64 (Not Timer 0) */ # define TMR_CTRL_CLK_PRES_DIV128 (7 << TMR_CTRL_CLK_PRES_SHIFT) /* /128 (Not Timer 0) */ -#define TMR_CTRL_MODE (1 << 7) /* Bit 7: Timer n mode, n={0,1,2,4,5} +#define TMR_CTRL_MODE (1 << 7) /* Bit 7: Timer n mode, n={0,1,2,4,5} */ +# define TMR_CTRL_MODE_SINGLE (1 << 7) /* 1=single mode */ +# define TMR_CTRL_MODE_CONTINUOUS (0 << 7) /* 0=continuous mode */ /* Timer 3 Control */ @@ -345,7 +337,7 @@ #define ALRAM_DD_HMS_HOUR_SHIFT (16) /* Bits 16-20: Hour (0-23) */ #define ALRAM_DD_HMS_HOUR_MASK (0x1f << ALRAM_DD_HMS_HOUR_SHIFT) # define ALRAM_DD_HMS_HOUR(n) ((uint32_t)(n) << ALRAM_DD_HMS_HOUR_SHIFT) -#define ALRAM_DD_HMS_DAY_SHIFT (24) /* Bits 24-31: /* Day (0-255) */ +#define ALRAM_DD_HMS_DAY_SHIFT (24) /* Bits 24-31: Day (0-255) */ #define ALRAM_DD_HMS_DAY_MASK (0xff << ALRAM_DD_HMS_DAY_SHIFT) # define ALRAM_DD_HMS_DAY(n) ((uint32_t)(n) << ALRAM_DD_HMS_DAY_SHIFT)