diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h
index 0e8f7c33b0..aee6625dde 100644
--- a/arch/xtensa/include/irq.h
+++ b/arch/xtensa/include/irq.h
@@ -108,20 +108,21 @@
 #  define REG_LBEG          (_REG_LOOPS_START + 0)
 #  define REG_LEND          (_REG_LOOPS_START + 1)
 #  define REG_LCOUNT        (_REG_LOOPS_START + 2)
-#  define _REG_CALL0_START  (_REG_LOOPS_START + 3)
+#  define _REG_WINDOW_TMPS  (_REG_LOOPS_START + 3)
 #else
-#  define _REG_CALL0_START  _REG_LOOPS_START
+#  define _REG_WINDOW_TMPS  _REG_LOOPS_START
 #endif
 
 #ifndef __XTENSA_CALL0_ABI__
-  /* Temporary space for saving stuff during window spill */
+  /* Temporary space for saving stuff during window spill.
+   * REVISIT: I don't think that we need so many temporaries.
+   */
 
-#  define REG_TMP0          (_REG_CALL0_START + 0)
-#  define REG_TMP1          (_REG_CALL0_START + 1)
-#  define REG_TMP2          (_REG_CALL0_START + 2)
-#  define _REG_OVLY_START   (_REG_CALL0_START + 3)
+#  define REG_TMP0          (_REG_WINDOW_TMPS + 0)
+#  define REG_TMP1          (_REG_WINDOW_TMPS + 1)
+#  define _REG_OVLY_START   (_REG_WINDOW_TMPS + 2)
 #else
-#  define _REG_OVLY_START   _REG_CALL0_START
+#  define _REG_OVLY_START   _REG_WINDOW_TMPS
 #endif
 
 #ifdef CONFIG_XTENSA_USE_OVLY
diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S
index eb4324f901..c3e7030b02 100644
--- a/arch/xtensa/src/common/xtensa_context.S
+++ b/arch/xtensa/src/common/xtensa_context.S
@@ -146,22 +146,13 @@ _xtensa_context_save:
 	s32i	a3, a2, (4 * REG_LCOUNT)
 #endif
 
-#ifndef __XTENSA_CALL0_ABI__
-	mov		a9,  a0							/* Preserve ret addr */
-#endif
-
 #ifndef __XTENSA_CALL0_ABI__
 	/* To spill the reg windows, temp. need pre-interrupt stack ptr and
-	 * a4-15.  Need to save a9,12,13 temporarily (in frame temps) and
-	 * recover originals.  Interrupts need to be disabled below
-	 * XCHAL_EXCM_LEVEL and window overflow and underflow exceptions
-	 * disabled (assured by PS.EXCM == 1).
+	 * a4-15.  Interrupts need to be disabled below XCHAL_EXCM_LEVEL and
+	 * window overflow and underflow exceptions disabled (assured by
+	 * PS.EXCM == 1).
 	 */
 
-	s32i	a12, a2, (4 * REG_TMP0)			/* Temp. save stuff in stack frame */
-	s32i	a13, a2, (4 * REG_TMP1)
-	s32i	a9,  a2, (4 * REG_TMP2)
-
 #ifdef CONFIG_XTENSA_USE_OVLY
 	/* Save the overlay state if we are supporting overlays. Since we just
 	 * saved three registers, we can conveniently use them here. Note that
@@ -171,17 +162,16 @@ _xtensa_context_save:
 #error Overly support is not implemented
 #endif
 
-	l32i	a12, a2, (4 * REG_A12)			/* Recover original a9,12,13 */
-	l32i	a13, a2, (4 * REG_A13)
-	l32i	a9,  a2, (4 * REG_A9)
+	s32i	a0, a2, (4 * REG_TMP0)			/* Save return address */
+	s32i	sp, a2, (4 * REG_TMP1)			/* Save current stack pointer */
+	wsr		a2, EXCSAVE_1					/* Preserve register save area */
 
-#warning REVISIT: The following is probably not correct due to changes in registers
-	addi	sp,  sp, (4 * XCPTCONTEXT_SIZE)	/* Restore the interruptee's SP */
-	call0	_xtensa_window_spill			/* Preserves only a4,5,8,9,12,13 */
-	addi	sp,  sp, -(4 * XCPTCONTEXT_SIZE)
-	l32i	a12, sp, (4 * REG_TMP0)			/* Recover stuff from stack frame */
-	l32i	a13, sp, (4 * REG_TMP1)
-	l32i	a9,  sp, (4 * REG_TMP2)
+	l32i	sp, a2, (4 * REG_A1)			/* Restore the interruptee's SP */
+	call0	_xtensa_window_spill			/* Preserves only a4-a5, a8-a9, a12-a13 */
+
+	rsr		a2, EXCSAVE_1					/* Save interruptee's a0 */
+	l32i	a0,  a2, (4 * REG_TMP0)			/* Save return address */
+	l32i	sp,  a2, (4 * REG_TMP1)			/* Save current stack pointer */
 #endif
 
 	ret
diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c
index 975993af62..4a9eaa3b0d 100644
--- a/arch/xtensa/src/common/xtensa_dumpstate.c
+++ b/arch/xtensa/src/common/xtensa_dumpstate.c
@@ -130,9 +130,8 @@ static inline void xtensa_registerdump(void)
              (unsigned long)regs[REG_LCOUNT]);
 #endif
 #ifndef __XTENSA_CALL0_ABI__
-      _alert(" TMP0: %08lx  TMP1: %08lx  TMP2: %08lx\n",
-             (unsigned long)regs[REG_TMP0], (unsigned long)regs[REG_TMP1],
-             (unsigned long)regs[REG_TMP2]);
+      _alert(" TMP0: %08lx  TMP1: %08lx\n",
+             (unsigned long)regs[REG_TMP0], (unsigned long)regs[REG_TMP1]);
 #endif
     }
 }