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Tiva Timer: SYNC regiser is only available on GPTM0

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This commit is contained in:
Gregory Nutt 2015-01-08 08:07:31 -06:00
parent ff02574863
commit 4224fd0edc
1 changed files with 4 additions and 39 deletions
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43
arch/arm/src/tiva/chip/tiva_timer.h
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@ -68,7 +68,7 @@
#define TIVA_TIMER_CTL_OFFSET 0x000c /* GPTM Control */
#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
# define TIVA_TIMER_SYNC_OFFSET 0x0010 /* GPTM Synchronize */
# define TIVA_TIMER_SYNC_OFFSET 0x0010 /* GPTM Synchronize (GPTM0 only) */
#endif
#define TIVA_TIMER_IMR_OFFSET 0x0018 /* GPTM Interrupt Mask */
@ -165,11 +165,6 @@
#define TIVA_TIMER1_TAMR (TIVA_TIMER1_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER1_TBMR (TIVA_TIMER1_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER1_CTL (TIVA_TIMER1_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
# define TIVA_TIMER1_SYNC (TIVA_TIMER1_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER1_IMR (TIVA_TIMER1_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER1_RIS (TIVA_TIMER1_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER1_MIS (TIVA_TIMER1_BASE + TIVA_TIMER_MIS_OFFSET)
@ -214,11 +209,6 @@
#define TIVA_TIMER2_TAMR (TIVA_TIMER2_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER2_TBMR (TIVA_TIMER2_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER2_CTL (TIVA_TIMER2_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
# define TIVA_TIMER2_SYNC (TIVA_TIMER2_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER2_IMR (TIVA_TIMER2_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER2_RIS (TIVA_TIMER2_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER2_MIS (TIVA_TIMER2_BASE + TIVA_TIMER_MIS_OFFSET)
@ -263,11 +253,6 @@
#define TIVA_TIMER3_TAMR (TIVA_TIMER3_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER3_TBMR (TIVA_TIMER3_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER3_CTL (TIVA_TIMER3_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
# define TIVA_TIMER3_SYNC (TIVA_TIMER3_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER3_IMR (TIVA_TIMER3_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER3_RIS (TIVA_TIMER3_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER3_MIS (TIVA_TIMER3_BASE + TIVA_TIMER_MIS_OFFSET)
@ -310,13 +295,8 @@
#if TIVA_NTIMERS > 4
#define TIVA_TIMER4_CFG (TIVA_TIMER4_BASE + TIVA_TIMER_CFG_OFFSET)
#define TIVA_TIMER4_TAMR (TIVA_TIMER4_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER4_TBMR (TIVA_TIMER4_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER4_TBMR (TIVA_TIMER4_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER4_CTL (TIVA_TIMER4_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
# define TIVA_TIMER4_SYNC (TIVA_TIMER4_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER4_IMR (TIVA_TIMER4_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER4_RIS (TIVA_TIMER4_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER4_MIS (TIVA_TIMER4_BASE + TIVA_TIMER_MIS_OFFSET)
@ -361,11 +341,6 @@
#define TIVA_TIMER5_TAMR (TIVA_TIMER5_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER5_TBMR (TIVA_TIMER5_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER5_CTL (TIVA_TIMER5_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
# define TIVA_TIMER5_SYNC (TIVA_TIMER5_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER5_IMR (TIVA_TIMER5_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER5_RIS (TIVA_TIMER5_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER5_MIS (TIVA_TIMER5_BASE + TIVA_TIMER_MIS_OFFSET)
@ -410,11 +385,6 @@
#define TIVA_TIMER6_TAMR (TIVA_TIMER6_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER6_TBMR (TIVA_TIMER6_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER6_CTL (TIVA_TIMER6_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
# define TIVA_TIMER6_SYNC (TIVA_TIMER6_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER6_IMR (TIVA_TIMER6_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER6_RIS (TIVA_TIMER6_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER6_MIS (TIVA_TIMER6_BASE + TIVA_TIMER_MIS_OFFSET)
@ -459,11 +429,6 @@
#define TIVA_TIMER7_TAMR (TIVA_TIMER7_BASE + TIVA_TIMER_TAMR_OFFSET)
#define TIVA_TIMER7_TBMR (TIVA_TIMER7_BASE + TIVA_TIMER_TBMR_OFFSET)
#define TIVA_TIMER7_CTL (TIVA_TIMER7_BASE + TIVA_TIMER_CTL_OFFSET)
#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
# define TIVA_TIMER7_SYNC (TIVA_TIMER7_BASE + TIVA_TIMER_SYNC_OFFSET)
#endif
#define TIVA_TIMER7_IMR (TIVA_TIMER7_BASE + TIVA_TIMER_IMR_OFFSET)
#define TIVA_TIMER7_RIS (TIVA_TIMER7_BASE + TIVA_TIMER_RIS_OFFSET)
#define TIVA_TIMER7_MIS (TIVA_TIMER7_BASE + TIVA_TIMER_MIS_OFFSET)
@ -619,7 +584,7 @@
# define TIMER_CTL_TBPWML (1 << 14) /* Bit 14: GPTM Timer B PWM Output Level */
#endif
/* GPTM Synchronize */
/* GPTM Synchronize (GPTM0 only) */
#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
# define TIMER_SYNC_SYNCT_NONE 0 /* GPTMn is not affected */
@ -958,7 +923,7 @@
#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C)
# define TIMER_TBPV_PSS_SHIFT (0) /* Bits 0-15: GPTM Timer B Prescaler Value */
# define TIMER_TBPS_PSS_MASK (0xffff << TIMER_TBPS_PSS_SHIFT)
# define TIMER_TBPS_PSS(n) ((uint32_t)(n) << TIMER_TBPS_PSS_SHIFT)
# define TIMER_TBPS_PSS(n) ((uint32_t)(n) << TIMER_TBPS_PSS_SHIFT)
#endif
/* GPTM DMA Event (DMAEV) */