SAMDL: Added DMAC header for SAMD, fixed up sam_dmac to compile with debugging enabled
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Matt Thompson
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arch/arm/src/samdl/chip/samd_dmac.h
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arch/arm/src/samdl/chip/samd_dmac.h
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/********************************************************************************************
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* arch/arm/src/samdl/chip/samd_dmac.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Matt Thompson <matt@extent3d.com>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DMAC_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DMAC_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* DMAC register offsets ********************************************************************/
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#define SAM_DMAC_CTRL_OFFSET 0x0000 /* Control Register */
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#define SAM_DMAC_CRCCTRL_OFFSET 0x0002 /* CRC Control Register */
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#define SAM_DMAC_CRCDATAIN_OFFSET 0x0004 /* CRC Data Input Register */
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#define SAM_DMAC_CRCCHKSUM_OFFSET 0x0008 /* CRC Checksum Register */
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#define SAM_DMAC_CRCSTATUS_OFFSET 0x000c /* CRC Status Register */
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#define SAM_DMAC_DBGCTRL_OFFSET 0x000d /* Debug Control Register */
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#define SAM_DMAC_QOSCTRL_OFFSET 0x000e /* Quality of Service Control Register */
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#define SAM_DMAC_SWTRIGCTRL_OFFSET 0x0010 /* Software Trigger Control Register */
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#define SAM_DMAC_PRICTRL0_OFFSET 0x0014 /* Priority Control 0 Register */
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#define SAM_DMAC_INTPEND_OFFSET 0x0020 /* Interrupt Pending Register */
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#define SAM_DMAC_INTSTATUS_OFFSET 0x0024 /* Interrupt Status Register */
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#define SAM_DMAC_BUSYCH_OFFSET 0x0028 /* Busy Channels Register */
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#define SAM_DMAC_PENDCH_OFFSET 0x002c /* Pending Channels Register */
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#define SAM_DMAC_ACTIVE_OFFSET 0x0030 /* Active Channels and Levels Register */
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#define SAM_DMAC_BASEADDR_OFFSET 0x0034 /* Descriptor Memory Section Base Address Register */
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#define SAM_DMAC_WRBADDR_OFFSET 0x0038 /* Write-Back Memory Section Base Address Register */
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#define SAM_DMAC_CHID_OFFSET 0x003f /* Channel ID Register */
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#define SAM_DMAC_CHCTRLA_OFFSET 0x0040 /* Channel Control A Register */
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#define SAM_DMAC_CHCTRLB_OFFSET 0x0044 /* Channel Control B Register */
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#define SAM_DMAC_CHINTENCLR_OFFSET 0x004c /* Channel Interrupt Enable Clear Register */
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#define SAM_DMAC_CHINTENSET_OFFSET 0x004d /* Channel Interrupt Enable Set Register */
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#define SAM_DMAC_CHINTFLAG_OFFSET 0x004e /* Channel Interrupt Flag Status and Clear Register */
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#define SAM_DMAC_CHSTATUS_OFFSET 0x004f /* Channel Status Register */
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/* LPSRAM Registers Relative to BASEADDR or WRBADDR */
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#define SAM_LPSRAM_BTCTRL_OFFSET 0x0000 /* Block Transfer Control Register */
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#define SAM_LPSRAM_BTCNT_OFFSET 0x0002 /* Block Transfer Count Register */
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#define SAM_LPSRAM_SRCADDR_OFFSET 0x0004 /* Block Transfer Source Address Register */
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#define SAM_LPSRAM_DSTADDR_OFFSET 0x0008 /* Block Transfer Destination Address Register */
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#define SAM_LPSRAM_DESCADDR_OFFSET 0x000c /* Next Address Descriptor Register */
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/* DMAC register addresses ******************************************************************/
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#define SAM_DMAC_CTRL (SAM_DMAC_BASE+SAM_DMAC_CTRL_OFFSET)
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#define SAM_DMAC_CRCCTRL (SAM_DMAC_BASE+SAM_DMAC_CRCCTRL_OFFSET)
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#define SAM_DMAC_CRCDATAIN (SAM_DMAC_BASE+SAM_DMAC_CRCDATAIN_OFFSET)
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#define SAM_DMAC_CRCCHKSUM (SAM_DMAC_BASE+SAM_DMAC_CRCCHKSUM_OFFSET)
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#define SAM_DMAC_CRCSTATUS (SAM_DMAC_BASE+SAM_DMAC_CRCSTATUS_OFFSET)
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#define SAM_DMAC_DBGCTRL (SAM_DMAC_BASE+SAM_DMAC_DBGCTRL_OFFSET)
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#define SAM_DMAC_QOSCTRL (SAM_DMAC_BASE+SAM_DMAC_QOSCTRL_OFFSET)
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#define SAM_DMAC_SWTRIGCTRL (SAM_DMAC_BASE+SAM_DMAC_SWTRIGCTRL_OFFSET)
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#define SAM_DMAC_PRICTRL0 (SAM_DMAC_BASE+SAM_DMAC_PRICTRL0_OFFSET)
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#define SAM_DMAC_INTPEND (SAM_DMAC_BASE+SAM_DMAC_INTPEND_OFFSET)
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#define SAM_DMAC_INTSTATUS (SAM_DMAC_BASE+SAM_DMAC_INTSTATUS_OFFSET)
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#define SAM_DMAC_BUSYCH (SAM_DMAC_BASE+SAM_DMAC_BUSYCH_OFFSET)
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#define SAM_DMAC_PENDCH (SAM_DMAC_BASE+SAM_DMAC_PENDCH_OFFSET)
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#define SAM_DMAC_ACTIVE (SAM_DMAC_BASE+SAM_DMAC_ACTIVE_OFFSET)
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#define SAM_DMAC_BASEADDR (SAM_DMAC_BASE+SAM_DMAC_BASEADDR_OFFSET)
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#define SAM_DMAC_WRBADDR (SAM_DMAC_BASE+SAM_DMAC_WRBADDR_OFFSET)
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#define SAM_DMAC_CHID (SAM_DMAC_BASE+SAM_DMAC_CHID_OFFSET)
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#define SAM_DMAC_CHCTRLA (SAM_DMAC_BASE+SAM_DMAC_CHCTRLA_OFFSET)
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#define SAM_DMAC_CHCTRLB (SAM_DMAC_BASE+SAM_DMAC_CHCTRLB_OFFSET)
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#define SAM_DMAC_CHINTENCLR (SAM_DMAC_BASE+SAM_DMAC_CHINTENCLR_OFFSET)
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#define SAM_DMAC_CHINTENSET (SAM_DMAC_BASE+SAM_DMAC_CHINTENSET_OFFSET)
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#define SAM_DMAC_CHINTFLAG (SAM_DMAC_BASE+SAM_DMAC_CHINTFLAG_OFFSET)
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#define SAM_DMAC_CHSTATUS (SAM_DMAC_BASE+SAM_DMAC_CHSTATUS_OFFSET)
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/* DMAC register bit definitions ************************************************************/
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/* Control Register */
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#define DMAC_CTRL_SWRST (1 << 0) /* Bit 0: Software Reset */
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#define DMAC_CTRL_DMAENABLE (1 << 1) /* Bit 1: DMA Enable */
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#define DMAC_CTRL_CRCENABLE (1 << 2) /* Bit 2: CRC Enable */
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#define DMAC_CTRL_LVLEN0 (1 << 8) /* Bit 8: Priority level 0 Enable */
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#define DMAC_CTRL_LVLEN1 (1 << 9) /* Bit 9: Priority level 1 Enable */
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#define DMAC_CTRL_LVLEN2 (1 << 10) /* Bit 10: Priority level 2 Enable */
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#define DMAC_CTRL_LVLEN3 (1 << 11) /* Bit 10: Priority level 2 Enable */
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/* CRC Control Register */
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#define DMAC_CRCCTRL_CRCBEATSIZE_SHIFT (0) /* Bits 0-1: CRC beat size */
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#define DMAC_CRCCTRL_CRCBEATSIZE_MASK (3 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT)
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# define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (0 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 8-bit bus transfer */
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# define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (1 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 16-bit bus transfer */
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# define DMAC_CRCCTRL_CRCBEATSIZE_WORD (2 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 32-bit bus transfer */
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#define DMAC_CRCCTRL_CRCPOLY_SHIFT (2) /* Bits 2-3: CRC polynomial type */
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#define DMAC_CRCCTRL_CRCPOLY_MASK (3 < DMAC_CRCCTRL_CRCPOLY_SHIFT)
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# define DMAC_CRCCTRL_CRCPOLY_CRC16 (0 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC-16 (CRC-CCITT) */
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# define DMAC_CRCCTRL_CRCPOLY_CRC32 (1 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC32 (IEEE 802.3) */
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#define DMAC_CRCCTRL_CRCSRC_SHIFT (8) /* Bits 8-13: CRC Input Source */
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#define DMAC_CRCCTRL_CRCSRC_MASK (0x3f < DMAC_CRCCTRL_CRCSRC_SHIFT)
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# define DMAC_CRCCTRL_CRCSRC_NOACTION (0 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* No action */
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# define DMAC_CRCCTRL_CRCSRC_IO (1 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* I/O interface */
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# define DMAC_CRCCTRL_CRCSRC_CHAN(n) (((uint32_t)(n) + 0x20) < DMAC_CRCCTRL_CRCSRC_SHIFT)
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/* CRC Data Input Register (32-bit value) */
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/* CRC Checksum Register (32-bit value) */
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/* CRC Status Register */
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#define DMAC_CRCSTATUS_CRCBUSY (1 << 0) /* Bit 0: CRC module busy */
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#define DMAC_CRCSTATUS_CRCZERO (1 << 1) /* Bit 1: CRC zero */
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/* Debug Control Register */
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#define DMAC_DBGCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */
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/* Quality of Service Control Register */
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#define DMAC_QOSCTRL_WRBQOS_SHIFT (0) /* Bits 0-1: Write back quality of service */
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#define DMAC_QOSCTRL_WRBQOS_MASK (3 << DMAC_QOSCTRL_WRBQOS_SHIFT)
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# define DMAC_QOSCTRL_WRBQOS_DISABLE (0 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Background */
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# define DMAC_QOSCTRL_WRBQOS_LOW (1 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive bandwidth */
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# define DMAC_QOSCTRL_WRBQOS_MEDIUM (2 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive latency */
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# define DMAC_QOSCTRL_WRBQOS_HIGH (3 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Critical latency */
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#define DMAC_QOSCTRL_FQOS_SHIFT (2) /* Bits 2-3: Fetch quality of service */
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#define DMAC_QOSCTRL_FQOS_MASK (3 << DMAC_QOSCTRL_FQOS_SHIFT)
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# define DMAC_QOSCTRL_FQOS_DISABLE (0 << DMAC_QOSCTRL_FQOS_SHIFT) /* Background */
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# define DMAC_QOSCTRL_FQOS_LOW (1 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive bandwidth */
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# define DMAC_QOSCTRL_FQOS_MEDIUM (2 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive latency */
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# define DMAC_QOSCTRL_FQOS_HIGH (3 << DMAC_QOSCTRL_FQOS_SHIFT) /* Critical latency */
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#define DMAC_QOSCTRL_DQOS_SHIFT (4) /* Bits 4-5: Data transfer quality of service */
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#define DMAC_QOSCTRL_DQOS_MASK (3 << DMAC_QOSCTRL_DQOS_SHIFT)
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# define DMAC_QOSCTRL_DQOS_DISABLE (0 << DMAC_QOSCTRL_DQOS_SHIFT) /* Background */
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# define DMAC_QOSCTRL_DQOS_LOW (1 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive bandwidth */
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# define DMAC_QOSCTRL_DQOS_MEDIUM (2 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive latency */
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# define DMAC_QOSCTRL_DQOS_HIGH (3 << DMAC_QOSCTRL_DQOS_SHIFT) /* Critical latency */
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/* Common bit definitions for: Software Trigger Control Register, Interrupt Status Register,
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* Busy Channels Register, and Pending Channels Register
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*/
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#define DMAC_CHAN(n) (1 << (n)) /* DMAC Channel n, n=0-11 */
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/* Priority Control 0 Register */
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#define DMAC_PRICTRL0_LVLPRI0_SHIFT (0) /* Bits 0-3: Level 0 channel priority number */
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#define DMAC_PRICTRL0_LVLPRI0_MASK (15 << DMAC_PRICTRL0_LVLPRI0_SHIFT)
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# define DMAC_PRICTRL0_LVLPRI0(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI0_SHIFT)
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#define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitrarion enable */
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#define DMAC_PRICTRL0_LVLPRI1_SHIFT (8) /* Bits 8-11: Level 1 channel priority number */
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#define DMAC_PRICTRL0_LVLPRI1_MASK (15 << DMAC_PRICTRL0_LVLPRI1_SHIFT)
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# define DMAC_PRICTRL0_LVLPRI1(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI1_SHIFT)
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#define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitrarion enable */
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#define DMAC_PRICTRL0_LVLPRI2_SHIFT (16) /* Bits 16-18: Level 2 channel priority number */
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#define DMAC_PRICTRL0_LVLPRI2_MASK (7 << DMAC_PRICTRL0_LVLPRI2_SHIFT)
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# define DMAC_PRICTRL0_LVLPRI2(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI2_SHIFT)
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#define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitrarion enable */
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#define DMAC_PRICTRL0_LVLPRI3_SHIFT (24) /* Bits 24-27: Level 3 channel priority number */
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#define DMAC_PRICTRL0_LVLPRI3_MASK (7 << DMAC_PRICTRL0_LVLPRI3_SHIFT)
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# define DMAC_PRICTRL0_LVLPRI3(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI3_SHIFT)
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#define DMAC_PRICTRL0_RRLVLEN3 (1 << 31) /* Bit 23: Level 3 round-robin arbitrarion enable */
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/* Interrupt Pending Register */
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#define DMAC_INTPEND_ID_SHIFT (0) /* Bit 0-3: Channel ID */
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#define DMAC_INTPEND_ID_MASK (15 << DMAC_INTPEND_ID_SHIFT)
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#define DMAC_INTPEND_TERR (1 << 8) /* Bit 8: Transfer error */
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#define DMAC_INTPEND_TCMPL (1 << 9) /* Bit 9: Transfer complete */
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#define DMAC_INTPEND_SUSP (1 << 10) /* Bit 10: Channel suspend */
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#define DMAC_INTPEND_FERR (1 << 13) /* Bit 13: Fetch error */
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#define DMAC_INTPEND_BUSY (1 << 14) /* Bit 14: Busy */
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#define DMAC_INTPEND_PEND (1 << 15) /* Bit 15: Pending */
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/* Interrupt Status Register */
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/* Busy Channels Register */
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/* Pending Channels Register */
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/* Active Channels and Levels Register */
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#define DMAC_ACTIVE_LVLEX0 (1 << 0) /* Bit 0: Level 0 channel trigger request executing */
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#define DMAC_ACTIVE_LVLEX1 (1 << 1) /* Bit 1: Level 1 channel trigger request executing */
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#define DMAC_ACTIVE_LVLEX2 (1 << 2) /* Bit 2: Level 2 channel trigger request executing */
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#define DMAC_ACTIVE_LVLEX3 (1 << 3) /* Bit 3: Level 3 channel trigger request executing */
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#define DMAC_ACTIVE_ID_SHIFT (8) /* Bits 8-11: Active channel ID */
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#define DMAC_ACTIVE_ID_MASK (15 << DMAC_ACTIVE_ID_SHIFT)
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#define DMAC_ACTIVE_ABUSY (1 << 15) /* Bit 15: Active channel busy */
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#define DMAC_ACTIVE_BTCNT_SHIFT (16) /* Bit 16-31: Active channel block transfer count */
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#define DMAC_ACTIVE_BTCNT_MASK (0xffff << DMAC_ACTIVE_BTCNT_SHIFT)
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/* Descriptor Memory Section Base Address Register (32-bit address) */
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/* Write-Back Memory Section Base Address Register (31-bit address) */
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/* Channel ID Register */
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#define DMAC_CHID_MASK 0x0f /* Bits 0-3: Channel ID */
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/* Channel Control A Register */
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#define DMAC_CHCTRLA_SWRST (1 << 0) /* Bit 0: Channel software reset */
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#define DMAC_CHCTRLA_ENABLE (1 << 1) /* Bit 1: Channel enable */
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/* Channel Control B Register */
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#define DMAC_CHCTRLB_EVACT_SHIFT (0) /* Bits 0-2: Event input action */
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#define DMAC_CHCTRLB_EVACT_MASK (7 << DMAC_CHCTRLB_EVACT_SHIFT)
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# define DMAC_CHCTRLB_EVACT_NOACT (0 << DMAC_CHCTRLB_EVACT_SHIFT) /* No action */
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# define DMAC_CHCTRLB_EVACT_TRIG (1 << DMAC_CHCTRLB_EVACT_SHIFT) /* Normal Transfer and Conditional Transfer on Strobe
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trigger */
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# define DMAC_CHCTRLB_EVACT_CTRIG (2 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional transfer trigger */
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# define DMAC_CHCTRLB_EVACT_CBLOCK (3 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional block transfer */
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# define DMAC_CHCTRLB_EVACT_SUSPEND (4 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel suspend operation */
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# define DMAC_CHCTRLB_EVACT_RESUME (5 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel resume operation */
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# define DMAC_CHCTRLB_EVACT_SSKIP (6 << DMAC_CHCTRLB_EVACT_SHIFT) /* Skip next block suspend action */
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#define DMAC_CHCTRLB_EVIE (1 << 3) /* Bit 3: Channel event input enable */
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#define DMAC_CHCTRLB_EVOE (1 << 4) /* Bit 4: Channel event output enable */
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#define DMAC_CHCTRLB_LVL_SHIFT (5) /* Bits 5-6: Channel arbitration level */
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#define DMAC_CHCTRLB_LVL_MASK (3 << DMAC_CHCTRLB_LVL_SHIFT)
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# define DMAC_CHCTRLB_LVL(n) ((uint32_t)(n) << DMAC_CHCTRLB_LVL_SHIFT)
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# define DMAC_CHCTRLB_LVL_LVL0 (0 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 0 */
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# define DMAC_CHCTRLB_LVL_LVL1 (1 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 1 */
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# define DMAC_CHCTRLB_LVL_LVL2 (2 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 2 */
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# define DMAC_CHCTRLB_LVL_LVL3 (3 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 3 */
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#define DMAC_CHCTRLB_TRIGSRC_SHIFT (8) /* Bits 8-13: Trigger source */
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#define DMAC_CHCTRLB_TRIGSRC_MASK (0x3f << DMAC_CHCTRLB_TRIGSRC_SHIFT)
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#define DMAC_CHCTRLB_TRIGSRC(n) ((uint32_t)(n) << DMAC_CHCTRLB_TRIGSRC_SHIFT)
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#define DMAC_CHCTRLB_TRIGACT_SHIFT (22) /* Bits 22-23: Trigger action */
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#define DMAC_CHCTRLB_TRIGACT_MASK (3 << DMAC_CHCTRLB_TRIGACT_SHIFT)
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# define DMAC_CHCTRLB_TRIGACT_BLOCK (0 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each action */
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# define DMAC_CHCTRLB_TRIGACT_BEAT (2 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for beat transfer */
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# define DMAC_CHCTRLB_TRIGACT_TRANSACT (3 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each transaction */
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#define DMAC_CHCTRLB_CMD_SHIFT (24) /* Bits 24-25: Software command */
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#define DMAC_CHCTRLB_CMD_MASK (3 << DMAC_CHCTRLB_CMD_SHIFT)
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# define DMAC_CHCTRLB_CMD_NOACTION (0 << DMAC_CHCTRLB_CMD_SHIFT) /* No action */
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# define DMAC_CHCTRLB_CMD_SUSPEND (1 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel suspend operation */
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# define DMAC_CHCTRLB_CMD_RESUME (2 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel resume operation */
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/* Values for use with the DMAC_CHCTRLB_TRIGSRC(n) macro: */
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#define DMAC_TRIGSRC_DISABLE (0) /* Only software/event triggers */
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#define DMAC_TRIGSRC_SERCOM0_RX (1) /* SERCOM0 RX Trigger */
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#define DMAC_TRIGSRC_SERCOM0_TX (2) /* SERCOM0 TX Trigger */
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#define DMAC_TRIGSRC_SERCOM1_RX (3) /* SERCOM1 RX Trigger */
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#define DMAC_TRIGSRC_SERCOM1_TX (4) /* SERCOM1 TX Trigger */
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#define DMAC_TRIGSRC_SERCOM2_RX (5) /* SERCOM2 RX Trigger */
|
||||
#define DMAC_TRIGSRC_SERCOM2_TX (6) /* SERCOM2 TX Trigger */
|
||||
#define DMAC_TRIGSRC_SERCOM3_RX (7) /* SERCOM3 RX Trigger */
|
||||
#define DMAC_TRIGSRC_SERCOM3_TX (8) /* SERCOM3 TX Trigger */
|
||||
#define DMAC_TRIGSRC_SERCOM4_RX (9) /* SERCOM4 RX Trigger */
|
||||
#define DMAC_TRIGSRC_SERCOM4_TX (10) /* SERCOM4 TX Trigger */
|
||||
#define DMAC_TRIGSRC_SERCOM5_RX (11) /* SERCOM4 RX Trigger */
|
||||
#define DMAC_TRIGSRC_SERCOM5_TX (12) /* SERCOM4 TX Trigger */
|
||||
#define DMAC_TRIGSRC_TCC0_OVF (13) /* TCC0 Overflow Trigger */
|
||||
#define DMAC_TRIGSRC_TCC0_MC0 (14) /* TCC0 Match/Compare 0 Trigger */
|
||||
#define DMAC_TRIGSRC_TCC0_MC1 (15) /* TCC0 Match/Compare 1 Trigger */
|
||||
#define DMAC_TRIGSRC_TCC0_MC2 (16) /* TCC0 Match/Compare 2 Trigger */
|
||||
#define DMAC_TRIGSRC_TCC0_MC3 (17) /* TCC0 Match/Compare 3 Trigger */
|
||||
#define DMAC_TRIGSRC_TCC1_OVF (18) /* TCC1 Overflow Trigger */
|
||||
#define DMAC_TRIGSRC_TCC1_MC0 (19) /* TCC1 Match/Compare 0 Trigger */
|
||||
#define DMAC_TRIGSRC_TCC1_MC1 (20) /* TCC1 Match/Compare 1 Trigger */
|
||||
#define DMAC_TRIGSRC_TCC2_OVF (21) /* TCC2 Overflow Trigger */
|
||||
#define DMAC_TRIGSRC_TCC2_MC0 (22) /* TCC2 Match/Compare 0 Trigger */
|
||||
#define DMAC_TRIGSRC_TCC2_MC1 (23) /* TCC2 Match/Compare 1 Trigger */
|
||||
#define DMAC_TRIGSRC_TC0_OVF (24) /* TC0 Overflow Trigger */
|
||||
#define DMAC_TRIGSRC_TC0_MC0 (25) /* TC0 Match/Compare 0 Trigger */
|
||||
#define DMAC_TRIGSRC_TC0 MC1 (26) /* TC0 Match/Compare 1 Trigger */
|
||||
#define DMAC_TRIGSRC_TC1_OVF (27) /* TC1 Overflow Trigger */
|
||||
#define DMAC_TRIGSRC_TC1_MC0 (28) /* TC1 Match/Compare 0 Trigger */
|
||||
#define DMAC_TRIGSRC_TC1_MC1 (29) /* TC1 Match/Compare 1 Trigger */
|
||||
#define DMAC_TRIGSRC_TC2_OVF (30) /* TC2 Overflow Trigger */
|
||||
#define DMAC_TRIGSRC_TC2_MC0 (31) /* TC2 Match/Compare 0 Trigger */
|
||||
#define DMAC_TRIGSRC_TC2_MC1 (32) /* TC2 Match/Compare 1 Trigger */
|
||||
#define DMAC_TRIGSRC_TC3_OVF (33) /* TC3 Overflow Trigger */
|
||||
#define DMAC_TRIGSRC_TC3_MC0 (34) /* TC3 Match/Compare 0 Trigger */
|
||||
#define DMAC_TRIGSRC_TC3_MC1 (35) /* TC3 Match/Compare 1 Trigger */
|
||||
#define DMAC_TRIGSRC_TC4_OVF (36) /* TC4 Overflow Trigger */
|
||||
#define DMAC_TRIGSRC_TC4_MC0 (37) /* TC4 Match/Compare 0 Trigger */
|
||||
#define DMAC_TRIGSRC_TC4_MC1 (38) /* TC4 Match/Compare 1 Trigger */
|
||||
#define DMAC_TRIGSRC_ADC_RESRDY (39) /* ADC Result Ready Trigger */
|
||||
#define DMAC_TRIGSRC_DAC_EMPTY (40) /* DAC0 Empty Trigger */
|
||||
#define DMAC_TRIGSRC_I2S0_RX (41) /* I2S0 RX Trigger */
|
||||
#define DMAC_TRIGSRC_I2S1_RX (42) /* I2S1 RX Trigger */
|
||||
#define DMAC_TRIGSRC_I2S0_TX (43) /* I2S0 TX Trigger */
|
||||
#define DMAC_TRIGSRC_I2S1_TX (44) /* I2S1 TX Trigger */
|
||||
|
||||
/* Common register bit definitions: Channel Interrupt Enable Clear Register, Channel Interrupt
|
||||
* Enable Set Register, and Channel Interrupt Flag Status and Clear Register
|
||||
*/
|
||||
|
||||
#define DMAC_INT_TERR (1 << 0) /* Bit 0: Transfer error interrupt */
|
||||
#define DMAC_INT_TCMPL (1 << 1) /* Bit 1: Channel transfer complete interrupt */
|
||||
#define DMAC_INT_SUSP (1 << 2) /* Bit 2: Channel suspend interrupt */
|
||||
#define DMAC_INT_ALL (0x07)
|
||||
|
||||
/* Channel Status Register */
|
||||
|
||||
#define DMAC_CHSTATUS_PEND (1 << 0) /* Bit 0: Chennel pending */
|
||||
#define DMAC_CHSTATUS_BUSY (1 << 1) /* Bit 1: Channel busy */
|
||||
#define DMAC_CHSTATUS_FERR (1 << 2) /* Bit 2: Channel fetch error */
|
||||
|
||||
/* Block Transfer Control Register */
|
||||
|
||||
#define LPSRAM_BTCTRL_VALID (1 << 0) /* Bit 0: Descriptor valid */
|
||||
#define LPSRAM_BTCTRL_EVOSEL_SHIFT (1) /* Bits 1-2: Event output selection */
|
||||
#define LPSRAM_BTCTRL_EVOSEL_MASK (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT)
|
||||
# define LPSRAM_BTCTRL_EVOSEL_DISABLE (0 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event generation disabled */
|
||||
# define LPSRAM_BTCTRL_EVOSEL_BLOCK (1 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when block transfer complete */
|
||||
# define LPSRAM_BTCTRL_EVOSEL_BEAT (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when beat transfer complete */
|
||||
#define LPSRAM_BTCTRL_BLOCKACT_SHIFT (3) /* Bits 3-4: Block action */
|
||||
#define LPSRAM_BTCTRL_BLOCKACT_MASK (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT)
|
||||
# define LPSRAM_BTCTRL_BLOCKACT_NOACT (0 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer */
|
||||
# define LPSRAM_BTCTRL_BLOCKACT_INT (1 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer + block int */
|
||||
# define LPSRAM_BTCTRL_BLOCKACT_SUSPEND (2 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel suspend operation is completed */
|
||||
# define LPSRAM_BTCTRL_BLOCKACT_BOTH (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Both channel suspend operation + block int */
|
||||
#define LPSRAM_BTCTRL_BEATSIZE_SHIFT (8) /* Bits 8-9: Beat size */
|
||||
#define LPSRAM_BTCTRL_BEATSIZE_MASK (3 << LPSRAM_BTCTRL_BEATSIZE_SHIFT)
|
||||
# define LPSRAM_BTCTRL_BEATSIZE_BYTE (0 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 8-bit bus transfer */
|
||||
# define LPSRAM_BTCTRL_BEATSIZE_HWORD (1 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 16-bit bus transfer */
|
||||
# define LPSRAM_BTCTRL_BEATSIZE_WORD (2 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 32-bit bus transfer */
|
||||
#define LPSRAM_BTCTRL_SRCINC (1 << 10) /* Bit 10: Source address increment enable */
|
||||
#define LPSRAM_BTCTRL_DSTINC (1 << 11) /* Bit 11: Destination address increment enable */
|
||||
#define LPSRAM_BTCTRL_STEPSEL (1 << 12) /* Bit 12: Step selection */
|
||||
#define LPSRAM_BTCTRL_STEPSIZE_SHIFT (13) /* Bits 13-15: Address increment step */
|
||||
#define LPSRAM_BTCTRL_STEPSIZE_MASK (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT)
|
||||
# define LPSRAM_BTCTRL_STEPSIZE_X1 (0 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 1 */
|
||||
# define LPSRAM_BTCTRL_STEPSIZE_X2 (1 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 2 */
|
||||
# define LPSRAM_BTCTRL_STEPSIZE_X4 (2 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 4 */
|
||||
# define LPSRAM_BTCTRL_STEPSIZE_X8 (3 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 8 */
|
||||
# define LPSRAM_BTCTRL_STEPSIZE_X16 (4 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 16 */
|
||||
# define LPSRAM_BTCTRL_STEPSIZE_X32 (5 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 32 */
|
||||
# define LPSRAM_BTCTRL_STEPSIZE_X64 (6 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 64 */
|
||||
# define LPSRAM_BTCTRL_STEPSIZE_X128 (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */
|
||||
|
||||
/* Block Transfer Count Register (16-bit count) */
|
||||
/* Block Transfer Source Address Register (32-bit address) */
|
||||
/* Block Transfer Destination Address Register (32-bit address) */
|
||||
/* Next Address Descriptor Register (32-bit address) */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
/* DMA descriptor */
|
||||
|
||||
struct dma_desc_s
|
||||
{
|
||||
uint16_t btctrl; /* Block Transfer Control Register */
|
||||
uint16_t btcnt; /* Block Transfer Count Register */
|
||||
uint32_t srcaddr; /* Block Transfer Source Address Register */
|
||||
uint32_t dstaddr; /* Block Transfer Destination Address Register */
|
||||
uint32_t descaddr; /* Next Address Descriptor Register */
|
||||
};
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DMAC_H */
|
||||
@ -500,7 +500,7 @@ static struct dma_desc_s *sam_append_desc(struct sam_dmach_s *dmach,
|
||||
{
|
||||
/* There is no previous link. This is the new head of the list */
|
||||
|
||||
DEBUGASSERT(desc == g_base_desc[dmach->dc_chan]);
|
||||
DEBUGASSERT(desc == &g_base_desc[dmach->dc_chan]);
|
||||
}
|
||||
|
||||
#if CONFIG_SAMDL_DMAC_NDESC > 0
|
||||
@ -627,7 +627,7 @@ static int sam_txbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
|
||||
uint16_t btcnt;
|
||||
uint16_t tmp;
|
||||
|
||||
DEBUGASSERT(dmac->dc_dir == DMADIR_UNKOWN || dmac->dc_dir == DMADIR_TX);
|
||||
DEBUGASSERT(dmach->dc_dir == DMADIR_UNKOWN || dmach->dc_dir == DMADIR_TX);
|
||||
|
||||
/* Set up the Block Transfer Control Register configuration:
|
||||
*
|
||||
@ -703,7 +703,7 @@ static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
|
||||
uint16_t btcnt;
|
||||
uint16_t tmp;
|
||||
|
||||
DEBUGASSERT(dmac->dc_dir == DMADIR_UNKOWN || dmac->dc_dir == DMADIR_RX);
|
||||
DEBUGASSERT(dmach->dc_dir == DMADIR_UNKOWN || dmach->dc_dir == DMADIR_RX);
|
||||
|
||||
/* Set up the Block Transfer Control Register configuration:
|
||||
*
|
||||
@ -1218,10 +1218,13 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
|
||||
/* Enable the channel */
|
||||
|
||||
ctrla = DMAC_CHCTRLA_ENABLE;
|
||||
|
||||
#ifdef CONFIG_ARCH_FAMILY_SAML21
|
||||
if (dmach->dc_flags & DMACH_FLAG_RUNINSTDBY)
|
||||
{
|
||||
ctrla |= DMAC_CHCTRLA_RUNSTDBY;
|
||||
}
|
||||
#endif
|
||||
|
||||
putreg8(ctrla, SAM_DMAC_CHCTRLA);
|
||||
|
||||
@ -1272,19 +1275,18 @@ void sam_dmastop(DMA_HANDLE handle)
|
||||
#ifdef CONFIG_DEBUG_DMA_INFO
|
||||
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
|
||||
{
|
||||
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
|
||||
uintptr_t base;
|
||||
irqstate_t flags;
|
||||
|
||||
/* Sample DMAC registers. */
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
regs->ctrl = getreg16(SAM_DMAC_CTRL); /* Control Register */
|
||||
regs->crcctrl = getreg16(SAM_DMAC_CRCCTRL); /* CRC Control Register */
|
||||
regs->crcdatain = getreg32(SAM_DMAC_CRCDATAIN); /* CRC Data Input Register */
|
||||
regs->crcchksum = getreg32(SAM_DMAC_CRCCHKSUM); /* CRC Checksum Register */
|
||||
regs->crcstatus = getreg8(SAM_DMAC_CRCSTATUS); /* CRC Status Register */
|
||||
regs->errctrl = getreg8(SAM_DMAC_DBGCTRL); /* Debug Control Register */
|
||||
regs->dbgctrl = getreg8(SAM_DMAC_DBGCTRL); /* Debug Control Register */
|
||||
regs->qosctrl = getreg8(SAM_DMAC_QOSCTRL); /* Quality of Service Control Register */
|
||||
regs->swtrigctrl = getreg32(SAM_DMAC_SWTRIGCTRL); /* Software Trigger Control Register */
|
||||
regs->prictrl0 = getreg32(SAM_DMAC_PRICTRL0); /* Priority Control 0 Register */
|
||||
@ -1300,6 +1302,8 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
|
||||
regs->chctrlb = getreg32(SAM_DMAC_CHCTRLB); /* Channel Control B Register */
|
||||
regs->chintflag = getreg8(SAM_DMAC_CHINTFLAG); /* Channel Interrupt Flag Status and Clear Register */
|
||||
regs->chstatus = getreg8(SAM_DMAC_CHSTATUS); /* Channel Status Register */
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif /* CONFIG_DEBUG_DMA_INFO */
|
||||
|
||||
@ -1325,13 +1329,13 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
|
||||
dmainfo(" CTRL: %04x CRCCTRL: %04x CRCDATAIN: %08x CRCCHKSUM: %08x\n",
|
||||
regs->ctrl, regs->crcctrl, regs->crcdatain, regs->crcchksum);
|
||||
dmainfo(" CRCSTATUS: %02x DBGCTRL: %02x QOSCTRL: %02x SWTRIGCTRL: %08x\n",
|
||||
regs->crcstatus, regs->errctrl, regs->qosctrl, regs->swtrigctrl);
|
||||
regs->crcstatus, regs->dbgctrl, regs->qosctrl, regs->swtrigctrl);
|
||||
dmainfo(" PRICTRL0: %08x INTPEND: %04x INSTSTATUS: %08x BUSYCH: %08x\n",
|
||||
regs->prictrl0, regs->intpend, regs->intstatus, regs->busych);
|
||||
dmainfo(" PENDCH: %08x ACTIVE: %08x BASEADDR: %08x WRBADDR: %08x\n",
|
||||
regs->pendch, regs->active, regs->baseaddr, regs->wrbaddr);
|
||||
dmainfo(" CHID: %02x CHCRTRLA: %02x CHCRTRLB: %08x CHINFLAG: %02x\n",
|
||||
regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag,
|
||||
regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag);
|
||||
dmainfo(" CHSTATUS: %02x\n",
|
||||
regs->chstatus);
|
||||
}
|
||||
|
||||
@ -50,8 +50,8 @@
|
||||
|
||||
#ifdef CONFIG_SAMDL_DMAC
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
|
||||
# error Missing support for the SAMD20 architecture
|
||||
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
|
||||
# include "chip/samd_dmac.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
|
||||
# include "chip/saml_dmac.h"
|
||||
#else
|
||||
|
||||
Loading…
Reference in New Issue
Block a user