SAMA5D4-EK LCDC: Change source clock to 2*Mck seems to solve stability issues
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@ -2976,7 +2976,7 @@ int up_fbinitialize(void)
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#if defined(BOARD_LCDC_ENABLE_DELAY) && BOARD_LCDC_ENABLE_DELAY > 0
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/* Delay a bit after enabling the LDC. I presume that a delay of a few
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* frame times allows some unstable clocking to synchronize before we
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* tart thrashing the framebuffer? But I am not sure why this is
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* start thrashing the framebuffer? But I am not sure why this is
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* necessary and, in fact, is certainly not necessary in most LCDC
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* configurations. Perhaps this delay would not be necessary if timings
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* were more precise?
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