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arch/arm/src/imxrt: Add GPIO5 IRQ support.

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This commit is contained in:
Jake Choy 2018-05-02 09:19:42 -06:00 committed by Gregory Nutt
parent 01ee9b3abc
commit 4261249fb6
6 changed files with 175 additions and 9 deletions
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54
arch/arm/include/imxrt/imxrt105x_irq.h
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@ -419,13 +419,65 @@
# define IMXRT_IRQ_GPIO4_31 (_IMXRT_GPIO4_16_31_BASE + 15) /* GPIO4 pin 31 interrupt */
# define _IMXRT_GPIO4_16_31_NIRQS 16
# define _IMXRT_GPIO5_0_15_BASE (_IMXRT_GPIO4_16_31_BASE + _IMXRT_GPIO4_16_31_NIRQS)
# define IMXRT_GPIO4_NIRQS (_IMXRT_GPIO4_0_15_NIRQS + _IMXRT_GPIO4_16_31_NIRQS)
#else
# define _IMXRT_GPIO5_0_15_BASE _IMXRT_GPIO4_16_31_BASE
# define IMXRT_GPIO4_NIRQS _IMXRT_GPIO4_0_15_NIRQS
#endif
#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
# define IMXRT_IRQ_GPIO5_16 (_IMXRT_GPIO5_0_15_BASE + 0) /* GPIO5 pin 0 interrupt */
# define IMXRT_IRQ_GPIO5_17 (_IMXRT_GPIO5_0_15_BASE + 1) /* GPIO5 pin 1 interrupt */
# define IMXRT_IRQ_GPIO5_18 (_IMXRT_GPIO5_0_15_BASE + 2) /* GPIO5 pin 2 interrupt */
# define IMXRT_IRQ_GPIO5_19 (_IMXRT_GPIO5_0_15_BASE + 3) /* GPIO5 pin 3 interrupt */
# define IMXRT_IRQ_GPIO5_20 (_IMXRT_GPIO5_0_15_BASE + 4) /* GPIO5 pin 4 interrupt */
# define IMXRT_IRQ_GPIO5_21 (_IMXRT_GPIO5_0_15_BASE + 5) /* GPIO5 pin 5 interrupt */
# define IMXRT_IRQ_GPIO5_22 (_IMXRT_GPIO5_0_15_BASE + 6) /* GPIO5 pin 6 interrupt */
# define IMXRT_IRQ_GPIO5_23 (_IMXRT_GPIO5_0_15_BASE + 7) /* GPIO5 pin 7 interrupt */
# define IMXRT_IRQ_GPIO5_24 (_IMXRT_GPIO5_0_15_BASE + 8) /* GPIO5 pin 8 interrupt */
# define IMXRT_IRQ_GPIO5_25 (_IMXRT_GPIO5_0_15_BASE + 9) /* GPIO5 pin 9 interrupt */
# define IMXRT_IRQ_GPIO5_26 (_IMXRT_GPIO5_0_15_BASE + 10) /* GPIO5 pin 10 interrupt */
# define IMXRT_IRQ_GPIO5_27 (_IMXRT_GPIO5_0_15_BASE + 11) /* GPIO5 pin 11 interrupt */
# define IMXRT_IRQ_GPIO5_28 (_IMXRT_GPIO5_0_15_BASE + 12) /* GPIO5 pin 12 interrupt */
# define IMXRT_IRQ_GPIO5_29 (_IMXRT_GPIO5_0_15_BASE + 13) /* GPIO5 pin 13 interrupt */
# define IMXRT_IRQ_GPIO5_30 (_IMXRT_GPIO5_0_15_BASE + 14) /* GPIO5 pin 14 interrupt */
# define IMXRT_IRQ_GPIO5_31 (_IMXRT_GPIO5_0_15_BASE + 15) /* GPIO5 pin 15 interrupt */
# define _IMXRT_GPIO5_0_15_NIRQS 16
# define _IMXRT_GPIO5_16_31_BASE (_IMXRT_GPIO5_0_15_BASE + _IMXRT_GPIO5_0_15_NIRQS)
#else
# define _IMXRT_GPIO5_0_15_NIRQS 0
# define _IMXRT_GPIO5_16_31_BASE _IMXRT_GPIO5_0_15_BASE
#endif
#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ
# define IMXRT_IRQ_GPIO5_16 (_IMXRT_GPIO5_16_31_BASE + 0) /* GPIO5 pin 16 interrupt */
# define IMXRT_IRQ_GPIO5_17 (_IMXRT_GPIO5_16_31_BASE + 1) /* GPIO5 pin 17 interrupt */
# define IMXRT_IRQ_GPIO5_18 (_IMXRT_GPIO5_16_31_BASE + 2) /* GPIO5 pin 18 interrupt */
# define IMXRT_IRQ_GPIO5_19 (_IMXRT_GPIO5_16_31_BASE + 3) /* GPIO5 pin 19 interrupt */
# define IMXRT_IRQ_GPIO5_20 (_IMXRT_GPIO5_16_31_BASE + 4) /* GPIO5 pin 20 interrupt */
# define IMXRT_IRQ_GPIO5_21 (_IMXRT_GPIO5_16_31_BASE + 5) /* GPIO5 pin 21 interrupt */
# define IMXRT_IRQ_GPIO5_22 (_IMXRT_GPIO5_16_31_BASE + 6) /* GPIO5 pin 22 interrupt */
# define IMXRT_IRQ_GPIO5_23 (_IMXRT_GPIO5_16_31_BASE + 7) /* GPIO5 pin 23 interrupt */
# define IMXRT_IRQ_GPIO5_24 (_IMXRT_GPIO5_16_31_BASE + 8) /* GPIO5 pin 24 interrupt */
# define IMXRT_IRQ_GPIO5_25 (_IMXRT_GPIO5_16_31_BASE + 9) /* GPIO5 pin 25 interrupt */
# define IMXRT_IRQ_GPIO5_26 (_IMXRT_GPIO5_16_31_BASE + 10) /* GPIO5 pin 26 interrupt */
# define IMXRT_IRQ_GPIO5_27 (_IMXRT_GPIO5_16_31_BASE + 11) /* GPIO5 pin 27 interrupt */
# define IMXRT_IRQ_GPIO5_28 (_IMXRT_GPIO5_16_31_BASE + 12) /* GPIO5 pin 28 interrupt */
# define IMXRT_IRQ_GPIO5_29 (_IMXRT_GPIO5_16_31_BASE + 13) /* GPIO5 pin 29 interrupt */
# define IMXRT_IRQ_GPIO5_30 (_IMXRT_GPIO5_16_31_BASE + 14) /* GPIO5 pin 30 interrupt */
# define IMXRT_IRQ_GPIO5_31 (_IMXRT_GPIO5_16_31_BASE + 15) /* GPIO5 pin 31 interrupt */
# define _IMXRT_GPIO5_16_31_NIRQS 16
# define IMXRT_GPIO5_NIRQS (_IMXRT_GPIO5_0_15_NIRQS + _IMXRT_GPIO5_16_31_NIRQS)
#else
# define IMXRT_GPIO5_NIRQS _IMXRT_GPIO5_0_15_NIRQS
#endif
#define IMXRT_GPIO_NIRQS (IMXRT_GPIO1_NIRQS + IMXRT_GPIO2_NIRQS + \
IMXRT_GPIO3_NIRQS + IMXRT_GPIO4_NIRQS)
IMXRT_GPIO3_NIRQS + IMXRT_GPIO4_NIRQS + \
IMXRT_GPIO5_NIRQS)
#define IMXRT_GPIO_IRQ_LAST (_IMXRT_GPIO1_0_15_BASE + IMXRT_GPIO_NIRQS)
/* Total number of IRQ numbers **********************************************************/

8
arch/arm/src/imxrt/Kconfig
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@ -158,6 +158,14 @@ config IMXRT_GPIO4_16_31_IRQ
bool "GPIO4 Pins 16-31 interrupts"
default n
config IMXRT_GPIO5_0_15_IRQ
bool "GPIO5 Pins 0-15 interrupts"
default n
config IMXRT_GPIO5_16_31_IRQ
bool "GPIO5 Pins 16-31 interrupts"
default n
endif # IMXRT_GPIO_IRQ
menu "Memory Configuration"

113
arch/arm/src/imxrt/imxrt_gpioirq.c
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@ -139,6 +139,23 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin)
}
else
#endif
#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
if (irq < _IMXRT_GPIO5_16_31_BASE)
{
*regaddr = IMXRT_GPIO5_IMR;
*pin = irq - _IMXRT_GPIO5_0_15_BASE;
}
else
#endif
#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
if (irq < IMXRT_GPIO_IRQ_LAST)
{
*regaddr = IMXRT_GPIO5_IMR;
*pin = irq - _IMXRT_GPIO5_16_31_BASE + 16;
}
else
#endif
{
return -EINVAL;
}
@ -450,6 +467,79 @@ static int imxrt_gpio4_16_31_interrupt(int irq, FAR void *context,
}
#endif
#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
static int imxrt_gpio5_0_15_interrupt(int irq, FAR void *context,
FAR void *arg)
{
uint32_t status;
int gpioirq;
int bit;
/* Get the pending interrupt indications */
status = getreg32(IMXRT_GPIO5_ISR) & getreg32(IMXRT_GPIO5_IMR) &
0x0000fffff;
/* Decode the pending interrupts */
for (bit = 0, gpioirq = _IMXRT_GPIO5_0_15_BASE;
bit < 16 && status != 0;
bit++, gpioirq++)
{
/* Is the IRQ associate with this pin pending? */
uint32_t mask = (1 << bit);
if ((status & mask) != 0)
{
/* Yes, clear the status bit and dispatch the interrupt */
putreg32(mask, IMXRT_GPIO5_ISR);
status &= ~mask;
irq_dispatch(gpioirq, context);
}
}
return OK;
}
#endif
#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ
static int imxrt_gpio5_16_31_interrupt(int irq, FAR void *context,
FAR void *arg)
{
uint32_t status;
int gpioirq;
int bit;
/* Get the pending interrupt indications */
status = getreg32(IMXRT_GPIO5_ISR) & getreg32(IMXRT_GPIO5_IMR) &
0xffff0000;
/* Decode the pending interrupts */
for (bit = 16, gpioirq = _IMXRT_GPIO5_16_31_BASE;
bit < 32 && status != 0;
bit++, gpioirq++)
{
/* Is the IRQ associate with this pin pending? */
uint32_t mask = (1 << bit);
if ((status & mask) != 0)
{
/* Yes, clear the status bit and dispatch the interrupt */
putreg32(mask, IMXRT_GPIO5_ISR);
status &= ~mask;
irq_dispatch(gpioirq, context);
}
}
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -470,6 +560,7 @@ void imxrt_gpioirq_initialize(void)
putreg32(0, IMXRT_GPIO2_IMR);
putreg32(0, IMXRT_GPIO3_IMR);
putreg32(0, IMXRT_GPIO4_IMR);
putreg32(0, IMXRT_GPIO5_IMR);
/* Disable all unconfigured GPIO interrupts at the NVIC */
@ -497,6 +588,12 @@ void imxrt_gpioirq_initialize(void)
#ifndef CONFIG_IMXRT_GPIO4_16_31_IRQ
up_disable_irq(IMXRT_IRQ_GPIO4_16_31);
#endif
#ifndef CONFIG_IMXRT_GPIO5_0_15_IRQ
up_disable_irq(IMXRT_IRQ_GPIO5_0_15);
#endif
#ifndef CONFIG_IMXRT_GPIO5_16_31_IRQ
up_disable_irq(IMXRT_IRQ_GPIO5_16_31);
#endif
/* Attach all configured GPIO interrupts and enable the interrupt at the
* NVIC
@ -544,11 +641,23 @@ void imxrt_gpioirq_initialize(void)
up_enable_irq(IMXRT_IRQ_GPIO4_0_15);
#endif
#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ
#ifdef CONFIG_IMXRT_GPIO4_16_31_IRQ
DEBUGVERIFY(irq_attach(IMXRT_IRQ_GPIO4_16_31,
imxrt_gpio4_16_31_interrupt, NULL));
up_enable_irq(IMXRT_IRQ_GPIO4_16_31);
#endif
#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
DEBUGVERIFY(irq_attach(IMXRT_IRQ_GPIO5_0_15,
imxrt_gpio5_0_15_interrupt, NULL));
up_enable_irq(IMXRT_IRQ_GPIO5_0_15);
#endif
#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ
DEBUGVERIFY(irq_attach(IMXRT_IRQ_GPIO5_16_31,
imxrt_gpio5_16_31_interrupt, NULL));
up_enable_irq(IMXRT_IRQ_GPIO5_16_31);
#endif
}
/************************************************************************************
@ -596,7 +705,6 @@ int imxrt_gpioirq_enable(int irq)
{
uintptr_t regaddr;
unsigned int pin;
uint32_t regval;
int ret;
ret = imxrt_gpio_info(irq, &regaddr, &pin);
@ -620,7 +728,6 @@ int imxrt_gpioirq_disable(int irq)
{
uintptr_t regaddr;
unsigned int pin;
uint32_t regval;
int ret;
ret = imxrt_gpio_info(irq, &regaddr, &pin);

2
configs/imxrt1050-evk/include/board.h
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@ -140,7 +140,7 @@
/* Button definitions ***************************************************************/
/* The IMXRT board has one external user button
*
* 1. SW8 (IRQ0) GPIO5-00
* 1. SW8 (IRQ88) GPIO5-00
*/
#define BUTTON_SW8 0

5
configs/imxrt1050-evk/src/imxrt1050-evk.h
View File

@ -78,13 +78,12 @@
*
* The IMXRT board has one external user button
*
* 1. SW8 (IRQ0) GPIO5-00
* 1. SW8 (IRQ88) GPIO5-00
*
* REVISIT: Button is set to Port1 pin24 for now.
*/
#define GPIO_SW8 (GPIO_INTERRUPT | GPIO_INT_FALLINGEDGE | \
GPIO_PORT1 | GPIO_PIN24)
GPIO_PORT5 | GPIO_PIN0)
/************************************************************************************
* Public Types

2
configs/imxrt1050-evk/src/imxrt_buttons.c
View File

@ -61,7 +61,7 @@
/* The IMXRT has 1 user button (SW8)):
*
* 1. SW8 (IRQ0) GPIO5-00
* 1. SW8 (IRQ88) GPIO5-00
*/
/****************************************************************************