arch/arm/src/imxrt/imxrt_lpspi.c: Fixed race on register setting. The ouput frequency was not being initialized correctly. The value of LPSPI_TCR_PRESCALE was getting set to 7. Making the setting atomic fixed the race. I suppose a DSB() could have also fixed it.
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@ -901,7 +901,6 @@ static uint32_t imxrt_lpspi_setfrequency(FAR struct spi_dev_s *dev,
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FAR struct imxrt_lpspidev_s *priv = (FAR struct imxrt_lpspidev_s *)dev;
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uint32_t men;
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uint32_t regval;
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uint32_t pll_freq;
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uint32_t pll3_div;
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uint32_t src_freq = 0;
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@ -986,14 +985,12 @@ static uint32_t imxrt_lpspi_setfrequency(FAR struct spi_dev_s *dev,
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/* Write the best values in the CCR register */
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regval = imxrt_lpspi_getreg32(priv, IMXRT_LPSPI_CCR_OFFSET);
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regval &= ~LPSPI_CCR_SCKDIV_MASK;
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regval |= LPSPI_CCR_SCKDIV(best_scaler);
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imxrt_lpspi_putreg32(priv, IMXRT_LPSPI_CCR_OFFSET, regval);
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imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET,
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LPSPI_CCR_SCKDIV_MASK,
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LPSPI_CCR_SCKDIV(best_scaler));
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imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET,
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LPSPI_TCR_PRESCALE_MASK, 0);
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imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET, 0,
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LPSPI_TCR_PRESCALE_MASK,
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LPSPI_TCR_PRESCALE(best_prescaler));
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priv->frequency = frequency;
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@ -1120,7 +1117,6 @@ static void imxrt_lpspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
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static void imxrt_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits)
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{
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FAR struct imxrt_lpspidev_s *priv = (FAR struct imxrt_lpspidev_s *)dev;
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uint32_t regval;
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uint32_t men;
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int savbits = nbits;
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@ -1144,11 +1140,9 @@ static void imxrt_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits)
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imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CR_OFFSET, LPSPI_CR_MEN, 0);
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}
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regval = imxrt_lpspi_getreg32(priv, IMXRT_LPSPI_TCR_OFFSET);
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regval &= ~LPSPI_TCR_FRAMESZ_MASK;
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regval |= LPSPI_TCR_FRAMESZ(nbits - 1);
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imxrt_lpspi_putreg32(priv, IMXRT_LPSPI_TCR_OFFSET, regval);
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imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET,
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LPSPI_TCR_FRAMESZ_MASK,
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LPSPI_TCR_FRAMESZ(nbits - 1));
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/* Save the selection so the subsequence re-configurations will be faster */
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