Add control reg defs

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@541 42af7a65-404d-4744-a932-0658087f49c3

arch/z16/src/z16f/chip.h

@@ -45,7 +45,7 @@
  * Definitions
  ************************************************************************************/
  
-/* Z16F Chip Variants */
+/* Z16F Chip Variants ***************************************************************/
  
 #if defined(CONFIG_ARCH_CHIP_Z16F2810)
 # define Z16F_INVMEM_SIZE (128*1024)
@@ -67,7 +67,7 @@
 # error "Z16F chip variant not specified"
 #endif
 
-/* Memory areas
+/* Memory areas**********************************************************************
  *
  * Internal non-volatile memory starts at address zero.  The size
  * of the internal non-volatile memory is chip-dependent.
@@ -101,6 +101,33 @@
 #define Z16F_IIO_BASE           0xffe000 /* Internal I/O memory and SFRs */
 #define Z16F_IIO_SIZE           0x001fff
 
+/* Control Registers  ***************************************************************/
+
+#define Z16F_CNTRL_PCOV         0xffe04  /* 32-bits: Program counter overflow */
+#define Z16F_CNTRL_SPOV         0xffe0c  /* 32-bits: Stack pointer overflow */
+#define Z16F_CNTRL_FLAGS        0xffe10  /*  8-bits: flags */
+#define Z16F_CNTRL_CPUCTL       0xffe12  /*  8-bits: CPU control */
+
+/* Flag register bits **************************\*************************************/
+
+#define Z16F_CNTRL_FLAGS_C      0x80     /* Bit 7: Carry flag */
+#define Z16F_CNTRL_FLAGS_Z      0x40     /* Bit 6: Zero flag */
+#define Z16F_CNTRL_FLAGS_S      0x20     /* Bit 5: Sign flag */
+#define Z16F_CNTRL_FLAGS_V      0x10     /* Bit 4: Overflow flag */
+#define Z16F_CNTRL_FLAGS_B      0x08     /* Bit 3: Blank flag */
+#define Z16F_CNTRL_FLAGS_F1     0x04     /* Bit 2: User flag 1 */
+#define Z16F_CNTRL_FLAGS_CIRQE  0x02     /* Bit 1: Chained interrupt enable */
+#define Z16F_CNTRL_FLAGS_IRQE   0x01     /* Bit 0: Master interrupt enable */
+
+/* CPU control register bits ********************************************************/
+
+                                         /* Bits 7-2: Reserved, must be zero */
+                                         /* Bits 1-0: DMA bandwidth control */
+#define Z16F_CNTRL_CPUCTL_BWALL 0x00     /*   DMA can consume 100% bandwidth */
+#define Z16F_CNTRL_CPUCTL_BW11  0x01     /*   DMA can do 1 transaction per 1 cycle */
+#define Z16F_CNTRL_CPUCTL_BW12  0x01     /*   DMA can do 1 transaction per 2 cycles */
+#define Z16F_CNTRL_CPUCTL_BW13  0x01     /*   DMA can do 1 transaction per 3 cycles */
+ 
 /************************************************************************************
  * Public Function Prototypes
  ************************************************************************************/