sergiotarxz/nuttx
sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

STM32F33: Fix hrtim definitions, Add beginning of HRTIM driver

Browse Source
This commit is contained in:
Mateusz Szafoni 2017-06-11 10:49:20 -06:00 committed by Gregory Nutt
parent 40f60d6da5
commit 437ad3ccb2
4 changed files with 164 additions and 305 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/src/stm32/Make.defs
View File

@ -225,6 +225,10 @@ ifeq ($(CONFIG_OPAMP),y)
CHIP_CSRCS += stm32_opamp.c
endif
ifeq ($(CONFIG_HRTIM),y)
CHIP_CSRCS += stm32_hrtim.c
endif
ifeq ($(CONFIG_STM32_1WIREDRIVER),y)
CHIP_CSRCS += stm32_1wire.c
endif

462
arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
View File

@ -67,310 +67,190 @@
/* Register Offsets *********************************************************************************/
/* Register Offsets for HRTIM Master Timer */
/* Register Offsets Common for Master Timer and Timer X */
#define STM32_HRTIM_MASTER_MCR 0x0000 /* HRTIM Master Timer Control Register */
#define STM32_HRTIM_MASTER_MISR 0x0004 /* HRTIM Master Timer Interrupt Status Register */
#define STM32_HRTIM_MASTER_MICR 0x0008 /* HRTIM Master Timer Interrupt Clear Register */
#define STM32_HRTIM_MASTER_MDIER 0x000C /* HRTIM Master Timer DMA/Interrupt Enable Register */
#define STM32_HRTIM_MASTER_MCNTR 0x0010 /* HRTIM Master Timer Counter Register */
#define STM32_HRTIM_MASTER_MPER 0x0014 /* HRTIM Master Timer Period Register */
#define STM32_HRTIM_MASTER_MREP 0x0018 /* HRTIM Master Timer Repetition Register */
#define STM32_HRTIM_MASTER_MCMP1R 0x001C /* HRTIM Master Timer Compare 1 Register */
#define STM32_HRTIM_MASTER_MCMP2R 0x0024 /* HRTIM Master Timer Compare 2 Register */
#define STM32_HRTIM_MASTER_MCMP3R 0x0028 /* HRTIM Master Timer Compare 3 Register */
#define STM32_HRTIM_MASTER_MCMP4R 0x002C /* HRTIM Master Timer Compare 4 Register */
#define STM32_HRTIM_TIM_CR_OFFSET 0x0000 /* HRTIM Timer Control Register */
#define STM32_HRTIM_TIM_ISR_OFFSET 0x0004 /* HRTIM Timer Interrupt Status Register */
#define STM32_HRTIM_TIM_ICR_OFFSET 0x0008 /* HRTIM Timer Interrupt Clear Register */
#define STM32_HRTIM_TIM_DIER_OFFSET 0x000C /* HRTIM Timer DMA/Interrupt Enable Register */
#define STM32_HRTIM_TIM_CNTR_OFFSET 0x0010 /* HRTIM Timer Counter Register */
#define STM32_HRTIM_TIM_PER_OFFSET 0x0014 /* HRTIM Timer Period Register */
#define STM32_HRTIM_TIM_REPR_OFFSET 0x0018 /* HRTIM Timer Repetition Register */
#define STM32_HRTIM_TIM_CMP1R_OFFSET 0x001C /* HRTIM Timer Compare 1 Register */
#define STM32_HRTIM_TIM_CMP2R_OFFSET 0x0024 /* HRTIM Timer Compare 2 Register */
#define STM32_HRTIM_TIM_CMP3R_OFFSET 0x0028 /* HRTIM Timer Compare 3 Register */
#define STM32_HRTIM_TIM_CMP4R_OFFSET 0x002C /* HRTIM Timer Compare 4 Register */
/* Register Offsets for HRTIM Timers A-E */
/* Register offsets Specific for Timer A-E */
#define STM32_HRTIM_TIMX_CR 0x0000 /* HRTIM Timer X Control Register */
#define STM32_HRTIM_TIMX_ISR 0x0004 /* HRTIM Timer X Interrupt Status Register */
#define STM32_HRTIM_TIMX_ICR 0x0008 /* HRTIM Timer X Interrupt Clear Register */
#define STM32_HRTIM_TIMX_DIER 0x000C /* HRTIM Timer X DMA/Interrupt Enable Register */
#define STM32_HRTIM_TIMX_CNTR 0x0010 /* HRTIM Timer X Counter Register */
#define STM32_HRTIM_TIMX_PER 0x0014 /* HRTIM Timer X Period Register */
#define STM32_HRTIM_TIMX_REP 0x0018 /* HRTIM Timer X Repetition Register */
#define STM32_HRTIM_TIMX_CMP1R 0x001C /* HRTIM Timer X Compare 1 Register */
#define STM32_HRTIM_TIMX_CMP1CR 0x0020 /* HRTIM Timer X Compare 1 Compound Register */
#define STM32_HRTIM_TIMX_CMP2R 0x0024 /* HRTIM Timer X Compare 2 Register */
#define STM32_HRTIM_TIMX_CMP3R 0x0028 /* HRTIM Timer X Compare 3 Register */
#define STM32_HRTIM_TIMX_CMP4R 0x002C /* HRTIM Timer X Compare 4 Register */
#define STM32_HRTIM_TIMX_CPT1R 0x0030 /* HRTIM Timer X Capture 1 Register */
#define STM32_HRTIM_TIMX_CPT2R 0x0034 /* HRTIM Timer X Capture 2 Register */
#define STM32_HRTIM_TIMX_DTR 0x0038 /* HRTIM Timer X Deadtime Register */
#define STM32_HRTIM_TIMX_SET1R 0x003C /* HRTIM Timer X Output1 Set Register */
#define STM32_HRTIM_TIMX_RST1R 0x0040 /* HRTIM Timer X Output1 Reset Register */
#define STM32_HRTIM_TIMX_SET2R 0x0044 /* HRTIM Timer X Output2 Set Register */
#define STM32_HRTIM_TIMX_RST2R 0x0048 /* HRTIM Timer X Output2 Reset Register */
#define STM32_HRTIM_TIMX_EEFR1 0x004C /* HRTIM Timer X External Event Filtering Register 1 */
#define STM32_HRTIM_TIMX_EEFR2 0x0050 /* HRTIM Timer X External Event Filtering Register 2 */
#define STM32_HRTIM_TIMX_RSTR 0x0054 /* HRTIM Timer X Reset Register */
#define STM32_HRTIM_TIMX_CHPR 0x0058 /* HRTIM Timer X Chopper Register */
#define STM32_HRTIM_TIMX_CPT1CR 0x005C /* HRTIM Timer X Capture 1 Control Register */
#define STM32_HRTIM_TIMX_CPT2CR 0x0060 /* HRTIM Timer X Capture 2 Control Register */
#define STM32_HRTIM_TIMX_OUTR 0x0064 /* HRTIM Timer X Output Register */
#define STM32_HRTIM_TIMX_FLTR 0x0068 /* HRTIM Timer X Fault Register */
#define STM32_HRTIM_TIM_CMP1CR_OFFSET 0x0020 /* HRTIM Timer Compare 1 Compound Register */
#define STM32_HRTIM_TIM_CPT1R_OFFSET 0x0030 /* HRTIM Timer Capture 1 Register */
#define STM32_HRTIM_TIM_CPT2R_OFFSET 0x0034 /* HRTIM Timer Capture 2 Register */
#define STM32_HRTIM_TIM_DTR_OFFSET 0x0038 /* HRTIM Timer Deadtime Register */
#define STM32_HRTIM_TIM_SET1R_OFFSET 0x003C /* HRTIM Timer Output1 Set Register */
#define STM32_HRTIM_TIM_RST1R_OFFSET 0x0040 /* HRTIM Timer Output1 Reset Register */
#define STM32_HRTIM_TIM_SET2R_OFFSET 0x0044 /* HRTIM Timer Output2 Set Register */
#define STM32_HRTIM_TIM_RST2R_OFFSET 0x0048 /* HRTIM Timer Output2 Reset Register */
#define STM32_HRTIM_TIM_EEFR1_OFFSET 0x004C /* HRTIM Timer External Event Filtering Register 1 */
#define STM32_HRTIM_TIM_EEFR2_OFFSET 0x0050 /* HRTIM Timer External Event Filtering Register 2 */
#define STM32_HRTIM_TIM_RSTR_OFFSET 0x0054 /* HRTIM Timer Reset Register */
#define STM32_HRTIM_TIM_CHPR_OFFSET 0x0058 /* HRTIM Timer Chopper Register */
#define STM32_HRTIM_TIM_CPT1CR_OFFSET 0x005C /* HRTIM Timer Capture 1 Control Register */
#define STM32_HRTIM_TIM_CPT2CR_OFFSET 0x0060 /* HRTIM Timer Capture 2 Control Register */
#define STM32_HRTIM_TIM_OUTR_OFFSET 0x0064 /* HRTIM Timer Output Register */
#define STM32_HRTIM_TIM_FLTR_OFFSET 0x0068 /* HRTIM Timer Fault Register */
/* Register Offset for HRTIM Common */
#define STM32_HRTIM_CMN_CR1 0x0000 /* HRTIM Control Register 1 */
#define STM32_HRTIM_CMN_CR2 0x0004 /* HRTIM Control Register 2 */
#define STM32_HRTIM_CMN_ISR 0x0008 /* HRTIM Interrupt Status Register */
#define STM32_HRTIM_CMN_ICR 0x000C /* HRTIM Interrupt Clear Register */
#define STM32_HRTIM_CMN_IER 0x0010 /* HRTIM Interrupt Enable Register */
#define STM32_HRTIM_CMN_OENR 0x0014 /* HRTIM Output Enable Register */
#define STM32_HRTIM_CMN_DISR 0x0018 /* HRTIM Output Disable Register */
#define STM32_HRTIM_CMN_ODSR 0x001C /* HRTIM Output Disable Status Register */
#define STM32_HRTIM_CMN_BMCR 0x0020 /* HRTIM Burst Mode Control Register */
#define STM32_HRTIM_CMN_BMTRGR 0x0024 /* HRTIM Burst Mode Trigger Register */
#define STM32_HRTIM_CMN_BMCMPR 0x0028 /* HRTIM Burst Mode Compare Register */
#define STM32_HRTIM_CMN_BMPER 0x002C /* HRTIM Burst Mode Period Register */
#define STM32_HRTIM_CMN_EECR1 0x0030 /* HRTIM Timer External Event Control Register 1 */
#define STM32_HRTIM_CMN_EECR2 0x0034 /* HRTIM Timer External Event Control Register 2 */
#define STM32_HRTIM_CMN_EECR3 0x0038 /* HRTIM Timer External Event Control Register 3 */
#define STM32_HRTIM_CMN_ADC1R 0x003C /* HRTIM ADC Trigger 1 Register */
#define STM32_HRTIM_CMN_ADC2R 0x0040 /* HRTIM ADC Trigger 2 Register */
#define STM32_HRTIM_CMN_ADC3R 0x0044 /* HRTIM ADC Trigger 3 Register */
#define STM32_HRTIM_CMN_ADC4R 0x0048 /* HRTIM ADC Trigger 4 Register */
#define STM32_HRTIM_CMN_DLLCR 0x004C /* HRTIM DLL Control Register */
#define STM32_HRTIM_CMN_FLTINR1 0x0050 /* HRTIM Fault Input Register 1 */
#define STM32_HRTIM_CMN_FLTINR2 0x0054 /* HRTIM Fault Input Register 2 */
#define STM32_HRTIM_CMN_BDMUPDR 0x0058 /* HRTIM Master Timer Update Register */
#define STM32_HRTIM_CMN_BDTAUPR 0x005C /* HRTIM Timer A Update Register */
#define STM32_HRTIM_CMN_BDTBUPR 0x0060 /* HRTIM Timer B Update Register */
#define STM32_HRTIM_CMN_BDTCUPR 0x0064 /* HRTIM Timer C Update Register */
#define STM32_HRTIM_CMN_BDTDUPR 0x0068 /* HRTIM Timer D Update Register */
#define STM32_HRTIM_CMN_BDTEUPR 0x006C /* HRTIM Timer E Update Register */
#define STM32_HRTIM_CMN_BDMADR 0x0070 /* HRTIM DMA Data Register */
#define STM32_HRTIM_CMN_CR1_OFFSET 0x0000 /* HRTIM Control Register 1 */
#define STM32_HRTIM_CMN_CR2_OFFSET 0x0004 /* HRTIM Control Register 2 */
#define STM32_HRTIM_CMN_ISR_OFFSET 0x0008 /* HRTIM Interrupt Status Register */
#define STM32_HRTIM_CMN_ICR_OFFSET 0x000C /* HRTIM Interrupt Clear Register */
#define STM32_HRTIM_CMN_IER_OFFSET 0x0010 /* HRTIM Interrupt Enable Register */
#define STM32_HRTIM_CMN_OENR_OFFSET 0x0014 /* HRTIM Output Enable Register */
#define STM32_HRTIM_CMN_DISR_OFFSET 0x0018 /* HRTIM Output Disable Register */
#define STM32_HRTIM_CMN_ODSR_OFFSET 0x001C /* HRTIM Output Disable Status Register */
#define STM32_HRTIM_CMN_BMCR_OFFSET 0x0020 /* HRTIM Burst Mode Control Register */
#define STM32_HRTIM_CMN_BMTRGR_OFFSET 0x0024 /* HRTIM Burst Mode Trigger Register */
#define STM32_HRTIM_CMN_BMCMPR_OFFSET 0x0028 /* HRTIM Burst Mode Compare Register */
#define STM32_HRTIM_CMN_BMPER_OFFSET 0x002C /* HRTIM Burst Mode Period Register */
#define STM32_HRTIM_CMN_EECR1_OFFSET 0x0030 /* HRTIM Timer External Event Control Register 1 */
#define STM32_HRTIM_CMN_EECR2_OFFSET 0x0034 /* HRTIM Timer External Event Control Register 2 */
#define STM32_HRTIM_CMN_EECR3_OFFSET 0x0038 /* HRTIM Timer External Event Control Register 3 */
#define STM32_HRTIM_CMN_ADC1R_OFFSET 0x003C /* HRTIM ADC Trigger 1 Register */
#define STM32_HRTIM_CMN_ADC2R_OFFSET 0x0040 /* HRTIM ADC Trigger 2 Register */
#define STM32_HRTIM_CMN_ADC3R_OFFSET 0x0044 /* HRTIM ADC Trigger 3 Register */
#define STM32_HRTIM_CMN_ADC4R_OFFSET 0x0048 /* HRTIM ADC Trigger 4 Register */
#define STM32_HRTIM_CMN_DLLCR_OFFSET 0x004C /* HRTIM DLL Control Register */
#define STM32_HRTIM_CMN_FLTINR1_OFFSET 0x0050 /* HRTIM Fault Input Register 1 */
#define STM32_HRTIM_CMN_FLTINR2_OFFSET 0x0054 /* HRTIM Fault Input Register 2 */
#define STM32_HRTIM_CMN_BDMUPDR_OFFSET 0x0058 /* HRTIM Master Timer Update Register */
#define STM32_HRTIM_CMN_BDTAUPR_OFFSET 0x005C /* HRTIM Timer A Update Register */
#define STM32_HRTIM_CMN_BDTBUPR_OFFSET 0x0060 /* HRTIM Timer B Update Register */
#define STM32_HRTIM_CMN_BDTCUPR_OFFSET 0x0064 /* HRTIM Timer C Update Register */
#define STM32_HRTIM_CMN_BDTDUPR_OFFSET 0x0068 /* HRTIM Timer D Update Register */
#define STM32_HRTIM_CMN_BDTEUPR_OFFSET 0x006C /* HRTIM Timer E Update Register */
#define STM32_HRTIM_CMN_BDMADR_OFFSET 0x0070 /* HRTIM DMA Data Register */
/* Register Addresses *******************************************************************************/
/* HRTIM1 Master Timer */
#define STM32_HRTIM1_MASTER_MCR (STM32_HRTIM_MASTER_MCR+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MISR (STM32_HRTIM_MASTER_MISR+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MICR (STM32_HRTIM_MASTER_MICR+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MDIER (STM32_HRTIM_MASTER_MDIER+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MCNTR (STM32_HRTIM_MASTER_MCNTR+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MPER (STM32_HRTIM_MASTER_MPER+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MREP (STM32_HRTIM_MASTER_MREP+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MCMP1R (STM32_HRTIM_MASTER_MCMP1R+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MCMP2R (STM32_HRTIM_MASTER_MCMP2R+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MCMP3R (STM32_HRTIM_MASTER_MCMP3R+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MCMP4R (STM32_HRTIM_MASTER_MCMP4R+STM32_HRTIM1_MASTER_BASE)
/* HRTIM1 Timer A */
/* remove ? */
#define STM32_HRTIM1_TIMERA_CR (STM32_HRTIM_TIMERA_CR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_ISR (STM32_HRTIM_TIMERA_ISR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_ICR (STM32_HRTIM_TIMERA_ICR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_DIER (STM32_HRTIM_TIMERA_DIER+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CNTR (STM32_HRTIM_TIMERA_CNTR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_PER (STM32_HRTIM_TIMERA_PER+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_REP (STM32_HRTIM_TIMERA_REP+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP1R (STM32_HRTIM_TIMERA_CMP1R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP1CR (STM32_HRTIM_TIMERA_CMP1CR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP2R (STM32_HRTIM_TIMERA_CMP2R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP3R (STM32_HRTIM_TIMERA_CMP3R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP4R (STM32_HRTIM_TIMERA_CMP4R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT1R (STM32_HRTIM_TIMERA_CMPT1R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT2R (STM32_HRTIM_TIMERA_CMPT2R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_DTR (STM32_HRTIM_TIMERA_DTR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_SET1R (STM32_HRTIM_TIMERA_SET1R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RST1R (STM32_HRTIM_TIMERA_RST1R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_SET2R (STM32_HRTIM_TIMERA_SET2R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RST2R (STM32_HRTIM_TIMERA_RST2R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_EEFR1 (STM32_HRTIM_TIMERA_EEFR1+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_EEFR2 (STM32_HRTIM_TIMERA_EEFR2+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RSTR (STM32_HRTIM_TIMERA_RSTR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CHPR (STM32_HRTIM_TIMERA_CHPR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT1CR (STM32_HRTIM_TIMERA_CPT1CR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT2CR (STM32_HRTIM_TIMERA_CPT2CR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_OUTR (STM32_HRTIM_TIMERA_OUTR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_FLTR (STM32_HRTIM_TIMERA_FLTR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CR (STM32_HRTIM_TIM_CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_ISR (STM32_HRTIM_TIM_ISR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_ICR (STM32_HRTIM_TIM_ICR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_DIER (STM32_HRTIM_TIM_DIER_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CNTR (STM32_HRTIM_TIM_CNTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_PER (STM32_HRTIM_TIM_PER_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_REP (STM32_HRTIM_TIM_REP_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP1R (STM32_HRTIM_TIM_CMP1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP1CR (STM32_HRTIM_TIM_CMP1CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP2R (STM32_HRTIM_TIM_CMP2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP3R (STM32_HRTIM_TIM_CMP3R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP4R (STM32_HRTIM_TIM_CMP4R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT1R (STM32_HRTIM_TIM_CMPT1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT2R (STM32_HRTIM_TIM_CMPT2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_DTR (STM32_HRTIM_TIM_DTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_SET1R (STM32_HRTIM_TIM_SET1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RST1R (STM32_HRTIM_TIM_RST1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_SET2R (STM32_HRTIM_TIM_SET2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RST2R (STM32_HRTIM_TIM_RST2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_EEFR1 (STM32_HRTIM_TIM_EEFR1_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_EEFR2 (STM32_HRTIM_TIM_EEFR2_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RSTR (STM32_HRTIM_TIM_RSTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CHPR (STM32_HRTIM_TIM_CHPR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT1CR (STM32_HRTIM_TIM_CPT1CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT2CR (STM32_HRTIM_TIM_CPT2CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_OUTR (STM32_HRTIM_TIM_OUTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_FLTR (STM32_HRTIM_TIM_FLTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
/* HRTIM1 Timer B */
#define STM32_HRTIM1_TIMERB_CR (STM32_HRTIM_TIMERB_CR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_ISR (STM32_HRTIM_TIMERB_ISR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_ICR (STM32_HRTIM_TIMERB_ICR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_DIER (STM32_HRTIM_TIMERB_DIER+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CNTR (STM32_HRTIM_TIMERB_CNTR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_PER (STM32_HRTIM_TIMERB_PER+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_REP (STM32_HRTIM_TIMERB_REP+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CMP1R (STM32_HRTIM_TIMERB_CMP1R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CMP1CR (STM32_HRTIM_TIMERB_CMP1CR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CMP2R (STM32_HRTIM_TIMERB_CMP2R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CMP3R (STM32_HRTIM_TIMERB_CMP3R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CMP4R (STM32_HRTIM_TIMERB_CMP4R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CPT1R (STM32_HRTIM_TIMERB_CMPT1R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CPT2R (STM32_HRTIM_TIMERB_CMPT2R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_DTR (STM32_HRTIM_TIMERB_DTR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_SET1R (STM32_HRTIM_TIMERB_SET1R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_RST1R (STM32_HRTIM_TIMERB_RST1R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_SET2R (STM32_HRTIM_TIMERB_SET2R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_RST2R (STM32_HRTIM_TIMERB_RST2R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_EEFR1 (STM32_HRTIM_TIMERB_EEFR1+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_EEFR2 (STM32_HRTIM_TIMERB_EEFR2+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_RSTR (STM32_HRTIM_TIMERB_RSTR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CHPR (STM32_HRTIM_TIMERB_CHPR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CPT1CR (STM32_HRTIM_TIMERB_CPT1CR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CPT2CR (STM32_HRTIM_TIMERB_CPT2CR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_OUTR (STM32_HRTIM_TIMERB_OUTR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_FLTR (STM32_HRTIM_TIMERB_FLTR+STM32_HRTIM1_TIMERB_BASE)
/* HRTIM1 Timer C */
#define STM32_HRTIM1_TIMERC_CR (STM32_HRTIM_TIMERC_CR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_ISR (STM32_HRTIM_TIMERC_ISR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_ICR (STM32_HRTIM_TIMERC_ICR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_DIER (STM32_HRTIM_TIMERC_DIER+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CNTR (STM32_HRTIM_TIMERC_CNTR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_PER (STM32_HRTIM_TIMERC_PER+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_REP (STM32_HRTIM_TIMERC_REP+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CMP1R (STM32_HRTIM_TIMERC_CMP1R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CMP1CR (STM32_HRTIM_TIMERC_CMP1CR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CMP2R (STM32_HRTIM_TIMERC_CMP2R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CMP3R (STM32_HRTIM_TIMERC_CMP3R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CMP4R (STM32_HRTIM_TIMERC_CMP4R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CPT1R (STM32_HRTIM_TIMERC_CMPT1R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CPT2R (STM32_HRTIM_TIMERC_CMPT2R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_DTR (STM32_HRTIM_TIMERC_DTR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_SET1R (STM32_HRTIM_TIMERC_SET1R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_RST1R (STM32_HRTIM_TIMERC_RST1R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_SET2R (STM32_HRTIM_TIMERC_SET2R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_RST2R (STM32_HRTIM_TIMERC_RST2R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_EEFR1 (STM32_HRTIM_TIMERC_EEFR1+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_EEFR2 (STM32_HRTIM_TIMERC_EEFR2+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_RSTR (STM32_HRTIM_TIMERC_RSTR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CHPR (STM32_HRTIM_TIMERC_CHPR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CPT1CR (STM32_HRTIM_TIMERC_CPT1CR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CPT2CR (STM32_HRTIM_TIMERC_CPT2CR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_OUTR (STM32_HRTIM_TIMERC_OUTR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_FLTR (STM32_HRTIM_TIMERC_FLTR+STM32_HRTIM1_TIMERC_BASE)
/* HRTIM1 Timer D */
#define STM32_HRTIM1_TIMERD_CR (STM32_HRTIM_TIMERD_CR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_ISR (STM32_HRTIM_TIMERD_ISR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_ICR (STM32_HRTIM_TIMERD_ICR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_DIER (STM32_HRTIM_TIMERD_DIER+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CNTR (STM32_HRTIM_TIMERD_CNTR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_PER (STM32_HRTIM_TIMERD_PER+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_REP (STM32_HRTIM_TIMERD_REP+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CMP1R (STM32_HRTIM_TIMERD_CMP1R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CMP1CR (STM32_HRTIM_TIMERD_CMP1CR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CMP2R (STM32_HRTIM_TIMERD_CMP2R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CMP3R (STM32_HRTIM_TIMERD_CMP3R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CMP4R (STM32_HRTIM_TIMERD_CMP4R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CPT1R (STM32_HRTIM_TIMERD_CMPT1R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CPT2R (STM32_HRTIM_TIMERD_CMPT2R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_DTR (STM32_HRTIM_TIMERD_DTR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_SET1R (STM32_HRTIM_TIMERD_SET1R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_RST1R (STM32_HRTIM_TIMERD_RST1R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_SET2R (STM32_HRTIM_TIMERD_SET2R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_RST2R (STM32_HRTIM_TIMERD_RST2R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_EEFR1 (STM32_HRTIM_TIMERD_EEFR1+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_EEFR2 (STM32_HRTIM_TIMERD_EEFR2+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_RSTR (STM32_HRTIM_TIMERD_RSTR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CHPR (STM32_HRTIM_TIMERD_CHPR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CPT1CR (STM32_HRTIM_TIMERD_CPT1CR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CPT2CR (STM32_HRTIM_TIMERD_CPT2CR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_OUTR (STM32_HRTIM_TIMERD_OUTR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_FLTR (STM32_HRTIM_TIMERD_FLTR+STM32_HRTIM1_TIMERD_BASE)
/* HRTIM1 Timer E */
#define STM32_HRTIM1_TIMERE_CR (STM32_HRTIM_TIMERE_CR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_ISR (STM32_HRTIM_TIMERE_ISR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_ICR (STM32_HRTIM_TIMERE_ICR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_DIER (STM32_HRTIM_TIMERE_DIER+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CNTR (STM32_HRTIM_TIMERE_CNTR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_PER (STM32_HRTIM_TIMERE_PER+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_REP (STM32_HRTIM_TIMERE_REP+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CMP1R (STM32_HRTIM_TIMERE_CMP1R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CMP1CR (STM32_HRTIM_TIMERE_CMP1CR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CMP2R (STM32_HRTIM_TIMERE_CMP2R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CMP3R (STM32_HRTIM_TIMERE_CMP3R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CMP4R (STM32_HRTIM_TIMERE_CMP4R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CPT1R (STM32_HRTIM_TIMERE_CMPT1R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CPT2R (STM32_HRTIM_TIMERE_CMPT2R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_DTR (STM32_HRTIM_TIMERE_DTR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_SET1R (STM32_HRTIM_TIMERE_SET1R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_RST1R (STM32_HRTIM_TIMERE_RST1R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_SET2R (STM32_HRTIM_TIMERE_SET2R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_RST2R (STM32_HRTIM_TIMERE_RST2R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_EEFR1 (STM32_HRTIM_TIMERE_EEFR1+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_EEFR2 (STM32_HRTIM_TIMERE_EEFR2+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_RSTR (STM32_HRTIM_TIMERE_RSTR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CHPR (STM32_HRTIM_TIMERE_CHPR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CPT1CR (STM32_HRTIM_TIMERE_CPT1CR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CPT2CR (STM32_HRTIM_TIMERE_CPT2CR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_OUTR (STM32_HRTIM_TIMERE_OUTR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_FLTR (STM32_HRTIM_TIMERE_FLTR+STM32_HRTIM1_TIMERE_BASE)
/* HRTIM1 Common Registers */
#define STM32_HRTIM_CMN_CR1 (STM32_HRTIM_CMN_CR1+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_CR2 (STM32_HRTIM_CMN_CR2+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ISR (STM32_HRTIM_CMN_ISR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ICR (STM32_HRTIM_CMN_ICR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_IER (STM32_HRTIM_CMN_IER+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_OENR (STM32_HRTIM_CMN_OENR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_DISR (STM32_HRTIM_CMN_DISR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ODSR (STM32_HRTIM_CMN_ODSR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMCR (STM32_HRTIM_CMN_BMCR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMTGR (STM32_HRTIM_CMN_BMTGR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMCMPR (STM32_HRTIM_CMN_MBCMPR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMPER (STM32_HRTIM_CMN_BMPER+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR1 (STM32_HRTIM_CMN_EECR1+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR2 (STM32_HRTIM_CMN_EECR2+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR3 (STM32_HRTIM_CMN_EECR3+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC1R (STM32_HRTIM_CMN_ADC1R+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC2R (STM32_HRTIM_CMN_ADC2R+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC3R (STM32_HRTIM_CMN_ADC3R+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC4R (STM32_HRTIM_CMN_ADC4R+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_DLLCR (STM32_HRTIM_CMN_DLLCR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_FLTINR1 (STM32_HRTIM_CMN_FTLINR1+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_FLTINR2 (STM32_HRTIM_CMN_FLTINR2+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDMUPDR (STM32_HRTIM_CMN_BDMUPDR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTAUPR (STM32_HRTIM_CMN_BDTAUPR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTBUPR (STM32_HRTIM_CMN_BDTBUR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTCUPR (STM32_HRTIM_CMN_BDTCUPR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTDUPR (STM32_HRTIM_CMN_BDTDUPR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTEUPR (STM32_HRTIM_CMN_BDTEUPR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDMADR (STM32_HRTIM_CMN_BDMADR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_CR1 (STM32_HRTIM_CMN_CR1_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_CR2 (STM32_HRTIM_CMN_CR2_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ISR (STM32_HRTIM_CMN_ISR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ICR (STM32_HRTIM_CMN_ICR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_IER (STM32_HRTIM_CMN_IER_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_OENR (STM32_HRTIM_CMN_OENR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_DISR (STM32_HRTIM_CMN_DISR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ODSR (STM32_HRTIM_CMN_ODSR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMCR (STM32_HRTIM_CMN_BMCR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMTGR (STM32_HRTIM_CMN_BMTGR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMCMPR (STM32_HRTIM_CMN_MBCMPR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMPER (STM32_HRTIM_CMN_BMPER_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR1 (STM32_HRTIM_CMN_EECR1_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR2 (STM32_HRTIM_CMN_EECR2_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR3 (STM32_HRTIM_CMN_EECR3_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC1R (STM32_HRTIM_CMN_ADC1R_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC2R (STM32_HRTIM_CMN_ADC2R_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC3R (STM32_HRTIM_CMN_ADC3R_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC4R (STM32_HRTIM_CMN_ADC4R_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_DLLCR (STM32_HRTIM_CMN_DLLCR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_FLTINR1 (STM32_HRTIM_CMN_FTLINR1_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_FLTINR2 (STM32_HRTIM_CMN_FLTINR2_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDMUPDR (STM32_HRTIM_CMN_BDMUPDR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTAUPR (STM32_HRTIM_CMN_BDTAUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTBUPR (STM32_HRTIM_CMN_BDTBUR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTCUPR (STM32_HRTIM_CMN_BDTCUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTDUPR (STM32_HRTIM_CMN_BDTDUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTEUPR (STM32_HRTIM_CMN_BDTEUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDMADR (STM32_HRTIM_CMN_BDMADR_OFFSET+STM32_HRTIM1_CMN_BASE)
/* Register Bitfield Definitions ****************************************************/
/* Master Timer Control Register */
/* Control Register Bits Common to Master Timer and Timer A-E */
#define HRTIM_MCR_CKPSC_SHIFT 0 /* Bits 0-2: Clock prescaler */
#define HRTIM_MCR_CKPSC_MASK (7 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_NODIV (0 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d2 (1 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d4 (2 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d8 (3 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d16 (4 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d32 (5 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d64 (6 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d128 (7 << HRTIM_MCR_CKPSC_SHIFT)
#define HRTIM_MCR_CONT (1 << 3) /* Bit 3: Continuous mode */
#define HRTIM_MCR_RETRIG (1 << 4) /* Bit 4: Re-triggerable mode */
#define HRTIM_MCR_HALF (1 << 5) /* Bit 5: Half mode */
#define HRTIM_MCR_SYNCIN_SHIFT 8 /* Bits 8-9: Synchronization input */
#define HRTIM_CMNCR_CKPSC_SHIFT 0 /* Bits 0-2: Clock prescaler */
#define HRTIM_CMNCR_CKPSC_MASK (7 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_NODIV (0 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d2 (1 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d4 (2 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d8 (3 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d16 (4 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d32 (5 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d64 (6 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d128 (7 << HRTIM_CMNCR_CKPSC_SHIFT)
#define HRTIM_CMNCR_CONT (1 << 3) /* Bit 3: Continuous mode */
#define HRTIM_CMNCR_RETRIG (1 << 4) /* Bit 4: Re-triggerable mode */
#define HRTIM_CMNCR_HALF (1 << 5) /* Bit 5: Half mode */
/* Bits 6-9 differs */
#define HRTIM_CMNCR_SYNCRST (1 << 10) /* Bit 10: Synchronization Resets Master */
#define HRTIM_CMNCR_SYNCSTRTM (1 << 11) /* Bit 11: Synchronization Starts Master */
/* Bits 12-24 differs */
#define HRTIM_CMNCR_DACSYNC_SHIFT 25 /* Bits 25-26: DAC Synchronization*/
#define HRTIM_CMNCR_DACSYNC_MASK (3 << HRTIM_CMNCR_DACSYNC_SHIFT)
# define HRTIM_CMNCR_DACSYNC_00 (0 << HRTIM_CMNCR_DACSYNC_SHIFT) /* 00: */
# define HRTIM_CMNCR_DACSYNC_01 (1 << HRTIM_CMNCR_DACSYNC_SHIFT) /* 01: */
# define HRTIM_CMNCR_DACSYNC_10 (2 << HRTIM_CMNCR_DACSYNC_SHIFT) /* 10: */
# define HRTIM_CMNCR_DACSYNC_11 (3 << HRTIM_CMNCR_DACSYNC_SHIFT) /* 11: */
#define HRTIM_CMNCR_PREEN (1 << 27) /* Bit 27: Preload enable */
/* Bits 29-31 differs */
/* Control Register Bits specific to Master Timer */
/* Bits 0-5 common */
/* Bits 6-7 reserved */
/* Bits 10-11 common */
#define HRTIM_MCR_SYNCIN_SHIFT 8 /* Bits 8-9: Synchronization input */
#define HRTIM_MCR_SYNCIN_MASK (3 << HRTIM_MCR_SYNCIN_SHIFT)
# define HRTIM_MCR_SYNCIN_DIS (0 << HRTIM_MCR_SYNCIN_SHIFT) /* 00 disabled */
# define HRTIM_MCR_SYNCIN_INTE (2 << HRTIM_MCR_SYNCIN_SHIFT) /* 10: Internal Event */
# define HRTIM_MCR_SYNCIN_EXTE (3 << HRTIM_MCR_SYNCIN_SHIFT) /* 11: External Event */
#define HRTIM_MCR_SYNCRST (1 << 10) /* Bit 10: Synchronization Resets Master */
#define HRTIM_MCR_SYNCSTRTM (1 << 11) /* Bit 11: Synchronization Starts Master */
#define HRTIM_MCR_SYNCOUT_SHIFT 12 /* Bits 12-13: Synchronization output */
#define HRTIM_MCR_SYNCOUT_SHIFT 12 /* Bits 12-13: Synchronization output */
#define HRTIM_MCR_SYNCOUT_MASK (3 << HRTIM_MCR_SYNCOUT_SHIFT)
# define HRTIM_MCR_SYNCOUT_DIS (0 << HRTIM_MCR_SYNCOUT_SHIFT) /* 00: Disabled */
# define HRTIM_MCR_SYNCOUT_POS (2 << HRTIM_MCR_SYNCOUT_SHIFT) /* 10: Positive pulse on SCOUT */
# define HRTIM_MCR_SYNCOUT_NEG (3 << HRTIM_MCR_SYNCOUT_SHIFT) /* 11: Negative pulse on SCOUT */
#define HRTIM_MCR_SYNCSRC_SHIFT 14 /* Bits 14-15: Synchronization source*/
#define HRTIM_MCR_SYNCSRC_SHIFT 14 /* Bits 14-15: Synchronization source*/
#define HRTIM_MCR_SYNCSRC_MASK (3 << HRTIM_MCR_SYNCSRC_SHIFT)
# define HRTIM_MCR_SYNCSRC_MSTRT (0 << HRTIM_MCR_SYNCSRC_SHIFT) /* 00: Master timer Start */
# define HRTIM_MCR_SYNCSRC_MCMP1 (1 << HRTIM_MCR_SYNCSRC_SHIFT) /* 01: Master timer Compare 1 Event */
@ -382,15 +262,10 @@
#define HRTIM_MCR_TCCEN (1 << 19) /* Bit 19: Timer C counter enable */
#define HRTIM_MCR_TDCEN (1 << 20) /* Bit 20: Timer D counter enable */
#define HRTIM_MCR_TECEN (1 << 21) /* Bit 21: Timer E counter enable */
#define HRTIM_MCR_DACSYNC_SHIFT 25 /* Bits 25-26: DAC Synchronization*/
#define HRTIM_MCR_DACSYNC_MASK (3 << HRTIM_MCR_DACSYNC_SHIFT)
# define HRTIM_MCR_DACSYNC_00 (0 << HRTIM_MCR_DACSYNC_SHIFT) /* 00: */
# define HRTIM_MCR_DACSYNC_01 (1 << HRTIM_MCR_DACSYNC_SHIFT) /* 01: */
# define HRTIM_MCR_DACSYNC_10 (2 << HRTIM_MCR_DACSYNC_SHIFT) /* 10: */
# define HRTIM_MCR_DACSYNC_11 (3 << HRTIM_MCR_DACSYNC_SHIFT) /* 11: */
#define HRTIM_MCR_PREEN (1 << 27) /* Bit 27: Preload enable */
/* Bits 22-24 reserved */
/* Bits 25-27 common */
#define HRTIM_MCR_MREPU (1 << 29) /* Bit 29: Master Timer Repetition Update */
#define HRTIM_MCR_BRSTDMA_SHIFT 30 /* Bits 30-31: Burs DMA Update*/
#define HRTIM_MCR_BRSTDMA_SHIFT 30 /* Bits 30-31: Burs DMA Update*/
#define HRTIM_MCR_BRSTDMA_MASK (3 << HRTIM_MCR_BRSTDMA_SHIFT)
# define HRTIM_MCR_BRSTDMA_00 (0 << HRTIM_MCR_BRSTDMA_SHIFT) /* 00 */
# define HRTIM_MCR_BRSTDMA_01 (1 << HRTIM_MCR_BRSTDMA_SHIFT) /* 01 */
@ -468,24 +343,11 @@
#define HRTIM_MCMP4_SHIFT 0 /* Bits 0-15: Master Timer Compare 4 value */
#define HRTIM_MCMP4_MASK (0xffff << HRTIM_MCMP4_SHIFT)
/* Timer X Control Register */
/* Timer A-E Control Register */
#define HRTIM_TIMCR_CKPSC_SHIFT 0 /* Bits 0-2: HRTIM Timer X Clock Prescaler */
#define HRTIM_TIMCR_CKPSC_MASK (7 << HRTIM_TIMCR_CKPSC_SHIFT)
# define HRTIM_TIMCR_CKPSC_000 (0 << HRTIM_TIMCR_CKPSC_SHIFT) /* 000: */
# define HRTIM_TIMCR_CKPSC_001 (1 << HRTIM_TIMCR_CKPSC_SHIFT) /* 001: */
# define HRTIM_TIMCR_CKPSC_010 (2 << HRTIM_TIMCR_CKPSC_SHIFT) /* 010: */
# define HRTIM_TIMCR_CKPSC_011 (3 << HRTIM_TIMCR_CKPSC_SHIFT) /* 011: */
# define HRTIM_TIMCR_CKPSC_100 (4 << HRTIM_TIMCR_CKPSC_SHIFT) /* 100: */
# define HRTIM_TIMCR_CKPSC_101 (5 << HRTIM_TIMCR_CKPSC_SHIFT) /* 101: */
# define HRTIM_TIMCR_CKPSC_110 (6 << HRTIM_TIMCR_CKPSC_SHIFT) /* 110: */
# define HRTIM_TIMCR_CKPSC_111 (7 << HRTIM_TIMCR_CKPSC_SHIFT) /* 111: */
#define HRTIM_TIMCR_CONT (1 << 3) /* Bit 3: Continuous mode */
#define HRTIM_TIMCR_RETRIG (1 << 4) /* Bit 4: Re-triggerable mode */
#define HRTIM_TIMCR_HALF (1 << 5) /* Bit 5: Half mode enable */
#define HRTIM_TIMCR_PSHPLL (1 << 6) /* Bit 6:Push-Pull mode enable */
#define HRTIM_TIMCR_SYNCRS (1 << 10) /* Bit 10: Synchronization Resets Timer X */
#define HRTIM_TIMCR_SYNCSTR (1 << 11) /* Bit 11: Synchronization Starts Timer X */
/* Bits 0-5 common */
#define HRTIM_TIMCR_PSHPLL (1 << 6) /* Bit 6:Push-Pull mode enable */
/* Bits 10-11 common */
#define HRTIM_TIMCR_DELCMP2_SHIFT 12 /* Bits 12-13: CMP2 auto-delayed mode */
#define HRTIM_TIMCR_DELCMP2_MASK (3 << HRTIM_TIMCR_DELCMP2_SHIFT)
# define HRTIM_TIMCR_DELCMP2_00 (0 << HRTIM_TIMCR_DELCMP2_SHIFT) /* 00: */
@ -506,13 +368,7 @@
#define HRTIM_TIMCR_TDU (1 << 22) /* Bit 22: Timer D Update */
#define HRTIM_TIMCR_TEU (1 << 23) /* Bit 23: Timer E Update */
#define HRTIM_TIMCR_MSTU (1 << 24) /* Bit 24: Master Timer Update */
#define HRTIM_TIMCR_DACSYNC_SHIFT 25 /* Bits 25-26: DAC Synchronization */
#define HRTIM_TIMCR_DACSYNC_MASK (3 << HRTIM_TIMCR_DACSYNC_SHIFT)
# define HRTIM_TIMCR_DACSYNC_00 (0 << HRTIM_TIMCR_DACSYNC_SHIFT)
# define HRTIM_TIMCR_DACSYNC_01 (1 << HRTIM_TIMCR_DACSYNC_SHIFT)
# define HRTIM_TIMCR_DACSYNC_10 (2 << HRTIM_TIMCR_DACSYNC_SHIFT)
# define HRTIM_TIMCR_DACSYNC_11 (3 << HRTIM_TIMCR_DACSYNC_SHIFT)
#define HRTIM_TIMCR_PREEN (1 << 27) /* Bit 27: Preload Enable */
/* Bits 25-27 common */
#define HRTIM_TIMCR_UPDGAT_SHIFT 28 /* Bits 28-31: Update Gating */
#define HRTIM_TIMCR_UPDGAT_MASK (15 << HRTIM_TIMCR_UPDGAT_SHIFT)
# define HRTIM_TIMCR_UPDGAT_0000 (0 << HRTIM_TIMCR_UPDGAT_SHIFT) /* 0000: */
@ -838,7 +694,7 @@
# define HRTIM_TIMEEF1_EE2FLT_0 (0 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0000: No filtering */
# define HRTIM_TIMEEF1_EE2FLT_1 (1 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0001: Blanking from counter reset/roll-over to Compare 1 */
# define HRTIM_TIMEEF1_EE2FLT_2 (2 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0010: Blanking from counter reset/roll-over to Compare 2 */
# define HRTIM_TIMEEF1_EE2FLT_2 (3 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0011: Blanking from counter reset/roll-over to Compare 3 */
# define HRTIM_TIMEEF1_EE2FLT_3 (3 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0011: Blanking from counter reset/roll-over to Compare 3 */
# define HRTIM_TIMEEF1_EE2FLT_4 (4 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0100: Blanking from counter reset/roll-over to Compare 4 */
# define HRTIM_TIMEEF1_EE2FLT_5 (5 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0101: Blanking from TIMFLTR1 source */
# define HRTIM_TIMEEF1_EE2FLT_6 (6 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0110: Blanking from TIMFLTR2 source */

1
arch/arm/src/stm32/stm32.h
View File

@ -67,6 +67,7 @@
#include "stm32_flash.h"
#include "stm32_fsmc.h"
#include "stm32_gpio.h"
#include "stm32_hrtim.h"
#include "stm32_i2c.h"
#include "stm32_ltdc.h"
#include "stm32_opamp.h"

2
arch/arm/src/stm32/stm32f33xxx_rcc.c
View File

@ -332,9 +332,7 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32_HRTIM1
/* HRTIM1 Timer clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB2ENR_HRTIM1EN;
#endif
#endif
putreg32(regval, STM32_RCC_APB2ENR);