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cortex-m/assert: dump all registers with alias

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Signed-off-by: chao.an <anchao@xiaomi.com>
This commit is contained in:
chao.an 2021-11-30 22:06:35 +08:00 committed by Xiang Xiao
parent 0161da4415
commit 437c81f8d0
3 changed files with 26 additions and 20 deletions
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14
arch/arm/src/armv6-m/arm_assert.c
View File

@ -107,12 +107,14 @@ static inline void up_registerdump(FAR volatile uint32_t *regs)
/* Dump the interrupt registers */
_alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
_alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
_alert("R0: %08x R1: %08x R2: %08x R3: %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3]);
_alert("R4: %08x R5: %08x R6: %08x FP: %08x\n",
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
_alert("R8: %08x SB: %08x SL: %08x R11: %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11]);
_alert("IP: %08x SP: %08x LR: %08x PC: %08x\n",
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
_alert("xPSR: %08x PRIMASK: %08x EXEC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);

16
arch/arm/src/armv7-m/arm_assert.c
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@ -110,12 +110,14 @@ static inline void up_registerdump(FAR volatile uint32_t *regs)
/* Dump the interrupt registers */
_alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
_alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
_alert("R0: %08x R1: %08x R2: %08x R3: %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3]);
_alert("R4: %08x R5: %08x R6: %08x FP: %08x\n",
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
_alert("R8: %08x SB: %08x SL: %08x R11: %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11]);
_alert("IP: %08x SP: %08x LR: %08x PC: %08x\n",
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
#ifdef CONFIG_ARMV7M_USEBASEPRI
_alert("xPSR: %08x BASEPRI: %08x CONTROL: %08x\n",
@ -125,7 +127,7 @@ static inline void up_registerdump(FAR volatile uint32_t *regs)
regs[REG_XPSR], regs[REG_PRIMASK], getcontrol());
#endif
#ifdef REG_EXC_RETURN
#ifdef CONFIG_BUILD_PROTECTED
_alert("EXC_RETURN: %08x\n", regs[REG_EXC_RETURN]);
#endif
}

16
arch/arm/src/armv8-m/arm_assert.c
View File

@ -110,12 +110,14 @@ static inline void up_registerdump(FAR volatile uint32_t *regs)
/* Dump the interrupt registers */
_alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
_alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
_alert("R0: %08x R1: %08x R2: %08x R3: %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3]);
_alert("R4: %08x R5: %08x R6: %08x FP: %08x\n",
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
_alert("R8: %08x SB: %08x SL: %08x R11: %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11]);
_alert("IP: %08x SP: %08x LR: %08x PC: %08x\n",
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
#ifdef CONFIG_ARMV8M_USEBASEPRI
_alert("xPSR: %08x BASEPRI: %08x CONTROL: %08x\n",
@ -125,7 +127,7 @@ static inline void up_registerdump(FAR volatile uint32_t *regs)
regs[REG_XPSR], regs[REG_PRIMASK], getcontrol());
#endif
#ifdef REG_EXC_RETURN
#ifdef CONFIG_BUILD_PROTECTED
_alert("EXC_RETURN: %08x\n", regs[REG_EXC_RETURN]);
#endif
}