arch/arm/src/samd5e5/: Some failed attempts to get the USART SERCOM initialized. Still worthy changes although they do not solve the problem.
This commit is contained in:
Gregory Nutt
parent
25dce66483
commit
438f6a866b
@ -337,6 +337,10 @@ config SAMD5E5_HAVE_TC7
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bool
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default n
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config SAMD5E5_SERCOM
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bool
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default n
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config SAMD5E5_AC
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bool "Analog Comparator"
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default n
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@ -376,35 +380,43 @@ config SAMD5E5_RTC
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config SAMD5E5_SERCOM0
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bool "Serial Communication Interface 0"
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default n
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select SAMD5E5_SERCOM
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config SAMD5E5_SERCOM1
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bool "Serial Communication Interface 1"
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default n
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select SAMD5E5_SERCOM
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config SAMD5E5_SERCOM2
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bool "Serial Communication Interface 2"
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default n
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select SAMD5E5_SERCOM
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config SAMD5E5_SERCOM3
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bool "Serial Communication Interface 3"
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default n
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select SAMD5E5_SERCOM
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config SAMD5E5_SERCOM4
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bool "Serial Communication Interface 4"
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default n
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select SAMD5E5_SERCOM
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config SAMD5E5_SERCOM5
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bool "Serial Communication Interface 5"
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default n
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select SAMD5E5_SERCOM
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config SAMD5E5_SERCOM6
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bool "Serial Communication Interface 6"
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default n
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select SAMD5E5_SERCOM
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depends on SAMD5E5_HAVE_SERCOM6
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config SAMD5E5_SERCOM7
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bool "Serial Communication Interface 7"
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default n
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select SAMD5E5_SERCOM
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depends on SAMD5E5_HAVE_SERCOM7
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config SAMD5E5_TC0
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@ -471,6 +483,9 @@ config SAMD5E5_DMAC_NDESC
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Each additional DMA descriptor will require 16-bytes for LPRAM
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memory.
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menu "SERCOM Configuration"
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depends on SAMD5E5_SERCOM
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choice
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prompt "SERCOM0 mode"
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default SAMD5E5_SERCOM0_ISUSART
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@ -630,6 +645,7 @@ config SAMD5E5_SERCOM7_ISUSART
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select USART7_SERIALDRIVER
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endchoice
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endmenu # SERCOM Configuration
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config SAMD5E5_HAVE_SPI
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bool
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@ -88,8 +88,7 @@ endif
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CHIP_ASRCS =
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CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_gclk.c sam_irq.c
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CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_sercom.c sam_start.c
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CHIP_CSRCS += sam_usart.c
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CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c sam_usart.c
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# Configuration-dependent SAMD5x/E5x files
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@ -97,6 +96,10 @@ ifneq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += sam_timerisr.c
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endif
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ifeq ($(CONFIG_SAMD5E5_SERCOM),y)
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CHIP_CSRCS += sam_sercom.c
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endif
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ifeq ($(CONFIG_SAMD5E5_TC),y)
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CHIP_CSRCS += sam_tc.c
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@ -292,7 +292,8 @@ int sam_usart_internal(const struct sam_usart_config_s * const config)
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/* Configure the GCLKs for the SERCOM module */
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sercom_coreclk_configure(config->sercom, config->coregen, false);
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sercom_coreclk_configure(config->sercom, config->coregen,
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(bool)config->corelock);
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sercom_slowclk_configure(config->sercom, config->slowgen);
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/* Set USART configuration according to the board configuration */
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@ -202,7 +202,8 @@ void sercom_slowclk_configure(int sercom, int slowgen)
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* of SERCOM modules and, hence, only need to configured once.
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*/
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sam_gclk_chan_enable(GCLK_CHAN_SERCOMn_SLOW, slowgen, true);
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sam_gclk_chan_enable(GCLK_CHAN_SERCOMn_SLOW, slowgen,
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BOARD_SERCOM_SLOWLOCK);
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/* The slow clock is now configured and should not be re=configured
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* again.
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@ -70,8 +70,9 @@ const struct sam_usart_config_s g_usart0config =
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.txirq = BOARD_TXIRQ_SERCOM0,
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.rxirq = BOARD_RXIRQ_SERCOM0,
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.coregen = BOARD_SERCOM0_COREGEN,
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.slowgen = BOARD_SERCOM0_SLOWGEN,
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.slowgen = BOARD_SERCOM_SLOWGEN,
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.stopbits2 = CONFIG_USART0_2STOP,
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.corelock = BOARD_SERCOM0_CORELOCK,
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.baud = CONFIG_USART0_BAUD,
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.pad0 = BOARD_SERCOM0_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM0_PINMAP_PAD1,
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@ -92,8 +93,9 @@ const struct sam_usart_config_s g_usart1config =
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.txirq = BOARD_TXIRQ_SERCOM1,
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.rxirq = BOARD_RXIRQ_SERCOM1,
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.coregen = BOARD_SERCOM1_COREGEN,
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.slowgen = BOARD_SERCOM1_SLOWGEN,
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.slowgen = BOARD_SERCOM_SLOWGEN,
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.stopbits2 = CONFIG_USART1_2STOP,
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.corelock = BOARD_SERCOM1_CORELOCK,
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.baud = CONFIG_USART1_BAUD,
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.pad0 = BOARD_SERCOM1_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM1_PINMAP_PAD1,
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@ -114,8 +116,9 @@ const struct sam_usart_config_s g_usart2config =
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.txirq = BOARD_TXIRQ_SERCOM2,
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.rxirq = BOARD_RXIRQ_SERCOM2,
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.coregen = BOARD_SERCOM2_COREGEN,
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.slowgen = BOARD_SERCOM2_SLOWGEN,
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.slowgen = BOARD_SERCOM_SLOWGEN,
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.stopbits2 = CONFIG_USART2_2STOP,
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.corelock = BOARD_SERCOM2_CORELOCK,
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.baud = CONFIG_USART2_BAUD,
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.pad0 = BOARD_SERCOM2_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM2_PINMAP_PAD1,
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@ -136,8 +139,9 @@ const struct sam_usart_config_s g_usart3config =
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.txirq = BOARD_TXIRQ_SERCOM3,
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.rxirq = BOARD_RXIRQ_SERCOM3,
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.coregen = BOARD_SERCOM3_COREGEN,
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.slowgen = BOARD_SERCOM3_SLOWGEN,
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.slowgen = BOARD_SERCOM_SLOWGEN,
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.stopbits2 = CONFIG_USART3_2STOP,
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.corelock = BOARD_SERCOM3_CORELOCK,
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.baud = CONFIG_USART3_BAUD,
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.pad0 = BOARD_SERCOM3_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM3_PINMAP_PAD1,
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@ -158,8 +162,9 @@ const struct sam_usart_config_s g_usart4config =
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.txirq = BOARD_TXIRQ_SERCOM4,
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.rxirq = BOARD_RXIRQ_SERCOM4,
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.coregen = BOARD_SERCOM4_COREGEN,
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.slowgen = BOARD_SERCOM4_SLOWGEN,
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.slowgen = BOARD_SERCOM_SLOWGEN,
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.stopbits2 = CONFIG_USART4_2STOP,
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.corelock = BOARD_SERCOM4_CORELOCK,
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.baud = CONFIG_USART4_BAUD,
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.pad0 = BOARD_SERCOM4_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM4_PINMAP_PAD1,
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@ -180,8 +185,9 @@ const struct sam_usart_config_s g_usart5config =
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.txirq = BOARD_TXIRQ_SERCOM5,
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.rxirq = BOARD_RXIRQ_SERCOM5,
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.coregen = BOARD_SERCOM5_COREGEN,
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.slowgen = BOARD_SERCOM5_SLOWGEN,
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.slowgen = BOARD_SERCOM_SLOWGEN,
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.stopbits2 = CONFIG_USART5_2STOP,
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.corelock = BOARD_SERCOM5_CORELOCK,
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.baud = CONFIG_USART5_BAUD,
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.pad0 = BOARD_SERCOM5_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM5_PINMAP_PAD1,
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@ -202,8 +208,9 @@ const struct sam_usart_config_s g_usart6config =
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.txirq = BOARD_TXIRQ_SERCOM6,
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.rxirq = BOARD_RXIRQ_SERCOM6,
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.coregen = BOARD_SERCOM6_COREGEN,
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.slowgen = BOARD_SERCOM6_SLOWGEN,
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.slowgen = BOARD_SERCOM_SLOWGEN,
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.stopbits2 = CONFIG_USART6_2STOP,
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.corelock = BOARD_SERCOM6_CORELOCK,
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.baud = CONFIG_USART6_BAUD,
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.pad0 = BOARD_SERCOM6_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM6_PINMAP_PAD1,
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@ -224,8 +231,9 @@ const struct sam_usart_config_s g_usart7config =
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.txirq = BOARD_TXIRQ_SERCOM7,
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.rxirq = BOARD_RXIRQ_SERCOM7,
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.coregen = BOARD_SERCOM7_COREGEN,
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.slowgen = BOARD_SERCOM7_SLOWGEN,
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.slowgen = BOARD_SERCOM_SLOWGEN,
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.stopbits2 = CONFIG_USART7_2STOP,
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.corelock = BOARD_SERCOM7_CORELOCK,
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.baud = CONFIG_USART7_BAUD,
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.pad0 = BOARD_SERCOM7_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM7_PINMAP_PAD1,
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@ -56,6 +56,7 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Pick the console USART configuration */
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#if defined(CONFIG_USART0_SERIAL_CONSOLE)
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@ -85,22 +86,23 @@
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struct sam_usart_config_s
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{
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uint8_t sercom; /* Identifies the SERCOM peripheral */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (5-9) */
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uint8_t txirq; /* Tx SERCOM IRQ number */
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uint8_t rxirq; /* Rx SERCOM IRQ number */
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uint8_t coregen; /* Core GCLK generator */
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uint8_t slowgen; /* Slow GCLK generator */
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bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
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uint32_t baud; /* Configured baud */
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port_pinset_t pad0; /* Pin configuration for PAD0 */
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port_pinset_t pad1; /* Pin configuration for PAD1 */
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port_pinset_t pad2; /* Pin configuration for PAD2 */
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port_pinset_t pad3; /* Pin configuration for PAD3 */
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uint32_t muxconfig; /* Pad multiplexing configuration */
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uint32_t frequency; /* Source clock frequency */
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uintptr_t base; /* SERCOM base address */
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uint8_t sercom; /* Identifies the SERCOM peripheral */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (5-9) */
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uint8_t txirq; /* Tx SERCOM IRQ number */
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uint8_t rxirq; /* Rx SERCOM IRQ number */
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uint8_t coregen; /* Core GCLK generator */
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uint8_t slowgen; /* Slow GCLK generator */
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uint8_t stopbits2 : 1; /* True: Configure with 2 stop bits instead of 1 */
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uint8_t corelock : 1; /* True: Lock the CORE clock */
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uint32_t baud; /* Configured baud */
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port_pinset_t pad0; /* Pin configuration for PAD0 */
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port_pinset_t pad1; /* Pin configuration for PAD1 */
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port_pinset_t pad2; /* Pin configuration for PAD2 */
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port_pinset_t pad3; /* Pin configuration for PAD3 */
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uint32_t muxconfig; /* Pad multiplexing configuration */
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uint32_t frequency; /* Source clock frequency */
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uintptr_t base; /* SERCOM base address */
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};
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/************************************************************************************
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@ -42,15 +42,18 @@
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#ifndef TRUE
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# define TRUE 1
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#endif
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#ifndef FALSE
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# define FALSE 0
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#endif
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/* Clocking *************************************************************************/
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/* Overview
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*
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@ -99,16 +102,16 @@
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/* XOSC32 */
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#define BOARD_HAVE_XOSC32K 1 /* 32.768 KHz XOSC32 crystal installed */
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#define BOARD_XOSC32K_ENABLE true /* Enable XOSC32 */
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#define BOARD_XOSC32K_XTALEN false /* External clock connected on XIN32 */
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#define BOARD_XOSC32K_EN32K false /* No 32KHz output */
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#define BOARD_XOSC32K_EN1K false /* No 1KHz output */
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#define BOARD_XOSC32K_HIGHSPEED true /* High speed mode */
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#define BOARD_XOSC32K_RUNSTDBY false /* Don't run in standby */
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#define BOARD_XOSC32K_ONDEMAND true /* Enable on-demand control */
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#define BOARD_XOSC32K_CFDEN false /* Clock failure detector not enabled */
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#define BOARD_XOSC32K_CFDEO false /* No clock failure event */
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#define BOARD_XOSC32K_CALIBEN false /* No OSCULP32K calibration */
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#define BOARD_XOSC32K_ENABLE TRUE /* Enable XOSC32 */
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#define BOARD_XOSC32K_XTALEN TRUE /* Crystal connected on XIN32 */
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#define BOARD_XOSC32K_EN32K FALSE /* No 32KHz output */
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#define BOARD_XOSC32K_EN1K FALSE /* No 1KHz output */
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#define BOARD_XOSC32K_HIGHSPEED TRUE /* High speed mode */
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#define BOARD_XOSC32K_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_XOSC32K_ONDEMAND TRUE /* Enable on-demand control */
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#define BOARD_XOSC32K_CFDEN FALSE /* Clock failure detector not enabled */
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#define BOARD_XOSC32K_CFDEO FALSE /* No clock failure event */
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#define BOARD_XOSC32K_CALIBEN FALSE /* No OSCULP32K calibration */
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#define BOARD_XOSC32K_STARTUP 0 /* Startup time: 62592us */
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#define BOARD_XOSC32K_CALIB 0 /* Dummy OSCULP32K calibration value */
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#define BOARD_XOSC32K_RTCSEL 0 /* RTC clock = ULP1K */
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@ -116,27 +119,27 @@
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/* XOSC0 */
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#define BOARD_HAVE_XOSC0 0 /* No XOSC0 clock/crystal installed */
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#define BOARD_XOSC0_ENABLE false /* Don't enable XOSC0 */
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#define BOARD_XOSC0_XTALEN false /* External clock connected */
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#define BOARD_XOSC0_RUNSTDBY false /* Don't run in standby */
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#define BOARD_XOSC0_ONDEMAND true /* Disable on-demand control */
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#define BOARD_XOSC0_LOWGAIN false /* Disable low buffer gain */
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#define BOARD_XOSC0_ENALC false /* Disable automatic loop control */
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#define BOARD_XOSC0_CFDEN false /* Clock failure detector not enabled */
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#define BOARD_XOSC0_SWBEN false /* XOSC clock switch not enabled */
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#define BOARD_XOSC0_ENABLE FALSE /* Don't enable XOSC0 */
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#define BOARD_XOSC0_XTALEN FALSE /* External clock connected */
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#define BOARD_XOSC0_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_XOSC0_ONDEMAND TRUE /* Disable on-demand control */
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#define BOARD_XOSC0_LOWGAIN FALSE /* Disable low buffer gain */
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#define BOARD_XOSC0_ENALC FALSE /* Disable automatic loop control */
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#define BOARD_XOSC0_CFDEN FALSE /* Clock failure detector not enabled */
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#define BOARD_XOSC0_SWBEN FALSE /* XOSC clock switch not enabled */
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#define BOARD_XOSC0_STARTUP 0 /* XOSC0 start-up time 31µs */
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/* XOSC1 */
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#define BOARD_HAVE_XOSC1 0 /* No XOSC0 clock/crystal installed */
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#define BOARD_XOSC1_ENABLE false /* Don't enable XOSC1 */
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#define BOARD_XOSC1_XTALEN true /* External crystal connected */
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#define BOARD_XOSC1_RUNSTDBY false /* Don't run in standby */
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#define BOARD_XOSC1_ONDEMAND true /* Disable on-demand control */
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#define BOARD_XOSC1_LOWGAIN false /* Disable low buffer gain */
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#define BOARD_XOSC1_ENALC false /* Disable automatic loop control */
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#define BOARD_XOSC1_CFDEN false /* Clock failure detector not enabled */
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#define BOARD_XOSC1_SWBEN false /* XOSC clock switch not enabled */
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#define BOARD_XOSC1_ENABLE FALSE /* Don't enable XOSC1 */
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#define BOARD_XOSC1_XTALEN TRUE /* External crystal connected */
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#define BOARD_XOSC1_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_XOSC1_ONDEMAND TRUE /* Disable on-demand control */
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#define BOARD_XOSC1_LOWGAIN FALSE /* Disable low buffer gain */
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#define BOARD_XOSC1_ENALC FALSE /* Disable automatic loop control */
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#define BOARD_XOSC1_CFDEN FALSE /* Clock failure detector not enabled */
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#define BOARD_XOSC1_SWBEN FALSE /* XOSC clock switch not enabled */
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#define BOARD_XOSC1_STARTUP 0 /* XOSC0 start-up time 31µs */
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/* GCLK */
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@ -144,108 +147,108 @@
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#define BOARD_GCLK_SET1 0x0020 /* Pre-configure: GCLK5 needed by DPLL0 */
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#define BOARD_GCLK_SET2 0x0fdf /* Post-configure: All GCLKs except GCLK5 */
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#define BOARD_GCLK0_ENABLE true /* Enable GCLK0 */
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#define BOARD_GCLK0_IDC false /* Don't improve duty cycle */
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#define BOARD_GCLK0_OOV false /* Clock output will be LOW */
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#define BOARD_GCLK0_OE true /* Generate output on GCLK_IO */
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#define BOARD_GCLK0_ENABLE TRUE /* Enable GCLK0 */
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#define BOARD_GCLK0_IDC FALSE /* Don't improve duty cycle */
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#define BOARD_GCLK0_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK0_OE TRUE /* Generate output on GCLK_IO */
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#define BOARD_GCLK0_DIVSEL 0 /* GCLK frequency is source/DIV */
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#define BOARD_GCLK0_RUNSTDBY false /* Don't run in standby */
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#define BOARD_GCLK0_RUNSTDBY FALSE /* Don't run in standby */
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#define BOARD_GCLK0_SOURCE 7 /* Select DPLL0 output as GCLK0 source */
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#define BOARD_GCLK0_DIV 1 /* Division factor */
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#define BOARD_GCLK1_ENABLE true /* Enable GCLK1 */
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#define BOARD_GCLK1_OOV false /* Clock output will be LOW */
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#define BOARD_GCLK1_OE true /* Generate output on GCLK_IO */
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#define BOARD_GCLK1_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK1_ENABLE TRUE /* Enable GCLK1 */
|
||||
#define BOARD_GCLK1_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK1_OE TRUE /* Generate output on GCLK_IO */
|
||||
#define BOARD_GCLK1_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GCLK1 source */
|
||||
#define BOARD_GCLK1_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK2_ENABLE false /* Don't enable GCLK2 */
|
||||
#define BOARD_GCLK2_OOV false /* Clock output will be LOW */
|
||||
#define BOARD_GCLK2_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK2_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK2_ENABLE FALSE /* Don't enable GCLK2 */
|
||||
#define BOARD_GCLK2_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK2_OE FALSE /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK2_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK2_SOURCE 5 /* Select XOSC32K as GCLK2 source */
|
||||
#define BOARD_GCLK2_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK3_ENABLE true /* Enable GCLK3 */
|
||||
#define BOARD_GCLK3_OOV false /* Clock output will be LOW */
|
||||
#define BOARD_GCLK3_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK3_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK3_ENABLE TRUE /* Enable GCLK3 */
|
||||
#define BOARD_GCLK3_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK3_OE FALSE /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK3_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
|
||||
#define BOARD_GCLK3_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK4_ENABLE true /* Enable GCLK4 */
|
||||
#define BOARD_GCLK4_OOV false /* Clock output will be LOW */
|
||||
#define BOARD_GCLK4_OE true /* Generate output on GCLK_IO */
|
||||
#define BOARD_GCLK4_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK4_ENABLE TRUE /* Enable GCLK4 */
|
||||
#define BOARD_GCLK4_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK4_OE TRUE /* Generate output on GCLK_IO */
|
||||
#define BOARD_GCLK4_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GCLK4 source */
|
||||
#define BOARD_GCLK4_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK5_ENABLE true /* Enable GCLK5 */
|
||||
#define BOARD_GCLK5_OOV false /* Clock output will be LOW */
|
||||
#define BOARD_GCLK5_OE true /* Generate output on GCLK_IO */
|
||||
#define BOARD_GCLK5_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK5_ENABLE TRUE /* Enable GCLK5 */
|
||||
#define BOARD_GCLK5_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK5_OE TRUE /* Generate output on GCLK_IO */
|
||||
#define BOARD_GCLK5_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GCLK5 source */
|
||||
#define BOARD_GCLK5_DIV 24 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK6_ENABLE false /* Don't enable GCLK6 */
|
||||
#define BOARD_GCLK6_OOV false /* Clock output will be LOW */
|
||||
#define BOARD_GCLK6_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK6_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK6_ENABLE FALSE /* Don't enable GCLK6 */
|
||||
#define BOARD_GCLK6_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK6_OE FALSE /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK6_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GCLK6 source */
|
||||
#define BOARD_GCLK6_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK7_ENABLE false /* Don't enable GCLK7 */
|
||||
#define BOARD_GCLK7_OOV false /* Clock output will be LOW */
|
||||
#define BOARD_GCLK7_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK7_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK7_ENABLE FALSE /* Don't enable GCLK7 */
|
||||
#define BOARD_GCLK7_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK7_OE FALSE /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK7_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GCLK7 source */
|
||||
#define BOARD_GCLK7_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK8_ENABLE false /* Don't enable GCLK8 */
|
||||
#define BOARD_GCLK8_OOV false /* Clock output will be LOW */
|
||||
#define BOARD_GCLK8_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK8_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK8_ENABLE FALSE /* Don't enable GCLK8 */
|
||||
#define BOARD_GCLK8_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK8_OE FALSE /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK8_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GCLK8 source */
|
||||
#define BOARD_GCLK8_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK9_ENABLE false /* Don't enable GCLK9 */
|
||||
#define BOARD_GCLK9_OOV false /* Clock output will be LOW */
|
||||
#define BOARD_GCLK9_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK9_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK9_ENABLE FALSE /* Don't enable GCLK9 */
|
||||
#define BOARD_GCLK9_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK9_OE FALSE /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK9_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GCLK9 source */
|
||||
#define BOARD_GCLK9_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK10_ENABLE false /* Don't enable GCLK10 */
|
||||
#define BOARD_GCLK10_OOV false /* Clock output will be LOW */
|
||||
#define BOARD_GCLK10_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK10_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK10_ENABLE FALSE /* Don't enable GCLK10 */
|
||||
#define BOARD_GCLK10_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK10_OE FALSE /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK10_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GCLK10 source */
|
||||
#define BOARD_GCLK10_DIV 1 /* Division factor */
|
||||
|
||||
#define BOARD_GCLK11_ENABLE false /* Don't enable GCLK11 */
|
||||
#define BOARD_GCLK11_OOV false /* Clock output will be LOW */
|
||||
#define BOARD_GCLK11_OE false /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK11_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_GCLK11_ENABLE FALSE /* Don't enable GCLK11 */
|
||||
#define BOARD_GCLK11_OOV FALSE /* Clock output will be LOW */
|
||||
#define BOARD_GCLK11_OE FALSE /* No generator output of GCLK_IO */
|
||||
#define BOARD_GCLK11_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GCLK11 source */
|
||||
#define BOARD_GCLK11_DIV 1 /* Division factor */
|
||||
#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY
|
||||
|
||||
/* FDLL */
|
||||
|
||||
#define BOARD_DFLL_ENABLE true /* DFLL enable */
|
||||
#define BOARD_DFLL_RUNSTDBY false /* Don't run in standby */
|
||||
#define BOARD_DFLL_ONDEMAND false /* No n-demand control */
|
||||
#define BOARD_DFLL_MODE false /* Open loop mode */
|
||||
#define BOARD_DFLL_STABLE false /* No stable DFLL frequency */
|
||||
#define BOARD_DFLL_LLAW false /* Don't ose lock after wake */
|
||||
#define BOARD_DFLL_USBCRM true /* Use USB clock recovery mode */
|
||||
#define BOARD_DFLL_CCDIS true /* Chill cycle disable */
|
||||
#define BOARD_DFLL_QLDIS false /* No Quick Lock Disable */
|
||||
#define BOARD_DFLL_BPLCKC false /* No ypass coarse clock */
|
||||
#define BOARD_DFLL_WAITLOCK true /* Wait lock */
|
||||
#define BOARD_DFLL_CALIBEN false /* Don't verwrite factory calibration */
|
||||
#define BOARD_DFLL_GCLKLOCK false /* Don't lock the GCLK source */
|
||||
#define BOARD_DFLL_ENABLE TRUE /* DFLL enable */
|
||||
#define BOARD_DFLL_RUNSTDBY FALSE /* Don't run in standby */
|
||||
#define BOARD_DFLL_ONDEMAND FALSE /* No n-demand control */
|
||||
#define BOARD_DFLL_MODE FALSE /* Open loop mode */
|
||||
#define BOARD_DFLL_STABLE FALSE /* No stable DFLL frequency */
|
||||
#define BOARD_DFLL_LLAW FALSE /* Don't ose lock after wake */
|
||||
#define BOARD_DFLL_USBCRM TRUE /* Use USB clock recovery mode */
|
||||
#define BOARD_DFLL_CCDIS TRUE /* Chill cycle disable */
|
||||
#define BOARD_DFLL_QLDIS FALSE /* No Quick Lock Disable */
|
||||
#define BOARD_DFLL_BPLCKC FALSE /* No ypass coarse clock */
|
||||
#define BOARD_DFLL_WAITLOCK TRUE /* Wait lock */
|
||||
#define BOARD_DFLL_CALIBEN FALSE /* Don't verwrite factory calibration */
|
||||
#define BOARD_DFLL_GCLKLOCK FALSE /* Don't lock the GCLK source */
|
||||
#define BOARD_DFLL_FCALIB 128 /* Coarse calibration value (if caliben) */
|
||||
#define BOARD_DFLL_CCALIB (31 / 4) /* Fine calibration value (if caliben) */
|
||||
#define BOARD_DFLL_FSTEP 1 /* Fine maximum step */
|
||||
@ -274,13 +277,13 @@
|
||||
* Fdpll = 32768 * (1463 + 1 + 13/32) = 47.986 MHz
|
||||
*/
|
||||
|
||||
#define BOARD_DPLL0_ENABLE true /* DPLL enable */
|
||||
#define BOARD_DPLL0_DCOEN false /* DCO filter enable */
|
||||
#define BOARD_DPLL0_LBYPASS false /* Lock bypass */
|
||||
#define BOARD_DPLL0_WUF false /* Wake up fast */
|
||||
#define BOARD_DPLL0_RUNSTDBY false /* Run in standby */
|
||||
#define BOARD_DPLL0_ONDEMAND false /* On demand clock activation */
|
||||
#define BOARD_DPLL0_REFLOCK false /* Do not lock reference clock section */
|
||||
#define BOARD_DPLL0_ENABLE TRUE /* DPLL enable */
|
||||
#define BOARD_DPLL0_DCOEN FALSE /* DCO filter enable */
|
||||
#define BOARD_DPLL0_LBYPASS FALSE /* Lock bypass */
|
||||
#define BOARD_DPLL0_WUF FALSE /* Wake up fast */
|
||||
#define BOARD_DPLL0_RUNSTDBY FALSE /* Run in standby */
|
||||
#define BOARD_DPLL0_ONDEMAND FALSE /* On demand clock activation */
|
||||
#define BOARD_DPLL0_REFLOCK FALSE /* Do not lock reference clock section */
|
||||
#define BOARD_DPLL0_REFCLK 0 /* Reference clock selection */
|
||||
#define BOARD_DPLL0_LTIME 0 /* Lock time */
|
||||
#define BOARD_DPLL0_FILTER 0 /* Proportional integer filter selection */
|
||||
@ -291,13 +294,13 @@
|
||||
#define BOARD_DPLL0_LDRINT 59 /* Loop divider ratio */
|
||||
#define BOARD_DPLL0_DIV 0 /* Clock divider */
|
||||
|
||||
#define BOARD_DPLL1_ENABLE false /* DPLL enable */
|
||||
#define BOARD_DPLL1_DCOEN false /* DCO filter enable */
|
||||
#define BOARD_DPLL1_LBYPASS false /* Lock bypass */
|
||||
#define BOARD_DPLL1_WUF false /* Wake up fast */
|
||||
#define BOARD_DPLL1_RUNSTDBY false /* Run in standby */
|
||||
#define BOARD_DPLL1_ONDEMAND false /* On demand clock activation */
|
||||
#define BOARD_DPLL1_REFLOCK false /* Do not lock reference clock section */
|
||||
#define BOARD_DPLL1_ENABLE FALSE /* DPLL enable */
|
||||
#define BOARD_DPLL1_DCOEN FALSE /* DCO filter enable */
|
||||
#define BOARD_DPLL1_LBYPASS FALSE /* Lock bypass */
|
||||
#define BOARD_DPLL1_WUF FALSE /* Wake up fast */
|
||||
#define BOARD_DPLL1_RUNSTDBY FALSE /* Run in standby */
|
||||
#define BOARD_DPLL1_ONDEMAND FALSE /* On demand clock activation */
|
||||
#define BOARD_DPLL1_REFLOCK FALSE /* Do not lock reference clock section */
|
||||
#define BOARD_DPLL1_REFCLK 1 /* Reference clock = XOSCK32 */
|
||||
#define BOARD_DPLL1_LTIME 0 /* Lock time */
|
||||
#define BOARD_DPLL1_FILTER 0 /* Sigma-delta DCO filter selection */
|
||||
@ -391,15 +394,19 @@
|
||||
|
||||
/* SERCOM definitions ***************************************************************/
|
||||
/* The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main
|
||||
* Clock Controller. The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and
|
||||
* GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the
|
||||
* SERCOM while working as a master. The slow clock (GCLK_SERCOMx_SLOW) is only
|
||||
* required for certain functions.
|
||||
* Clock Controller. The SERCOM uses two generic clocks: GCLK_SERCOMn_CORE and
|
||||
* GCLK_SERCOM_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the
|
||||
* SERCOM while working as a master. The slow clock (GCLK_SERCOM_SLOW) is only
|
||||
* required for certain functions and is common to all SERCOM modules.
|
||||
*
|
||||
* These clocks must be configured and enabled in the Generic Clock Controller (GCLK)
|
||||
* before using the SERCOM.
|
||||
*/
|
||||
|
||||
#define BOARD_SERCOM_SLOWGEN 3 /* 48MHz, common to all SERCOMS */
|
||||
#define BOARD_SERCOM_SLOWLOCK FALSE /* Don't lock the SLOWCLOCK */
|
||||
#define BOARD_SLOWCLOCK_FREQUENCY BOARD_GCLK3_FREQUENCY
|
||||
|
||||
/* SERCOM3
|
||||
*
|
||||
* An Arduino compatible serial Shield is assumed (or equivalently, an external
|
||||
@ -425,8 +432,8 @@
|
||||
#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0
|
||||
#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_1
|
||||
|
||||
#define BOARD_SERCOM3_COREGEN 1 /* 48MHz, common to all SERCOMS */
|
||||
#define BOARD_SERCOM3_SLOWGEN 3 /* 48MHz */
|
||||
#define BOARD_SERCOM3_COREGEN 1 /* 48MHz Core clock */
|
||||
#define BOARD_SERCOM3_CORELOCK FALSE /* Don't lock the CORECLOCK */
|
||||
#define BOARD_SERCOM3_FREQUENCY BOARD_GCLK1_FREQUENCY
|
||||
|
||||
/* USB */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user