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arch/arm/src/samd5e5/: Some failed attempts to get the USART SERCOM initialized. Still worthy changes although they do not solve the problem.

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This commit is contained in:
Gregory Nutt 2018-08-31 16:18:10 -06:00
parent 25dce66483
commit 438f6a866b
7 changed files with 179 additions and 141 deletions
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16
arch/arm/src/samd5e5/Kconfig
View File

@ -337,6 +337,10 @@ config SAMD5E5_HAVE_TC7
bool
default n
config SAMD5E5_SERCOM
bool
default n
config SAMD5E5_AC
bool "Analog Comparator"
default n
@ -376,35 +380,43 @@ config SAMD5E5_RTC
config SAMD5E5_SERCOM0
bool "Serial Communication Interface 0"
default n
select SAMD5E5_SERCOM
config SAMD5E5_SERCOM1
bool "Serial Communication Interface 1"
default n
select SAMD5E5_SERCOM
config SAMD5E5_SERCOM2
bool "Serial Communication Interface 2"
default n
select SAMD5E5_SERCOM
config SAMD5E5_SERCOM3
bool "Serial Communication Interface 3"
default n
select SAMD5E5_SERCOM
config SAMD5E5_SERCOM4
bool "Serial Communication Interface 4"
default n
select SAMD5E5_SERCOM
config SAMD5E5_SERCOM5
bool "Serial Communication Interface 5"
default n
select SAMD5E5_SERCOM
config SAMD5E5_SERCOM6
bool "Serial Communication Interface 6"
default n
select SAMD5E5_SERCOM
depends on SAMD5E5_HAVE_SERCOM6
config SAMD5E5_SERCOM7
bool "Serial Communication Interface 7"
default n
select SAMD5E5_SERCOM
depends on SAMD5E5_HAVE_SERCOM7
config SAMD5E5_TC0
@ -471,6 +483,9 @@ config SAMD5E5_DMAC_NDESC
Each additional DMA descriptor will require 16-bytes for LPRAM
memory.
menu "SERCOM Configuration"
depends on SAMD5E5_SERCOM
choice
prompt "SERCOM0 mode"
default SAMD5E5_SERCOM0_ISUSART
@ -630,6 +645,7 @@ config SAMD5E5_SERCOM7_ISUSART
select USART7_SERIALDRIVER
endchoice
endmenu # SERCOM Configuration
config SAMD5E5_HAVE_SPI
bool

7
arch/arm/src/samd5e5/Make.defs
View File

@ -88,8 +88,7 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_gclk.c sam_irq.c
CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_sercom.c sam_start.c
CHIP_CSRCS += sam_usart.c
CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c sam_usart.c
# Configuration-dependent SAMD5x/E5x files
@ -97,6 +96,10 @@ ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_timerisr.c
endif
ifeq ($(CONFIG_SAMD5E5_SERCOM),y)
CHIP_CSRCS += sam_sercom.c
endif
ifeq ($(CONFIG_SAMD5E5_TC),y)
CHIP_CSRCS += sam_tc.c

3
arch/arm/src/samd5e5/sam_lowputc.c
View File

@ -292,7 +292,8 @@ int sam_usart_internal(const struct sam_usart_config_s * const config)
/* Configure the GCLKs for the SERCOM module */
sercom_coreclk_configure(config->sercom, config->coregen, false);
sercom_coreclk_configure(config->sercom, config->coregen,
(bool)config->corelock);
sercom_slowclk_configure(config->sercom, config->slowgen);
/* Set USART configuration according to the board configuration */

3
arch/arm/src/samd5e5/sam_sercom.c
View File

@ -202,7 +202,8 @@ void sercom_slowclk_configure(int sercom, int slowgen)
* of SERCOM modules and, hence, only need to configured once.
*/
sam_gclk_chan_enable(GCLK_CHAN_SERCOMn_SLOW, slowgen, true);
sam_gclk_chan_enable(GCLK_CHAN_SERCOMn_SLOW, slowgen,
BOARD_SERCOM_SLOWLOCK);
/* The slow clock is now configured and should not be re=configured
* again.

24
arch/arm/src/samd5e5/sam_usart.c
View File

@ -70,8 +70,9 @@ const struct sam_usart_config_s g_usart0config =
.txirq = BOARD_TXIRQ_SERCOM0,
.rxirq = BOARD_RXIRQ_SERCOM0,
.coregen = BOARD_SERCOM0_COREGEN,
.slowgen = BOARD_SERCOM0_SLOWGEN,
.slowgen = BOARD_SERCOM_SLOWGEN,
.stopbits2 = CONFIG_USART0_2STOP,
.corelock = BOARD_SERCOM0_CORELOCK,
.baud = CONFIG_USART0_BAUD,
.pad0 = BOARD_SERCOM0_PINMAP_PAD0,
.pad1 = BOARD_SERCOM0_PINMAP_PAD1,
@ -92,8 +93,9 @@ const struct sam_usart_config_s g_usart1config =
.txirq = BOARD_TXIRQ_SERCOM1,
.rxirq = BOARD_RXIRQ_SERCOM1,
.coregen = BOARD_SERCOM1_COREGEN,
.slowgen = BOARD_SERCOM1_SLOWGEN,
.slowgen = BOARD_SERCOM_SLOWGEN,
.stopbits2 = CONFIG_USART1_2STOP,
.corelock = BOARD_SERCOM1_CORELOCK,
.baud = CONFIG_USART1_BAUD,
.pad0 = BOARD_SERCOM1_PINMAP_PAD0,
.pad1 = BOARD_SERCOM1_PINMAP_PAD1,
@ -114,8 +116,9 @@ const struct sam_usart_config_s g_usart2config =
.txirq = BOARD_TXIRQ_SERCOM2,
.rxirq = BOARD_RXIRQ_SERCOM2,
.coregen = BOARD_SERCOM2_COREGEN,
.slowgen = BOARD_SERCOM2_SLOWGEN,
.slowgen = BOARD_SERCOM_SLOWGEN,
.stopbits2 = CONFIG_USART2_2STOP,
.corelock = BOARD_SERCOM2_CORELOCK,
.baud = CONFIG_USART2_BAUD,
.pad0 = BOARD_SERCOM2_PINMAP_PAD0,
.pad1 = BOARD_SERCOM2_PINMAP_PAD1,
@ -136,8 +139,9 @@ const struct sam_usart_config_s g_usart3config =
.txirq = BOARD_TXIRQ_SERCOM3,
.rxirq = BOARD_RXIRQ_SERCOM3,
.coregen = BOARD_SERCOM3_COREGEN,
.slowgen = BOARD_SERCOM3_SLOWGEN,
.slowgen = BOARD_SERCOM_SLOWGEN,
.stopbits2 = CONFIG_USART3_2STOP,
.corelock = BOARD_SERCOM3_CORELOCK,
.baud = CONFIG_USART3_BAUD,
.pad0 = BOARD_SERCOM3_PINMAP_PAD0,
.pad1 = BOARD_SERCOM3_PINMAP_PAD1,
@ -158,8 +162,9 @@ const struct sam_usart_config_s g_usart4config =
.txirq = BOARD_TXIRQ_SERCOM4,
.rxirq = BOARD_RXIRQ_SERCOM4,
.coregen = BOARD_SERCOM4_COREGEN,
.slowgen = BOARD_SERCOM4_SLOWGEN,
.slowgen = BOARD_SERCOM_SLOWGEN,
.stopbits2 = CONFIG_USART4_2STOP,
.corelock = BOARD_SERCOM4_CORELOCK,
.baud = CONFIG_USART4_BAUD,
.pad0 = BOARD_SERCOM4_PINMAP_PAD0,
.pad1 = BOARD_SERCOM4_PINMAP_PAD1,
@ -180,8 +185,9 @@ const struct sam_usart_config_s g_usart5config =
.txirq = BOARD_TXIRQ_SERCOM5,
.rxirq = BOARD_RXIRQ_SERCOM5,
.coregen = BOARD_SERCOM5_COREGEN,
.slowgen = BOARD_SERCOM5_SLOWGEN,
.slowgen = BOARD_SERCOM_SLOWGEN,
.stopbits2 = CONFIG_USART5_2STOP,
.corelock = BOARD_SERCOM5_CORELOCK,
.baud = CONFIG_USART5_BAUD,
.pad0 = BOARD_SERCOM5_PINMAP_PAD0,
.pad1 = BOARD_SERCOM5_PINMAP_PAD1,
@ -202,8 +208,9 @@ const struct sam_usart_config_s g_usart6config =
.txirq = BOARD_TXIRQ_SERCOM6,
.rxirq = BOARD_RXIRQ_SERCOM6,
.coregen = BOARD_SERCOM6_COREGEN,
.slowgen = BOARD_SERCOM6_SLOWGEN,
.slowgen = BOARD_SERCOM_SLOWGEN,
.stopbits2 = CONFIG_USART6_2STOP,
.corelock = BOARD_SERCOM6_CORELOCK,
.baud = CONFIG_USART6_BAUD,
.pad0 = BOARD_SERCOM6_PINMAP_PAD0,
.pad1 = BOARD_SERCOM6_PINMAP_PAD1,
@ -224,8 +231,9 @@ const struct sam_usart_config_s g_usart7config =
.txirq = BOARD_TXIRQ_SERCOM7,
.rxirq = BOARD_RXIRQ_SERCOM7,
.coregen = BOARD_SERCOM7_COREGEN,
.slowgen = BOARD_SERCOM7_SLOWGEN,
.slowgen = BOARD_SERCOM_SLOWGEN,
.stopbits2 = CONFIG_USART7_2STOP,
.corelock = BOARD_SERCOM7_CORELOCK,
.baud = CONFIG_USART7_BAUD,
.pad0 = BOARD_SERCOM7_PINMAP_PAD0,
.pad1 = BOARD_SERCOM7_PINMAP_PAD1,

4
arch/arm/src/samd5e5/sam_usart.h
View File

@ -56,6 +56,7 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Pick the console USART configuration */
#if defined(CONFIG_USART0_SERIAL_CONSOLE)
@ -92,7 +93,8 @@ struct sam_usart_config_s
uint8_t rxirq; /* Rx SERCOM IRQ number */
uint8_t coregen; /* Core GCLK generator */
uint8_t slowgen; /* Slow GCLK generator */
bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
uint8_t stopbits2 : 1; /* True: Configure with 2 stop bits instead of 1 */
uint8_t corelock : 1; /* True: Lock the CORE clock */
uint32_t baud; /* Configured baud */
port_pinset_t pad0; /* Pin configuration for PAD0 */
port_pinset_t pad1; /* Pin configuration for PAD1 */

233
configs/metro-m4/include/board.h
View File

@ -42,15 +42,18 @@
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#ifndef TRUE
# define TRUE 1
#endif
#ifndef FALSE
# define FALSE 0
#endif
/* Clocking *************************************************************************/
/* Overview
*
@ -99,16 +102,16 @@
/* XOSC32 */
#define BOARD_HAVE_XOSC32K 1 /* 32.768 KHz XOSC32 crystal installed */
#define BOARD_XOSC32K_ENABLE true /* Enable XOSC32 */
#define BOARD_XOSC32K_XTALEN false /* External clock connected on XIN32 */
#define BOARD_XOSC32K_EN32K false /* No 32KHz output */
#define BOARD_XOSC32K_EN1K false /* No 1KHz output */
#define BOARD_XOSC32K_HIGHSPEED true /* High speed mode */
#define BOARD_XOSC32K_RUNSTDBY false /* Don't run in standby */
#define BOARD_XOSC32K_ONDEMAND true /* Enable on-demand control */
#define BOARD_XOSC32K_CFDEN false /* Clock failure detector not enabled */
#define BOARD_XOSC32K_CFDEO false /* No clock failure event */
#define BOARD_XOSC32K_CALIBEN false /* No OSCULP32K calibration */
#define BOARD_XOSC32K_ENABLE TRUE /* Enable XOSC32 */
#define BOARD_XOSC32K_XTALEN TRUE /* Crystal connected on XIN32 */
#define BOARD_XOSC32K_EN32K FALSE /* No 32KHz output */
#define BOARD_XOSC32K_EN1K FALSE /* No 1KHz output */
#define BOARD_XOSC32K_HIGHSPEED TRUE /* High speed mode */
#define BOARD_XOSC32K_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_XOSC32K_ONDEMAND TRUE /* Enable on-demand control */
#define BOARD_XOSC32K_CFDEN FALSE /* Clock failure detector not enabled */
#define BOARD_XOSC32K_CFDEO FALSE /* No clock failure event */
#define BOARD_XOSC32K_CALIBEN FALSE /* No OSCULP32K calibration */
#define BOARD_XOSC32K_STARTUP 0 /* Startup time: 62592us */
#define BOARD_XOSC32K_CALIB 0 /* Dummy OSCULP32K calibration value */
#define BOARD_XOSC32K_RTCSEL 0 /* RTC clock = ULP1K */
@ -116,27 +119,27 @@
/* XOSC0 */
#define BOARD_HAVE_XOSC0 0 /* No XOSC0 clock/crystal installed */
#define BOARD_XOSC0_ENABLE false /* Don't enable XOSC0 */
#define BOARD_XOSC0_XTALEN false /* External clock connected */
#define BOARD_XOSC0_RUNSTDBY false /* Don't run in standby */
#define BOARD_XOSC0_ONDEMAND true /* Disable on-demand control */
#define BOARD_XOSC0_LOWGAIN false /* Disable low buffer gain */
#define BOARD_XOSC0_ENALC false /* Disable automatic loop control */
#define BOARD_XOSC0_CFDEN false /* Clock failure detector not enabled */
#define BOARD_XOSC0_SWBEN false /* XOSC clock switch not enabled */
#define BOARD_XOSC0_ENABLE FALSE /* Don't enable XOSC0 */
#define BOARD_XOSC0_XTALEN FALSE /* External clock connected */
#define BOARD_XOSC0_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_XOSC0_ONDEMAND TRUE /* Disable on-demand control */
#define BOARD_XOSC0_LOWGAIN FALSE /* Disable low buffer gain */
#define BOARD_XOSC0_ENALC FALSE /* Disable automatic loop control */
#define BOARD_XOSC0_CFDEN FALSE /* Clock failure detector not enabled */
#define BOARD_XOSC0_SWBEN FALSE /* XOSC clock switch not enabled */
#define BOARD_XOSC0_STARTUP 0 /* XOSC0 start-up time 31µs */
/* XOSC1 */
#define BOARD_HAVE_XOSC1 0 /* No XOSC0 clock/crystal installed */
#define BOARD_XOSC1_ENABLE false /* Don't enable XOSC1 */
#define BOARD_XOSC1_XTALEN true /* External crystal connected */
#define BOARD_XOSC1_RUNSTDBY false /* Don't run in standby */
#define BOARD_XOSC1_ONDEMAND true /* Disable on-demand control */
#define BOARD_XOSC1_LOWGAIN false /* Disable low buffer gain */
#define BOARD_XOSC1_ENALC false /* Disable automatic loop control */
#define BOARD_XOSC1_CFDEN false /* Clock failure detector not enabled */
#define BOARD_XOSC1_SWBEN false /* XOSC clock switch not enabled */
#define BOARD_XOSC1_ENABLE FALSE /* Don't enable XOSC1 */
#define BOARD_XOSC1_XTALEN TRUE /* External crystal connected */
#define BOARD_XOSC1_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_XOSC1_ONDEMAND TRUE /* Disable on-demand control */
#define BOARD_XOSC1_LOWGAIN FALSE /* Disable low buffer gain */
#define BOARD_XOSC1_ENALC FALSE /* Disable automatic loop control */
#define BOARD_XOSC1_CFDEN FALSE /* Clock failure detector not enabled */
#define BOARD_XOSC1_SWBEN FALSE /* XOSC clock switch not enabled */
#define BOARD_XOSC1_STARTUP 0 /* XOSC0 start-up time 31µs */
/* GCLK */
@ -144,108 +147,108 @@
#define BOARD_GCLK_SET1 0x0020 /* Pre-configure: GCLK5 needed by DPLL0 */
#define BOARD_GCLK_SET2 0x0fdf /* Post-configure: All GCLKs except GCLK5 */
#define BOARD_GCLK0_ENABLE true /* Enable GCLK0 */
#define BOARD_GCLK0_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK0_OOV false /* Clock output will be LOW */
#define BOARD_GCLK0_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK0_ENABLE TRUE /* Enable GCLK0 */
#define BOARD_GCLK0_IDC FALSE /* Don't improve duty cycle */
#define BOARD_GCLK0_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK0_OE TRUE /* Generate output on GCLK_IO */
#define BOARD_GCLK0_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK0_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK0_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK0_SOURCE 7 /* Select DPLL0 output as GCLK0 source */
#define BOARD_GCLK0_DIV 1 /* Division factor */
#define BOARD_GCLK1_ENABLE true /* Enable GCLK1 */
#define BOARD_GCLK1_OOV false /* Clock output will be LOW */
#define BOARD_GCLK1_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK1_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK1_ENABLE TRUE /* Enable GCLK1 */
#define BOARD_GCLK1_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK1_OE TRUE /* Generate output on GCLK_IO */
#define BOARD_GCLK1_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GCLK1 source */
#define BOARD_GCLK1_DIV 1 /* Division factor */
#define BOARD_GCLK2_ENABLE false /* Don't enable GCLK2 */
#define BOARD_GCLK2_OOV false /* Clock output will be LOW */
#define BOARD_GCLK2_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK2_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK2_ENABLE FALSE /* Don't enable GCLK2 */
#define BOARD_GCLK2_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK2_OE FALSE /* No generator output of GCLK_IO */
#define BOARD_GCLK2_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK2_SOURCE 5 /* Select XOSC32K as GCLK2 source */
#define BOARD_GCLK2_DIV 1 /* Division factor */
#define BOARD_GCLK3_ENABLE true /* Enable GCLK3 */
#define BOARD_GCLK3_OOV false /* Clock output will be LOW */
#define BOARD_GCLK3_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK3_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK3_ENABLE TRUE /* Enable GCLK3 */
#define BOARD_GCLK3_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK3_OE FALSE /* No generator output of GCLK_IO */
#define BOARD_GCLK3_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
#define BOARD_GCLK3_DIV 1 /* Division factor */
#define BOARD_GCLK4_ENABLE true /* Enable GCLK4 */
#define BOARD_GCLK4_OOV false /* Clock output will be LOW */
#define BOARD_GCLK4_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK4_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK4_ENABLE TRUE /* Enable GCLK4 */
#define BOARD_GCLK4_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK4_OE TRUE /* Generate output on GCLK_IO */
#define BOARD_GCLK4_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GCLK4 source */
#define BOARD_GCLK4_DIV 1 /* Division factor */
#define BOARD_GCLK5_ENABLE true /* Enable GCLK5 */
#define BOARD_GCLK5_OOV false /* Clock output will be LOW */
#define BOARD_GCLK5_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK5_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK5_ENABLE TRUE /* Enable GCLK5 */
#define BOARD_GCLK5_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK5_OE TRUE /* Generate output on GCLK_IO */
#define BOARD_GCLK5_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GCLK5 source */
#define BOARD_GCLK5_DIV 24 /* Division factor */
#define BOARD_GCLK6_ENABLE false /* Don't enable GCLK6 */
#define BOARD_GCLK6_OOV false /* Clock output will be LOW */
#define BOARD_GCLK6_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK6_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK6_ENABLE FALSE /* Don't enable GCLK6 */
#define BOARD_GCLK6_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK6_OE FALSE /* No generator output of GCLK_IO */
#define BOARD_GCLK6_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GCLK6 source */
#define BOARD_GCLK6_DIV 1 /* Division factor */
#define BOARD_GCLK7_ENABLE false /* Don't enable GCLK7 */
#define BOARD_GCLK7_OOV false /* Clock output will be LOW */
#define BOARD_GCLK7_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK7_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK7_ENABLE FALSE /* Don't enable GCLK7 */
#define BOARD_GCLK7_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK7_OE FALSE /* No generator output of GCLK_IO */
#define BOARD_GCLK7_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GCLK7 source */
#define BOARD_GCLK7_DIV 1 /* Division factor */
#define BOARD_GCLK8_ENABLE false /* Don't enable GCLK8 */
#define BOARD_GCLK8_OOV false /* Clock output will be LOW */
#define BOARD_GCLK8_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK8_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK8_ENABLE FALSE /* Don't enable GCLK8 */
#define BOARD_GCLK8_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK8_OE FALSE /* No generator output of GCLK_IO */
#define BOARD_GCLK8_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GCLK8 source */
#define BOARD_GCLK8_DIV 1 /* Division factor */
#define BOARD_GCLK9_ENABLE false /* Don't enable GCLK9 */
#define BOARD_GCLK9_OOV false /* Clock output will be LOW */
#define BOARD_GCLK9_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK9_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK9_ENABLE FALSE /* Don't enable GCLK9 */
#define BOARD_GCLK9_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK9_OE FALSE /* No generator output of GCLK_IO */
#define BOARD_GCLK9_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GCLK9 source */
#define BOARD_GCLK9_DIV 1 /* Division factor */
#define BOARD_GCLK10_ENABLE false /* Don't enable GCLK10 */
#define BOARD_GCLK10_OOV false /* Clock output will be LOW */
#define BOARD_GCLK10_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK10_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK10_ENABLE FALSE /* Don't enable GCLK10 */
#define BOARD_GCLK10_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK10_OE FALSE /* No generator output of GCLK_IO */
#define BOARD_GCLK10_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GCLK10 source */
#define BOARD_GCLK10_DIV 1 /* Division factor */
#define BOARD_GCLK11_ENABLE false /* Don't enable GCLK11 */
#define BOARD_GCLK11_OOV false /* Clock output will be LOW */
#define BOARD_GCLK11_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK11_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK11_ENABLE FALSE /* Don't enable GCLK11 */
#define BOARD_GCLK11_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK11_OE FALSE /* No generator output of GCLK_IO */
#define BOARD_GCLK11_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GCLK11 source */
#define BOARD_GCLK11_DIV 1 /* Division factor */
#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY
/* FDLL */
#define BOARD_DFLL_ENABLE true /* DFLL enable */
#define BOARD_DFLL_RUNSTDBY false /* Don't run in standby */
#define BOARD_DFLL_ONDEMAND false /* No n-demand control */
#define BOARD_DFLL_MODE false /* Open loop mode */
#define BOARD_DFLL_STABLE false /* No stable DFLL frequency */
#define BOARD_DFLL_LLAW false /* Don't ose lock after wake */
#define BOARD_DFLL_USBCRM true /* Use USB clock recovery mode */
#define BOARD_DFLL_CCDIS true /* Chill cycle disable */
#define BOARD_DFLL_QLDIS false /* No Quick Lock Disable */
#define BOARD_DFLL_BPLCKC false /* No ypass coarse clock */
#define BOARD_DFLL_WAITLOCK true /* Wait lock */
#define BOARD_DFLL_CALIBEN false /* Don't verwrite factory calibration */
#define BOARD_DFLL_GCLKLOCK false /* Don't lock the GCLK source */
#define BOARD_DFLL_ENABLE TRUE /* DFLL enable */
#define BOARD_DFLL_RUNSTDBY FALSE /* Don't run in standby */
#define BOARD_DFLL_ONDEMAND FALSE /* No n-demand control */
#define BOARD_DFLL_MODE FALSE /* Open loop mode */
#define BOARD_DFLL_STABLE FALSE /* No stable DFLL frequency */
#define BOARD_DFLL_LLAW FALSE /* Don't ose lock after wake */
#define BOARD_DFLL_USBCRM TRUE /* Use USB clock recovery mode */
#define BOARD_DFLL_CCDIS TRUE /* Chill cycle disable */
#define BOARD_DFLL_QLDIS FALSE /* No Quick Lock Disable */
#define BOARD_DFLL_BPLCKC FALSE /* No ypass coarse clock */
#define BOARD_DFLL_WAITLOCK TRUE /* Wait lock */
#define BOARD_DFLL_CALIBEN FALSE /* Don't verwrite factory calibration */
#define BOARD_DFLL_GCLKLOCK FALSE /* Don't lock the GCLK source */
#define BOARD_DFLL_FCALIB 128 /* Coarse calibration value (if caliben) */
#define BOARD_DFLL_CCALIB (31 / 4) /* Fine calibration value (if caliben) */
#define BOARD_DFLL_FSTEP 1 /* Fine maximum step */
@ -274,13 +277,13 @@
* Fdpll = 32768 * (1463 + 1 + 13/32) = 47.986 MHz
*/
#define BOARD_DPLL0_ENABLE true /* DPLL enable */
#define BOARD_DPLL0_DCOEN false /* DCO filter enable */
#define BOARD_DPLL0_LBYPASS false /* Lock bypass */
#define BOARD_DPLL0_WUF false /* Wake up fast */
#define BOARD_DPLL0_RUNSTDBY false /* Run in standby */
#define BOARD_DPLL0_ONDEMAND false /* On demand clock activation */
#define BOARD_DPLL0_REFLOCK false /* Do not lock reference clock section */
#define BOARD_DPLL0_ENABLE TRUE /* DPLL enable */
#define BOARD_DPLL0_DCOEN FALSE /* DCO filter enable */
#define BOARD_DPLL0_LBYPASS FALSE /* Lock bypass */
#define BOARD_DPLL0_WUF FALSE /* Wake up fast */
#define BOARD_DPLL0_RUNSTDBY FALSE /* Run in standby */
#define BOARD_DPLL0_ONDEMAND FALSE /* On demand clock activation */
#define BOARD_DPLL0_REFLOCK FALSE /* Do not lock reference clock section */
#define BOARD_DPLL0_REFCLK 0 /* Reference clock selection */
#define BOARD_DPLL0_LTIME 0 /* Lock time */
#define BOARD_DPLL0_FILTER 0 /* Proportional integer filter selection */
@ -291,13 +294,13 @@
#define BOARD_DPLL0_LDRINT 59 /* Loop divider ratio */
#define BOARD_DPLL0_DIV 0 /* Clock divider */
#define BOARD_DPLL1_ENABLE false /* DPLL enable */
#define BOARD_DPLL1_DCOEN false /* DCO filter enable */
#define BOARD_DPLL1_LBYPASS false /* Lock bypass */
#define BOARD_DPLL1_WUF false /* Wake up fast */
#define BOARD_DPLL1_RUNSTDBY false /* Run in standby */
#define BOARD_DPLL1_ONDEMAND false /* On demand clock activation */
#define BOARD_DPLL1_REFLOCK false /* Do not lock reference clock section */
#define BOARD_DPLL1_ENABLE FALSE /* DPLL enable */
#define BOARD_DPLL1_DCOEN FALSE /* DCO filter enable */
#define BOARD_DPLL1_LBYPASS FALSE /* Lock bypass */
#define BOARD_DPLL1_WUF FALSE /* Wake up fast */
#define BOARD_DPLL1_RUNSTDBY FALSE /* Run in standby */
#define BOARD_DPLL1_ONDEMAND FALSE /* On demand clock activation */
#define BOARD_DPLL1_REFLOCK FALSE /* Do not lock reference clock section */
#define BOARD_DPLL1_REFCLK 1 /* Reference clock = XOSCK32 */
#define BOARD_DPLL1_LTIME 0 /* Lock time */
#define BOARD_DPLL1_FILTER 0 /* Sigma-delta DCO filter selection */
@ -391,15 +394,19 @@
/* SERCOM definitions ***************************************************************/
/* The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main
* Clock Controller. The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and
* GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the
* SERCOM while working as a master. The slow clock (GCLK_SERCOMx_SLOW) is only
* required for certain functions.
* Clock Controller. The SERCOM uses two generic clocks: GCLK_SERCOMn_CORE and
* GCLK_SERCOM_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the
* SERCOM while working as a master. The slow clock (GCLK_SERCOM_SLOW) is only
* required for certain functions and is common to all SERCOM modules.
*
* These clocks must be configured and enabled in the Generic Clock Controller (GCLK)
* before using the SERCOM.
*/
#define BOARD_SERCOM_SLOWGEN 3 /* 48MHz, common to all SERCOMS */
#define BOARD_SERCOM_SLOWLOCK FALSE /* Don't lock the SLOWCLOCK */
#define BOARD_SLOWCLOCK_FREQUENCY BOARD_GCLK3_FREQUENCY
/* SERCOM3
*
* An Arduino compatible serial Shield is assumed (or equivalently, an external
@ -425,8 +432,8 @@
#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0
#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_1
#define BOARD_SERCOM3_COREGEN 1 /* 48MHz, common to all SERCOMS */
#define BOARD_SERCOM3_SLOWGEN 3 /* 48MHz */
#define BOARD_SERCOM3_COREGEN 1 /* 48MHz Core clock */
#define BOARD_SERCOM3_CORELOCK FALSE /* Don't lock the CORECLOCK */
#define BOARD_SERCOM3_FREQUENCY BOARD_GCLK1_FREQUENCY
/* USB */