arch/arm/src/stm32f7/stm32_ethernet.c: Add some delays so that ifup() does not hog the CPU.
This commit is contained in:
David Sidrane
Gregory Nutt
parent
f410d9711a
commit
43a6e43a0f
@ -53,6 +53,7 @@
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#include <nuttx/irq.h>
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#include <nuttx/wdog.h>
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#include <nuttx/wqueue.h>
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#include <nuttx/signal.h>
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#include <nuttx/net/mii.h>
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#include <nuttx/net/arp.h>
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#include <nuttx/net/netdev.h>
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@ -278,6 +279,7 @@
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#endif
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/* Clocking *****************************************************************/
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/* Set MACMIIAR CR bits depending on HCLK setting */
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#if STM32_HCLK_FREQUENCY >= 20000000 && STM32_HCLK_FREQUENCY < 35000000
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@ -295,6 +297,7 @@
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#endif
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/* Timing *******************************************************************/
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/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
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* second
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*/
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@ -314,7 +317,7 @@
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#define PHY_READ_TIMEOUT (0x0004ffff)
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#define PHY_WRITE_TIMEOUT (0x0004ffff)
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#define PHY_RETRY_TIMEOUT (0x0004ffff)
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#define PHY_RETRY_TIMEOUT (0x00000ccc)
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/* MAC reset ready delays in loop counts */
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@ -556,6 +559,7 @@
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#endif
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/* Interrupt bit sets *******************************************************/
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/* All interrupts in the normal and abnormal interrupt summary. Early transmit
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* interrupt (ETI) is excluded from the abnormal set because it causes too
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* many interrupts and is not interesting.
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@ -582,6 +586,7 @@
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#endif
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/* Helpers ******************************************************************/
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/* This is a helper pointer for accessing the contents of the Ethernet
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* header
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*/
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@ -591,6 +596,7 @@
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This union type forces the allocated size of RX descriptors to be the
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* padded to a exact multiple of the Cortex-M7 D-Cache line size.
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*/
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@ -675,6 +681,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32F7_NETHERNET];
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Register operations ******************************************************/
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#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG
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@ -786,6 +793,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv);
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_getreg
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*
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@ -840,7 +848,7 @@ static uint32_t stm32_getreg(uint32_t addr)
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{
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/* Yes.. then show how many times the value repeated */
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ninfo("[repeats %d more times]\n", count-3);
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ninfo("[repeats %d more times]\n", count - 3);
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}
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/* Save the new address, value, and count */
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@ -1086,7 +1094,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
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{
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/* Yes... how many buffers will be need to send the packet? */
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bufcount = (priv->dev.d_len + (ALIGNED_BUFSIZE-1)) / ALIGNED_BUFSIZE;
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bufcount = (priv->dev.d_len + (ALIGNED_BUFSIZE - 1)) / ALIGNED_BUFSIZE;
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lastsize = priv->dev.d_len - (bufcount - 1) * ALIGNED_BUFSIZE;
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ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
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@ -1111,7 +1119,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
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/* Set the buffer size in all TX descriptors */
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if (i == (bufcount-1))
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if (i == (bufcount - 1))
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{
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/* This is the last segment. Set the last segment bit in the
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* last TX descriptor and ask for an interrupt when this
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@ -2634,6 +2642,7 @@ static uint32_t stm32_calcethcrc(const uint8_t *data, size_t length)
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if (((crc >> 31) ^ (data[i] >> j)) & 0x01)
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{
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/* x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
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crc = (crc << 1) ^ 0x04c11db7;
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}
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else
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@ -2680,7 +2689,7 @@ static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac)
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crc = stm32_calcethcrc(mac, 6);
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hashindex = (crc >> 26) & 0x3F;
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hashindex = (crc >> 26) & 0x3f;
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if (hashindex > 31)
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{
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@ -2737,7 +2746,7 @@ static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac)
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crc = stm32_calcethcrc(mac, 6);
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hashindex = (crc >> 26) & 0x3F;
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hashindex = (crc >> 26) & 0x3f;
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if (hashindex > 31)
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{
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@ -2803,8 +2812,8 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv,
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* transfers.
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*/
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priv->txtail = NULL;
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priv->inflight = 0;
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priv->txtail = NULL;
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priv->inflight = 0;
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/* Initialize each TX descriptor */
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@ -2830,13 +2839,13 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv,
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/* Initialize the next descriptor with the Next Descriptor Polling Enable */
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if (i < (CONFIG_STM32F7_ETH_NTXDESC-1))
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if (i < (CONFIG_STM32F7_ETH_NTXDESC - 1))
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{
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/* Set next descriptor address register with next descriptor base
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* address
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*/
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txdesc->tdes3 = (uint32_t)&txtable[i+1].txdesc;
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txdesc->tdes3 = (uint32_t)&txtable[i + 1].txdesc;
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}
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else
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{
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@ -2920,13 +2929,13 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
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/* Initialize the next descriptor with the Next Descriptor Polling Enable */
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if (i < (CONFIG_STM32F7_ETH_NRXDESC-1))
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if (i < (CONFIG_STM32F7_ETH_NRXDESC - 1))
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{
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/* Set next descriptor address register with next descriptor base
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* address
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*/
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rxdesc->rdes3 = (uint32_t)&rxtable[i+1].rxdesc;
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rxdesc->rdes3 = (uint32_t)&rxtable[i + 1].rxdesc;
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}
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else
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{
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@ -3287,6 +3296,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
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nerr("ERROR: Failed to reset the PHY: %d\n", ret);
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return ret;
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}
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up_mdelay(PHY_RESET_DELAY);
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/* Perform any necessary, board-specific PHY initialization */
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@ -3327,6 +3337,8 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
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{
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break;
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}
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nxsig_usleep(100);
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}
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if (timeout >= PHY_RETRY_TIMEOUT)
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@ -3358,6 +3370,8 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
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{
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break;
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}
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nxsig_usleep(100);
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}
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if (timeout >= PHY_RETRY_TIMEOUT)
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@ -3787,6 +3801,7 @@ static int stm32_macconfig(struct stm32_ethmac_s *priv)
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stm32_putreg(0, STM32_ETH_MACVLANTR);
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/* DMA Configuration */
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/* Set up the DMAOMR register */
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regval = stm32_getreg(STM32_ETH_DMAOMR);
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