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XTENSA: Add some interrupt controls

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This commit is contained in:
Gregory Nutt 2016-10-15 11:29:50 -06:00
parent 0be3d12ba0
commit 43d08db1a0
3 changed files with 410 additions and 0 deletions
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148
arch/xtensa/src/common/xtensa_irq.S Normal file
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/****************************************************************************
* arch/xtensa/src/common/xtensa_irq.S
*
* Adapted from use in NuttX by:
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Derives from logic originally provided by Cadence Design Systems Inc.
*
* Copyright (c) 2006-2015 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "xtensa_specregs.h"
#include "xtensa_macros.h"
#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS
/****************************************************************************
* Public Data
****************************************************************************/
/* INTENABLE virtualization information. */
.data
.global _xtensa_intdata
.align 8
_xtensa_intdata:
.global _xtensa_intenable
.type _xtensa_intenable, @object
_xtensa_intenable:
.word 0 /* Virtual INTENABLE */
.size _xtensa_intenable,4
.global _xtensa_vprimask
.type _xtensa_vprimask, @object
_xtensa_vprimask:
.word 0xffffffff /* Virtual priority mask */
.size _xtensa_vprimask, 4
#endif /* XCHAL_HAVE_INTERRUPTS */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* C Prototype:
* irqstate_t xtensa_enable_interrupts(irqstate_t mask)
*
* Description:
* Enables a set of interrupts. Does not simply set INTENABLE directly,
* but computes it as a function of the current virtual priority.
* Can be called from interrupt handlers.
*
****************************************************************************/
.text
.align 4
.global xtensa_enable_interrupts
.type xtensa_enable_interrupts, @function
xtensa_enable_interrupts:
ENTRY0
#if XCHAL_HAVE_INTERRUPTS
movi a3, 0
movi a4, _xtensa_intdata
xsr a3, INTENABLE /* Disables all interrupts */
rsync
l32i a3, a4, 0 /* a3 = _xtensa_intenable */
l32i a6, a4, 4 /* a6 = _xtensa_vprimask */
or a5, a3, a2 /* a5 = _xtensa_intenable | mask */
s32i a5, a4, 0 /* _xtensa_intenable |= mask */
and a5, a5, a6 /* a5 = _xtensa_intenable & _xtensa_vprimask */
wsr a5, INTENABLE /* Reenable interrupts */
mov a2, a3 /* Previous mask */
#else
movi a2, 0 /* Return zero */
#endif
RET0
.size xtensa_enable_interrupts, . - xtensa_enable_interrupts
/****************************************************************************
* C Prototype:
* irqstate_t xtensa_disable_interrupts(irqstate_t mask)
*
* Description:
* Disables a set of interrupts. Does not simply set INTENABLE directly,
* but computes it as a function of the current virtual priority.
* Can be called from interrupt handlers.
*
****************************************************************************/
.text
.align 4
.global xtensa_disable_interrupts
.type xtensa_disable_interrupts,@function
xtensa_disable_interrupts:
ENTRY0
#if XCHAL_HAVE_INTERRUPTS
movi a3, 0
movi a4, _xtensa_intdata
xsr a3, INTENABLE /* Disables all interrupts */
rsync
l32i a3, a4, 0 /* a3 = _xtensa_intenable */
l32i a6, a4, 4 /* a6 = _xtensa_vprimask */
or a5, a3, a2 /* a5 = _xtensa_intenable | mask */
xor a5, a5, a2 /* a5 = _xtensa_intenable & ~mask */
s32i a5, a4, 0 /* _xtensa_intenable &= ~mask */
and a5, a5, a6 /* a5 = _xtensa_intenable & _xtensa_vprimask */
wsr a5, INTENABLE /* Reenable interrupts */
mov a2, a3 /* Previous mask */
#else
movi a2, 0 /* return zero */
#endif
RET0
.size xtensa_disable_interrupts, . - xtensa_disable_interrupts

108
arch/xtensa/src/common/xtensa_macros.h Normal file
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/****************************************************************************
* arch/xtensa/src/common/xtensa_macros.h
*
* Adapted from use in NuttX by:
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Derives from logic originally provided by Cadence Design Systems Inc.
*
* Copyright (c) 2006-2015 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
#ifdef __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H
#define __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H 1
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Assembly Language Macros
****************************************************************************/
#ifdef __ASSEMBLY__
/* Macro to get the current core ID. Only uses the reg given as an argument.
* Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO
* processor and 0xabab on the APP CPU. We distinguish between the two by
* simply checking bit 1: it's 1 on the APP and 0 on the PRO processor.
*/
.macro getcoreid reg
rsr.prid \reg
bbci \reg,1,1f
movi \reg,1
j 2f
1:
movi \reg,0
2:
.endm
/* Macros to handle ABI specifics of function entry and return.
*
* Convenient where the frame size requirements are the same for both ABIs.
* ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
* ENTRY0, RET0 are for frameless functions (no locals, no calls).
*
* where size = size of stack frame in bytes (must be >0 and aligned to 16).
* For framed functions the frame is created and the return address saved at
* base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
* For frameless functions, there is no frame and return address remains in a0.
* Note: Because CPP macros expand to a single line, macros requiring multi-line
* expansions are implemented as assembler macros.
*/
#ifdef CONFIG_XTENSA_CALL0_ABI
/* Call0 */
.macro entry1 size=0x10
addi sp, sp, -\size
s32i a0, sp, 0
.endm
.macro ret1 size=0x10
l32i a0, sp, 0
addi sp, sp, \size
ret
.endm
# define ENTRY(sz) entry1 sz
# define ENTRY0
# define RET(sz) ret1 sz
# define RET0 ret
#else
/* Windowed */
# define ENTRY(sz) entry sp, sz
# define ENTRY0 entry sp, 0x10
# define RET(sz) retw
# define RET0 retw
#endif /* CONFIG_XTENSA_CALL0_ABI */
#endif /* __ASSEMBLY */
#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H */

154
arch/xtensa/src/common/xtensa_specregs.h Normal file
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/****************************************************************************
* arch/xtensa/src/common/xtensa_macros.h
* Xtensa Special Register symbolic names
*
* Adapted from use in NuttX by:
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Derives from logic originally provided by Tensilica Inc.
*
* Copyright (c) 2005-2011 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H
#define __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define LITBASE 5
#define SCOMPARE1 12
#define ACCLO 16
#define ACCHI 17
#define MR_0 32
#define MR_1 33
#define MR_2 34
#define MR_3 35
#define PREFCTL 40
#define WINDOWBASE 72
#define WINDOWSTART 73
#define PTEVADDR 83
#define RASID 90
#define ITLBCFG 91
#define DTLBCFG 92
#define IBREAKENABLE 96
#define MEMCTL 97
#define CACHEATTR 98
#define ATOMCTL 99
#define DDR 104
#define MECR 110
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define CONFIGID0 176
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define EPC_5 181
#define EPC_6 182
#define EPC_7 183
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EPS_5 197
#define EPS_6 198
#define EPS_7 199
#define CONFIGID1 208
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define EXCSAVE_5 213
#define EXCSAVE_6 214
#define EXCSAVE_7 215
#define CPENABLE 224
#define INTERRUPT 226
#define INTREAD INTERRUPT /* Alternate name for backward compatibility */
#define INTSET INTERRUPT /* Alternate name for backward compatibility */
#define INTCLEAR 227
#define INTENABLE 228
#define PS 230
#define VECBASE 231
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
#define MISC_REG_2 246
#define MISC_REG_3 247
/* Special cases (bases of special register series): */
#define MR 32
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
#define MISC_REG 244
/* Tensilica-defined user registers: */
#if 0
/*#define ... 21..24 */ /* (545CK) */
/*#define ... 140..143 */ /* (545CK) */
#define EXPSTATE 230 /* Diamond */
#define THREADPTR 231 /* threadptr option */
#define FCR 232 /* FPU */
#define FSR 233 /* FPU */
#define AE_OVF_SAR 240 /* HiFi2 */
#define AE_BITHEAD 241 /* HiFi2 */
#define AE_TS_FTS_BU_BP 242 /* HiFi2 */
#define AE_SD_NO 243 /* HiFi2 */
#define VSAR 240 /* VectraLX */
#define ROUND_LO 242 /* VectraLX */
#define ROUND_HI 243 /* VectraLX */
#define CBEGIN 246 /* VectraLX */
#define CEND 247 /* VectraLX */
#endif
#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H */