Flash layout, bootloader, paging fixes
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2321 42af7a65-404d-4744-a932-0658087f49c3
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README
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^^^^^^
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This README discusses issues unique to NuttX configurations for the
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Freescale DEMO9S12NE64 development board.
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This README discusses issues unique to NuttX configurations for the
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Freescale DEMO9S12NE64 development board.
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MC9S12NE64 Features
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^^^^^^^^^^^^^^^^^^^
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• 16-bit HCS12 core
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- HCS12 CPU
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- Upward compatible with M68HC11 instruction set
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- Interrupt stacking and programmer’s model identical to M68HC11
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- Instruction queue
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- Enhanced indexed addressing
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- Memory map and interface (MMC)
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- Interrupt control (INT)
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- Background debug mode (BDM)
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- Enhanced debug12 module, including breakpoints and change-of-flow
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trace buffer (DBG)
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- Multiplexed expansion bus interface (MEBI) - available only in
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112-pin package version
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• Wakeup interrupt inputs
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- Up to 21 port bits available for wakeup interrupt function with
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digital filtering
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• Memory
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- 64K bytes of FLASH EEPROM
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- 8K bytes of RAM
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• Analog-to-digital converter (ATD)
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- One 8-channel module with 10-bit resolution
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- External conversion trigger capability
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• Timer module (TIM)
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- 4-channel timer
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- Each channel configurable as either input capture or output
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compare
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- Simple PWM mode
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- Modulo reset of timer counter
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- 16-bit pulse accumulator
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- External event counting
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- Gated time accumulation
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• Serial interfaces
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- Two asynchronous serial communications interface (SCI)
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- One synchronous serial peripheral interface (SPI)
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- One inter-IC bus (IIC)
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• Ethernet Media access controller (EMAC)
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- IEEE 802.3 compliant
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- Medium-independent interface (MII)
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- Full-duplex and half-duplex modes
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- Flow control using pause frames
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- MII management function
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- Address recognition
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- Frames with broadcast address are always accepted or always
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rejected
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- Exact match for single 48-bit individual (unicast) address
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- Hash (64-bit hash) check of group (multicast) addresses
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- Promiscuous mode
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• Ethertype filter
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• Loopback mode
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• Two receive and one transmit Ethernet buffer interfaces
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• Ethernet 10/100 Mbps transceiver (EPHY)
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- IEEE 802.3 compliant
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- Digital adaptive equalization
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- Half-duplex and full-duplex
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- Auto-negotiation next page ability
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- Baseline wander (BLW) correction
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- 125-MHz clock generator and timing recovery
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- Integrated wave-shaping circuitry
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- Loopback modes
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• CRG (clock and reset generator module)
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- Windowed COP watchdog
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- Real-time interrupt
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- Clock monitor
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- Pierce oscillator
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- Phase-locked loop clock frequency multiplier
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- Limp home mode in absence of external clock
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- 25-MHz crystal oscillator reference clock
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• Operating frequency
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- 50 MHz equivalent to 25 MHz bus speed for single chip
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- 32 MHz equivalent to 16 MHz bus speed in expanded bus modes
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• Internal 2.5-V regulator
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- Supports an input voltage range from 3.3 V ± 5%
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- Low-power mode capability
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- Includes low-voltage reset (LVR) circuitry
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• 80-pin TQFP-EP or 112-pin LQFP package
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- Up to 70 I/O pins with 3.3 V input and drive capability (112-pin
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package)
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- Up to two dedicated 3.3 V input only lines (IRQ, XIRQ)
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• Development support
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- Single-wire background debug™ mode (BDM)
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- On-chip hardware breakpoints
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- Enhanced DBG debug features
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Development Environment
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^^^^^^^^^^^^^^^^^^^^^^^
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Either Linux or Cygwin on Windows can be used for the development environment.
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The source has been built only using the GNU toolchain (see below). Other
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toolchains will likely cause problems.
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Either Linux or Cygwin on Windows can be used for the development
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environment. The source has been built only using the GNU toolchain
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(see below). Other toolchains will likely cause problems.
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NuttX buildroot Toolchain
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^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -49,6 +135,61 @@ NuttX buildroot Toolchain
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detailed PLUS some special instructions that you will need to follow if you are
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building a Cortex-M3 toolchain for Cygwin under Windows.
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FreeScale HCS12 Serial Monitor
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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General:
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The NuttX HCS12 port is configured to use the Freescale HCS serial
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monitor. This monitor supports primitive debug commands that allow
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FLASH/EEPROM programming and debugging through an RS-232 serial
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interface. The serial monior is 2Kb in size and resides in FLASH at
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addresses 0xf800-0xffff. The monitor does not use any RAM other than
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the stack itself.
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AN2458
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The serial monitor is described in detail in Freescale Application
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Note AN2458.pdf.
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COP:
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The serial monitor uses the COP for the cold reset function and should
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not be used by the application without some precautions (see AN2458).
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Clocking:
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The serial monitor sets the operating frequency to 24 MHz. This is
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not altered by the NuttX start-up; doing so would interfere with the
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operation of the serial monitor.
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Memory Configuration:
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Registers:
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• Register space is located at 0x0000–0x03ff.
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FLASH:
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• FLASH memory is any address greater than 0x4000. All paged
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addresses are assumed to be FLASH memory.
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• Application code should exclude the 0xf780–0xff7f memory.
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SRAM:
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• RAM ends at 0x3FFF and builds down to the limit of the device’s
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available RAM.
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• The serial monitor's stack pointer is set to the end of RAM+1
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(0x4000).
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EEPROM:
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• EEPROM (if the target device has any) is limited to the available
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space between the registers and the RAM (0x0400–to start of RAM).
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External Devices:
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• External devices attached to the multiplexed external bus
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interface are not supported
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Serial Communications:
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The serial monitor uses RS-232 serial communications through SCI0 at
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115,200 baud. The monitor must have exclusive use of this interface.
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Access to the serial port is available through a monitor jump table.
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Interrrupts:
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The serial monitor redirects interrupt vectors to an unprotected
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portion of FLASH just before the protected monitor program
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(0xf780–0xf7fe). The monitor will automatically redirect vector
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programming operations to these user vectors. The user code should
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therefore keep the normal (non-monitor) vector locations
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(0xff80–0xfffe).
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HCS12/DEMO9S12NEC64-specific Configuration Options
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -34,16 +34,57 @@
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****************************************************************************/
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/* The DEMO9S12NE64 has 64Kb of FLASH and 8Kb of SRAM that are assumed to be
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* positioned as below:
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* paged and positioned as below:
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*/
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MEMORY
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{
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flash (rx) : ORIGIN = 0x0800, LENGTH = 64K
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sram (rwx) : ORIGIN = 0x3800, LENGTH = 8K
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/* The 8Kb SRAM is mapped to 0x2000-0x2fff. The top 256 bytes are reserved
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* for the serial monitor stack space.
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*/
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sram (rwx) : ORIGIN = 0x2000, LENGTH = 8K-256
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/* Two fixed text flash pages (corresponding to page 3e and 3f */
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lowtext(rx) : ORIGIN = 0x4000, LENGTH = 16K /* Page 3e */
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hitext (rx) : ORIGIN = 0xc000, LENGTH = 16K-2k /* Page 3f */
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/* Flash memory pages:
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*
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* The MC9S12NE64 implements 6 bits of the PPAGE register which gives it a
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* 1 Mbyte program memory address space that is accessed through the PPAGE
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* window. The lower 768K portion (0x000000-0x0bffff) of the address space
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* is accessed with PPAGE values 0x00 through 0x2f. This address range
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* is reserved for external memory when the part is operated in expanded
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* mode. The upper 256K of the address space (0x0c0000-0x100000), accessed
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* with PPAGE values 0x30 through 0x3f, is occupied by on chip flash.
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*/
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page30 (rx) : ORIGIN = 0x0c0000, LENGTH = 16K /* Page 30 */
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page31 (rx) : ORIGIN = 0x0c4000, LENGTH = 16K /* Page 31 */
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page32 (rx) : ORIGIN = 0x0c8000, LENGTH = 16K /* Page 32 */
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page33 (rx) : ORIGIN = 0x0cc000, LENGTH = 16K /* Page 33 */
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page34 (rx) : ORIGIN = 0x0d0000, LENGTH = 16K /* Page 34 */
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page35 (rx) : ORIGIN = 0x0d4000, LENGTH = 16K /* Page 35 */
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page36 (rx) : ORIGIN = 0x0d8000, LENGTH = 16K /* Page 36 */
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page37 (rx) : ORIGIN = 0x0dc000, LENGTH = 16K /* Page 37 */
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page38 (rx) : ORIGIN = 0x0e0000, LENGTH = 16K /* Page 38 */
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page39 (rx) : ORIGIN = 0x0e4000, LENGTH = 16K /* Page 39 */
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page3a (rx) : ORIGIN = 0x0e8000, LENGTH = 16K /* Page 3a */
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page3b (rx) : ORIGIN = 0x0ec000, LENGTH = 16K /* Page 3b */
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page3c (rx) : ORIGIN = 0x0f0000, LENGTH = 16K /* Page 3c */
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page3d (rx) : ORIGIN = 0x0f4000, LENGTH = 16K /* Page 3d */
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page3e (rx) : ORIGIN = 0x0f8000, LENGTH = 16K /* Page 3e */
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page3f (rx) : ORIGIN = 0x0fc000, LENGTH = 16K-2K /* Page 3f */
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/* Vectors. These get relocated to 0xf780-f7ff by the serial loader */
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vectors (rx) : ORIGIN = 0xff80, LENGTH = 256
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}
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OUTPUT_ARCH(m68hcs12)
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OUTPUT_ARCH(m68hc12)
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ENTRY(_stext)
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SECTIONS
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{
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@ -61,29 +102,17 @@ SECTIONS
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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_etext = ABSOLUTE(.);
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} > flash
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} > hitext
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_eronly = ABSOLUTE(.); /* See below */
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/* The DEMO9S12NE64 has 64Kb of SRAM beginning at the following address */
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.data : {
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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_edata = ABSOLUTE(.);
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} > sram AT > flash
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.ARM.extab : {
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*(.ARM.extab*)
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} >sram
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.ARM.exidx : {
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__exidx_start = ABSOLUTE(.);
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*(.ARM.exidx*)
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__exidx_end = ABSOLUTE(.);
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} >sram
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} > sram AT > lowtext
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.bss : { /* BSS */
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_sbss = ABSOLUTE(.);
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@ -92,7 +121,14 @@ SECTIONS
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*(COMMON)
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_ebss = ABSOLUTE(.);
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} > sram
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/* Stabs debugging sections. */
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.vectors : {
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_svectors = ABSOLUTE(.);
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*(.vectors)
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_evectors = ABSOLUTE(.);
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} > vectors
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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