ARMv7 L2 Cache: Minor bugfixes/improvements
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0519118de2
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@ -284,7 +284,7 @@ static void pl310_flush_all(void)
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/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
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* EB, are empty.
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*/
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putreg32(0, L2CC_CSR);
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}
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@ -313,9 +313,14 @@ int l2cc_initialize(void)
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uint32_t regval;
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int i;
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/* Make sure that this is a PL310 cache, version r3p2 */
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/* Make sure that this is a PL310 cache, version r3p2.
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*
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* REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which is
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* r3p2, but the chip that I have actually* reports 0x410000C9 which is some
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* later revision.
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*/
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DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2);
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//DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2);
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/* Make sure that actual cache configuration agrees with the configured
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* cache configuration.
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@ -506,19 +511,19 @@ void l2cc_sync(void)
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*
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***************************************************************************/
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static void l2cc_invalidate_all(void)
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void l2cc_invalidate_all(void)
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{
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irqstate_t flags;
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uint32_t regval;
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/* Invalidate all ways */
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flags = irqsave();
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/* Verify that we are not attempting to invalidate the L2 cache while it
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* is enabled
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*/
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/* Disable the L2 cache while we invalidate it */
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DEBUGASSERT((getreg32(L2CC_CR) & L2CC_CR_L2CEN) == 0);
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regval = getreg32(L2CC_CR);
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l2cc_disable();
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/* Invalidate all ways by writing the bit mask of ways to be invalidated
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* the Invalidate Way Register (IWR).
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@ -533,8 +538,12 @@ static void l2cc_invalidate_all(void)
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/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
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* EB, are empty.
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*/
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putreg32(0, L2CC_CSR);
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/* Then re-enable the L2 cache if it was enabled before */
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putreg32(regval, L2CC_CR);
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irqrestore(flags);
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}
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@ -629,7 +638,7 @@ void l2cc_invalidate(uintptr_t startaddr, uintptr_t endaddr)
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/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
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* EB, are empty.
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*/
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flags = irqsave();
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putreg32(0, L2CC_CSR);
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irqrestore(flags);
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@ -667,7 +676,7 @@ void l2cc_clean_all(void)
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/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
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* EB, are empty.
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*/
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putreg32(0, L2CC_CSR);
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irqrestore(flags);
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}
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@ -719,7 +728,7 @@ void l2cc_clean(uintptr_t startaddr, uintptr_t endaddr)
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* this in small chunks so that we do not have to keep interrupts
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* disabled throughout the whole flush.
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*/
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cleansize = endaddr - startaddr;
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gulpend = startaddr + MIN(cleansize, PL310_GULP_SIZE);
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@ -747,7 +756,7 @@ void l2cc_clean(uintptr_t startaddr, uintptr_t endaddr)
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/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
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* EB, are empty.
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*/
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flags = irqsave();
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putreg32(0, L2CC_CSR);
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irqrestore(flags);
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@ -825,7 +834,7 @@ void l2cc_flush(uint32_t startaddr, uint32_t endaddr)
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* this in small chunks so that we do not have to keep interrupts
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* disabled throughout the whole flush.
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*/
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flushsize = endaddr - startaddr;
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gulpend = startaddr + MIN(flushsize, PL310_GULP_SIZE);
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@ -853,7 +862,7 @@ void l2cc_flush(uint32_t startaddr, uint32_t endaddr)
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/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
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* EB, are empty.
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*/
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flags = irqsave();
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putreg32(0, L2CC_CSR);
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irqrestore(flags);
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@ -147,7 +147,7 @@ void l2cc_sync(void);
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*
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***************************************************************************/
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static void l2cc_invalidate_all(void);
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void l2cc_invalidate_all(void);
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/***************************************************************************
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* Name: l2cc_invalidate
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@ -238,5 +238,21 @@ void l2cc_flush(uint32_t startaddr, uint32_t endaddr);
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#endif
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#endif /* __ASSEMBLY__ */
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#else /* CONFIG_ARMV7A_L2CC */
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/* Provide simple definitions to concentrate the inline conditional
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* compilation in one place.
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*/
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# define l2cc_initialize() (0)
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# define l2cc_enable()
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# define l2cc_disable()
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# define l2cc_sync()
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# define l2cc_invalidate_all()
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# define l2cc_invalidate(s,e)
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# define l2cc_clean_all()
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# define l2cc_clean(s,e)
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# define l2cc_flush_all()
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# define l2cc_flush(s,e)
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#endif /* CONFIG_ARMV7A_L2CC */
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#endif /* __ARCH_ARM_SRC_ARMV7_A_L2CC_H */
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