SAML21: Add interrupt header file + fix a few initial compile issues. Still a long way to go
This commit is contained in:
Gregory Nutt
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dfa87403b3
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4458a34787
@ -75,10 +75,12 @@
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/* Chip-Specific External interrupts */
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#if defined(SAMD20)
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#if defined(CONFIG_ARCH_FAMILY_SAMD20)
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# include <arch/samdl/samd20_irq.h>
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#elif defined(CONFIG_ARCH_FAMILY_SAML21)
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# include <arch/samdl/saml21_irq.h>
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#else
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# error "Unrecognized/unsupported SAMD/L chip"
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# error Unrecognized SAMD/L architecture
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#endif
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/****************************************************************************************
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150
arch/arm/include/samdl/saml21_irq.h
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150
arch/arm/include/samdl/saml21_irq.h
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@ -0,0 +1,150 @@
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/****************************************************************************************
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* arch/arm/include/samd/saml21_irq.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through
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* nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_SAMDL_SAML21_IRQ_H
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#define __ARCH_ARM_INCLUDE_SAMDL_SAML21_IRQ_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* External interrupts */
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#define SAM_IRQ_PM (SAM_IRQ_INTERRUPT+0) /* Power Manager */
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#define SAM_IRQ_MCLK (SAM_IRQ_INTERRUPT+0) /* Main Clock */
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#define SAM_IRQ_OSCCTRL (SAM_IRQ_INTERRUPT+0) /* Oscillators Controller */
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#define SAM_IRQ_OSC32KCTRL (SAM_IRQ_INTERRUPT+0) /* 32KHz scillators Controller */
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#define SAM_IRQ_SUPC (SAM_IRQ_INTERRUPT+0) /* Supply Controller */
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#define SAM_IRQ_PACC (SAM_IRQ_INTERRUPT+0) /* Protection Access Controller */
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#define SAM_IRQ_WDT (SAM_IRQ_INTERRUPT+1) /* Watchdog Timer */
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#define SAM_IRQ_RTC (SAM_IRQ_INTERRUPT+2) /* Real Time Counter */
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#define SAM_IRQ_EIC (SAM_IRQ_INTERRUPT+3) /* External Interrupt Controller */
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#define SAM_IRQ_NVMCTRL (SAM_IRQ_INTERRUPT+4) /* Non-Volatile Memory Controller */
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#define SAM_IRQ_DMAC (SAM_IRQ_INTERRUPT+5) /* Direct Memory Access Controller */
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#define SAM_IRQ_USB (SAM_IRQ_INTERRUPT+6) /* Universal Serial Bus */
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#define SAM_IRQ_EVSYS (SAM_IRQ_INTERRUPT+7) /* Event System */
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#define SAM_IRQ_SERCOM0 (SAM_IRQ_INTERRUPT+8) /* Serial Communication Interface 0 */
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#define SAM_IRQ_SERCOM1 (SAM_IRQ_INTERRUPT+9) /* Serial Communication Interface 1 */
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#define SAM_IRQ_SERCOM2 (SAM_IRQ_INTERRUPT+10) /* Serial Communication Interface 2 */
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#define SAM_IRQ_SERCOM3 (SAM_IRQ_INTERRUPT+11) /* Serial Communication Interface 3 */
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#define SAM_IRQ_SERCOM4 (SAM_IRQ_INTERRUPT+12) /* Serial Communication Interface 4 */
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#define SAM_IRQ_SERCOM5 (SAM_IRQ_INTERRUPT+13) /* Serial Communication Interface 5 */
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#define SAM_IRQ_TCC0 (SAM_IRQ_INTERRUPT+14) /* Timer/Counter for Control 0 */
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#define SAM_IRQ_TCC1 (SAM_IRQ_INTERRUPT+15) /* Timer/Counter for Control 1 */
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#define SAM_IRQ_TCC2 (SAM_IRQ_INTERRUPT+16) /* Timer/Counter for Control 2 */
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#define SAM_IRQ_TC0 (SAM_IRQ_INTERRUPT+17) /* Timer/Counter 0 */
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#define SAM_IRQ_TC1 (SAM_IRQ_INTERRUPT+18) /* Timer/Counter 1 */
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#define SAM_IRQ_TC2 (SAM_IRQ_INTERRUPT+19) /* Timer/Counter 2 */
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#define SAM_IRQ_TC3 (SAM_IRQ_INTERRUPT+20) /* Timer/Counter 3 */
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#define SAM_IRQ_TC4 (SAM_IRQ_INTERRUPT+21) /* Timer/Counter 4 */
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#define SAM_IRQ_ADC (SAM_IRQ_INTERRUPT+22) /* Analog-to-Digital Converter */
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#define SAM_IRQ_AC (SAM_IRQ_INTERRUPT+23) /* Analog Comparator */
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#define SAM_IRQ_DAC (SAM_IRQ_INTERRUPT+24) /* Digital-to-Analog Converter */
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#define SAM_IRQ_PTC (SAM_IRQ_INTERRUPT+25) /* Peripheral Touch Controller */
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#define SAM_IRQ_AES (SAM_IRQ_INTERRUPT+26) /* Advanced Encryption Standard Module */
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#define SAM_IRQ_TRNG (SAM_IRQ_INTERRUPT+27) /* True Random Number Generator */
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#define SAM_IRQ_NINTS (28) /* Total number of interrupts */
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#define SAM_IRQ_NIRQS (SAM_IRQ_INTERRUPT+28) /* The number of real interrupts */
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/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
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#ifdef CONFIG_GPIO_IRQ
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# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
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# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
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# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
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# define SAM_IRQ_EXTINT3 (SAM_IRQ_NIRQS+3) /* External interrupt 3 */
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# define SAM_IRQ_EXTINT4 (SAM_IRQ_NIRQS+4) /* External interrupt 4 */
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# define SAM_IRQ_EXTINT5 (SAM_IRQ_NIRQS+5) /* External interrupt 5 */
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# define SAM_IRQ_EXTINT6 (SAM_IRQ_NIRQS+6) /* External interrupt 6 */
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# define SAM_IRQ_EXTINT7 (SAM_IRQ_NIRQS+7) /* External interrupt 7 */
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# define SAM_IRQ_EXTINT8 (SAM_IRQ_NIRQS+8) /* External interrupt 8 */
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# define SAM_IRQ_EXTINT9 (SAM_IRQ_NIRQS+9) /* External interrupt 9 */
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# define SAM_IRQ_EXTINT10 (SAM_IRQ_NIRQS+10) /* External interrupt 10 */
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# define SAM_IRQ_EXTINT11 (SAM_IRQ_NIRQS+11) /* External interrupt 11 */
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# define SAM_IRQ_EXTINT12 (SAM_IRQ_NIRQS+12) /* External interrupt 12 */
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# define SAM_IRQ_EXTINT13 (SAM_IRQ_NIRQS+13) /* External interrupt 13 */
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# define SAM_IRQ_EXTINT14 (SAM_IRQ_NIRQS+14) /* External interrupt 14 */
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# define SAM_IRQ_EXTINT15 (SAM_IRQ_NIRQS+15) /* External interrupt 15 */
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# define SAM_IRQ_NEXTINTS 16
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#else
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# define SAM_IRQ_NEXTINTS 0
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#endif
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/* Total number of IRQ numbers */
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#define NR_VECTORS SAM_IRQ_NIRQS
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#define NR_IRQS (SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS + SAM_IRQ_NEXTINTS)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Inline Functions
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************************
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* Public Function Prototypes
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****************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_SAMDL_SAML21_IRQ_H */
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@ -293,8 +293,8 @@
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#define PORT_SERCOM3_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN18)
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#define PORT_SERCOM3_PAD3_1 (PORT_FUNCC | PORTA | PORT_PIN25)
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#define PORT_SERCOM3_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN19)
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#define PORT_SERCOM3_PAD3_1 (PORT_FUNCD | PORTA | PORT_PIN20)
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#define PORT_SERCOM3_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN21)
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#define PORT_SERCOM3_PAD3_3 (PORT_FUNCD | PORTA | PORT_PIN20)
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#define PORT_SERCOM3_PAD3_4 (PORT_FUNCD | PORTA | PORT_PIN21)
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#define PORT_SERCOM4_PAD0_1 (PORT_FUNCC | PORTB | PORT_PIN12)
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#define PORT_SERCOM4_PAD0_2 (PORT_FUNCD | PORTA | PORT_PIN12)
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#define PORT_SERCOM4_PAD0_3 (PORT_FUNCD | PORTB | PORT_PIN9)
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@ -303,7 +303,7 @@
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#define PORT_SERCOM4_PAD1_3 (PORT_FUNCD | PORTB | PORT_PIN8)
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#define PORT_SERCOM4_PAD2_1 (PORT_FUNCC | PORTB | PORT_PIN14)
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#define PORT_SERCOM4_PAD2_2 (PORT_FUNCD | PORTA | PORT_PIN14)
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#define PORT_SERCOM4_PAD2_2 (PORT_FUNCD | PORTB | PORT_PIN10)
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#define PORT_SERCOM4_PAD2_3 (PORT_FUNCD | PORTB | PORT_PIN10)
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#define PORT_SERCOM4_PAD3_1 (PORT_FUNCC | PORTB | PORT_PIN15)
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#define PORT_SERCOM4_PAD3_2 (PORT_FUNCD | PORTA | PORT_PIN15)
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#define PORT_SERCOM4_PAD3_3 (PORT_FUNCD | PORTB | PORT_PIN11)
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@ -62,10 +62,10 @@
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/* NVM Software Calibration Area */
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#defien SAM_NVMCALIB_AREA0 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 0-31 */
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#defien SAM_NVMCALIB_AREA1 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 32-63 */
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#defien SAM_NVMCALIB_AREA2 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 64-95 */
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#defien SAM_NVMCALIB_AREA3 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 96-127 */
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#define SAM_NVMCALIB_AREA0 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 0-31 */
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#define SAM_NVMCALIB_AREA1 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 32-63 */
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#define SAM_NVMCALIB_AREA2 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 64-95 */
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#define SAM_NVMCALIB_AREA3 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 96-127 */
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/* Fuse bit-field definitions **************************************************************/
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/* NVM user row bits 0-31 */
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