SAMV7: Add basic clock and timer ISR configuration logic
This commit is contained in:
Gregory Nutt
parent
16b29c54a9
commit
44648d4a97
@ -51,7 +51,7 @@
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#endif
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/************************************************************************************
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* Definitions
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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@ -82,7 +82,7 @@
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/* PLLA configuration.
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*
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* Divider = 1
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* Multipler = 16 or 20
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* Multiplier = 16 or 20
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*/
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#ifdef CONFIG_SAM4EEK_120MHZ
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@ -177,7 +177,7 @@
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/* FLASH wait states.
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*
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* SAM4E-EK documetion says:
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* SAM4E-EK documentation says:
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* VDDCORE: "The voltage ranges from 1.08V to 1.32V."
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* VDDIO: Looks like it is at 3.3V
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*
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@ -274,7 +274,8 @@
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C" {
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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@ -311,10 +312,10 @@ void sam_setleds(uint8_t ledset);
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#endif
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/************************************************************************************
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* Name: stm32_lcdclear
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* Name: sam_lcdclear
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*
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* Description:
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* This is a non-standard LCD interface just for the Shenzhou board. Because
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* This is a non-standard LCD interface just for the SAM4e-EK board. Because
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* of the various rotations, clearing the display in the normal way by writing a
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* sequences of runs that covers the entire display can be very slow. Here the
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* display is cleared by simply setting all GRAM memory to the specified color.
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@ -45,6 +45,129 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* After power-on reset, the SAMV71Q device is running out of the Master Clock using
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* the Fast RC Oscillator running at 4 MHz.
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*
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* MAINOSC: Frequency = 12MHz (crystal)
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*
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* 300MHz Settings:
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* PLLA: PLL Divider = 1, Multiplier = 20 to generate PLLACK = 240MHz
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* Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 120MHz
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* CPU clock: 120MHz
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*
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*/
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/* Main oscillator register settings.
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*
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* The main oscillator could be either the embedded 4/8/12 MHz fast RC oscillators
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* or an external 3-20 MHz crystal or ceramic resonator. The external clock source
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* is selected by default in sam_clockconfig.c. Here we need to specify the main
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* oscillator start-up time.
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*
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* REVISIT... this is old information:
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* The start up time should be should be:
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*
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* Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
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*/
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#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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/* PLLA configuration.
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*
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* Divider = 1
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* Multiplier = 25
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*
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* Yields:
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*
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* PLLACK = 25 * 12MHz / 1 = 300MHz
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*/
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#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_CKGR_PLLAR_MUL PMC_CKGR_PLLAR_MUL(25)
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#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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/* PMC master clock register settings.
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*
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* BOARD_PMC_MCKR_CSS - The source of main clock input. This may be one of:
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*
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* PMC_MCKR_CSS_SLOW Slow Clock
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* PMC_MCKR_CSS_MAIN Main Clock
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* PMC_MCKR_CSS_PLLA PLLA Clock
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* MC_MCKR_CSS_UPLL Divided UPLL Clock
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*
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* BOARD_PMC_MCKR_PRES - Source clock pre-scaler. May be one of:
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*
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* PMC_MCKR_PRES_DIV1 Selected clock
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* PMC_MCKR_PRES_DIV2 Selected clock divided by 2
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* PMC_MCKR_PRES_DIV4 Selected clock divided by 4
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* PMC_MCKR_PRES_DIV8 Selected clock divided by 8
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* PMC_MCKR_PRES_DIV16 Selected clock divided by 16
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* MC_MCKR_PRES_DIV32 Selected clock divided by 32
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* PMC_MCKR_PRES_DIV64 Selected clock divided by 64
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* PMC_MCKR_PRES_DIV3 Selected clock divided by 3
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*
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* The prescaler determines (1) the CPU clock and (2) the input into the
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* second divider that then generates the Master Clock (MCK). MCK is the
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* source clock of the peripheral clocks.
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*
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* BOARD_PMC_MCKR_MDIV - MCK divider. May be one of:
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*
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* PMC_MCKR_MDIV_DIV1 Master Clock is Prescaler Output Clock / 1
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* PMC_MCKR_MDIV_DIV2 Master Clock = Prescaler Output Clock / 2
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* PMC_MCKR_MDIV_DIV4 Master Clock = Prescaler Output Clock / 4
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* PMC_MCKR_MDIV_DIV3 Master Clock = Prescaler Output Clock / 3
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*/
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA /* Source = PLLA */
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1 /* Prescaler = /1 */
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#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_DIV2 /* MCK divider = /2 */
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/* USB clocking
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* To be provided
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*/
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#define BOARD_PMC_MCKR_UPLLDIV2 0 /* UPLL clock not divided by 2 */
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/* Resulting frequencies */
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#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
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#define BOARD_PLLA_FREQUENCY (300000000) /* PLLACK: 25 * 12Mhz / 1 */
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#define BOARD_CPU_FREQUENCY (300000000) /* CPU: PLLACK / 1 */
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#define BOARD_MCK_FREQUENCY (150000000) /* MCK: PLLACK / 1 / 2 */
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV+1)).
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*
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* MCI_SPEED = MCK / (2*(CLKDIV+1))
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* CLKDIV = MCK / MCI_SPEED / 2 - 1
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*
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* Where CLKDIV has a range of 0-255.
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*/
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/* FLASH wait states.
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*
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* Wait states Max frequency at 105 centigrade (STH conditions)
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*
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* VDDIO
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* 1.62V 2.7V
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* --- ------- -------
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* 0 26 MHz 30 MHz
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* 1 52 MHz 62 MHz
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* 2 78 MHz 93 MHz
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* 3 104 MHz 124 MHz
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* 4 131 MHz 150 MHz
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* 5 150 MHz --- MHz
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*/
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#define BOARD_FWS 5
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/* LED definitions ******************************************************************/
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/* Button definitions ***************************************************************/
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/************************************************************************************
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* Public Types
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@ -54,8 +177,58 @@
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: sam_ledinit, sam_setled, and sam_setleds
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*
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* Description:
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* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If
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* CONFIG_ARCH_LEDS is not defined, then the following interfacesare available to
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* control the LEDs from user applications.
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*
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************************************************************************************/
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#ifndef CONFIG_ARCH_LEDS
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void sam_ledinit(void);
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void sam_setled(int led, bool ledon);
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void sam_setleds(uint8_t ledset);
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#endif
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/************************************************************************************
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* Name: sam_lcdclear
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*
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* Description:
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* This is a non-standard LCD interface just for the SAM4e-EK board. Because
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* of the various rotations, clearing the display in the normal way by writing a
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* sequences of runs that covers the entire display can be very slow. Here the
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* display is cleared by simply setting all GRAM memory to the specified color.
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*
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************************************************************************************/
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#if defined(CONFIG_SAM4EEK_LCD_RGB565)
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void sam_lcdclear(uint16_t color);
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#else /* if defined(CONFIG_SAM4EEK_LCD_RGB24) defined(CONFIG_SAM4EEK_LCD_RGB32) */
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void sam_lcdclear(uint32_t color);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __CONFIGS_SAMV71_XULT_INCLUDE_BOARD_H */
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