Misc. trivial changes from review of last PR
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/stm32l4/stm32l4_lse.c
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*
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* Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: dev@ziggurat29.com
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*
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* Redistribution and use in source and binary forms, with or without
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@ -45,18 +45,6 @@
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#include "stm32l4_rcc.h"
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#include "stm32l4_waste.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -88,8 +76,8 @@ void stm32l4_rcc_enablelse(void)
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* the RCC BDCR register.
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*/
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regval = getreg32(STM32L4_RCC_BDCR);
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regval |= RCC_BDCR_LSEON|RCC_BDCR_LSEDRV_MIDHI;
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regval = getreg32(STM32L4_RCC_BDCR);
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regval |= RCC_BDCR_LSEON | RCC_BDCR_LSEDRV_MIDHI;
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putreg32(regval,STM32L4_RCC_BDCR);
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/* Wait for the LSE clock to be ready */
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@ -2,7 +2,7 @@
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* arch/arm/src/stm32l4/stm32l4_pwr.c
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
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* Authors: Uros Platise <uros.platise@isotel.eu>
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* Gregory Nutt <gnutt@nuttx.org>
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* dev@ziggurat29.com
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@ -51,11 +51,6 @@
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#include "stm32l4_pwr.h"
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#include "stm32l4_rcc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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@ -103,8 +98,7 @@ bool stm32l4_pwr_enableclk(bool enable)
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regval = getreg32(STM32L4_RCC_APB1ENR1);
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wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
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/* Power interface clock enable.
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*/
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/* Power interface clock enable. */
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if (wasenabled && !enable)
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{
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32l4/stm32l4_pwr.h
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*
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* Copyright (C) 2009, 2013, 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: dev@ziggurat29.com
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*
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* Redistribution and use in source and binary forms, with or without
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@ -84,7 +84,6 @@ extern "C"
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bool stm32l4_pwr_enableclk(bool enable);
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/************************************************************************************
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* Name: stm32l4_pwr_enablebkp
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*
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@ -581,7 +581,7 @@ static void stm32l4_stdclockconfig(void)
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# error STM32L4_BOARD_USEMSI not yet implemented in arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
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/* setting MSIRANGE */
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/* setting MSIPLLEN */
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regval = getreg32(STM32L4_RCC_CR);
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regval |= RCC_CR_MSION; /* Enable MSI */
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putreg32(regval, STM32L4_RCC_CR);
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@ -621,9 +621,8 @@ static void stm32l4_stdclockconfig(void)
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{
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#warning todo: regulator voltage according to clock freq
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#if 0
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/* ensure Power control is enabled before modifying it
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*/
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/* Ensure Power control is enabled before modifying it. */
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regval = getreg32(STM32L4_RCC_APB1ENR);
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regval |= RCC_APB1ENR_PWREN;
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putreg32(regval, STM32L4_RCC_APB1ENR);
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@ -631,7 +630,7 @@ static void stm32l4_stdclockconfig(void)
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/* Select regulator voltage output Scale 1 mode to support system
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* frequencies up to 168 MHz.
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*/
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regval = getreg32(STM32L4_PWR_CR);
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regval &= ~PWR_CR_VOS_MASK;
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regval |= PWR_CR_VOS_SCALE_1;
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