Add lm3s ethernet header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1808 42af7a65-404d-4744-a932-0658087f49c3
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arch/arm/src/lm3s/lm3s_ethernet.h
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arch/arm/src/lm3s/lm3s_ethernet.h
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/************************************************************************************
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* arch/arm/src/lm3s/lm3s_ethernet.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LM3S_LM3S_ETHERNET_H
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#define __ARCH_ARM_SRC_LM3S_LM3S_ETHERNET_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Ethernet Controller Register Offsets *********************************************/
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/* Ethernet MAC Register Offsets */
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#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
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#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
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#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
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#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
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#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
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#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
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#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
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#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
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#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
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#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
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#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
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#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
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#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
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#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
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#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
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/* MII Management Registers (see include/nuttx/mii.h) */
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/* Ethernet Controller Register Addresses *******************************************/
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#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET)
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#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET)
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#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET)
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#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET)
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#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET)
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#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET)
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#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET)
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#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET)
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#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET)
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#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET)
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#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET)
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#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET)
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#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
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#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
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#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
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/* Ethernet Controller Register Bit Definitions *************************************/
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/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */
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#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */
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#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */
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#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */
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#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */
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#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */
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#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */
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#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */
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#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */
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#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */
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#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */
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#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */
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#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */
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#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */
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#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */
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/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */
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#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */
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#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */
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#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */
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#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */
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#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */
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#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */
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#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */
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/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */
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#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */
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#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */
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#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */
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#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */
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#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */
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/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */
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#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */
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#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */
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#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */
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#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */
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/* Ethernet MAC Threshold (MACTHR), offset 0x01c */
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#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */
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/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */
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#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */
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#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */
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#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */
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#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT)
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/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */
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#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */
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/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */
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#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */
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/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */
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#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LM3S_LM3S_ETHERNET_H */
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@ -1,7 +1,7 @@
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/****************************************************************************
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* include/nuttx/mii.h
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -49,15 +49,29 @@
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/* MII register offsets *****************************************************/
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/* Apparently common registers */
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/* Common MII management registers. The IEEE 802.3 standard specifies a
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* register set for controlling and gathering status from the PHY layer. The
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* registers are collectively known as the MII Management registers and are
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* detailed in Section 22.2.4 of the IEEE 802.3 specification.
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*/
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#define MII_MCR 0x00 /* MII management control */
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#define MII_MSR 0x01 /* MII management status */
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#define MII_PHYID1 0x02 /* PHY ID 1 */
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#define MII_PHYID2 0x03 /* PHY ID 2 */
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#define MII_ADVERTISE 0x04 /* Auto-negotiation advertisement */
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#define MII_LPA 0x05 /* Auto-negotiation link partner ability */
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#define MII_EXPANSION 0x06 /* Auto-negotiation expansion register*/
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#define MII_LPA 0x05 /* Auto-negotiation link partner base page ability */
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#define MII_EXPANSION 0x06 /* Auto-negotiation expansion */
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#define MII_NEXTPAGE 0x07 /* Auto-negotiation next page */
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#define MII_LPANEXTPAGE 0x08 /* Auto-negotiation link partner received next page */
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#define MII_MSCONTROL 0x09 /* Master/slave control register */
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#define MII_MSSTATUS 0x0a /* Master/slave status register */
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#define MII_PSECONTROL 0x0b /* PSE control register */
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#define MII_PSESTATUS 0x0c /* PSE status register */
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#define MII_MMDCONTROL 0x0d /* MMD access control register */
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#define MII_ESTATUS 0x0f /* Extended status register */
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/* Registers 16-31 may be used for vendor specific abilities */
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/* DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f reserved */
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#define MII_AM79C874_NPADVERTISE 0x07 /* Auto-negotiation next page advertisement */
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#define MII_AM79C874_MISCFEATURES 0x10 /* Miscellaneous features reg */
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#define MII_AM79C874_INTCS 0x11 /* Interrupt control/status */
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#define MII_AM79C874_DIAGNOSTIC 0x12 /* Diagnostic register */
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#define MII_AM79C874_LOOPBACK 0x13 /* Power management/loopback register */
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#define MII_AM79C874_DIAGNOSTIC 0x12 /* Diagnostic */
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#define MII_AM79C874_LOOPBACK 0x13 /* Power management/loopback */
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#define MII_AM79C874_MODEC 0x15 /* Mode control register */
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#define MII_AM79C874_DISCONNECT 0x17 /* Disconnect counter */
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#define MII_AM79C874_RCVERROR 0x18 /* Receive error counter */
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/* Luminary LM3S6918 built-in PHY */
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#define MII_LM3S_VSPECIFIC 0x10 /* Vendor-Specific */
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#define MII_LM3S_INTCS 0x11 /* Interrupt control/status */
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#define MII_LM3S_DIAGNOSTIC 0x12 /* Diagnostic */
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#define MII_LM3S_XCVRCONTROL 0x13 /* Transceiver Control */
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#define MII_LM3S_LEDCONFIG 0x17 /* LED Configuration */
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#define MII_LM3S_MDICONTROL 0x18 /* Ethernet PHY Management MDI/MDIX Control */
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/* */
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#define MII_CTRL1000 0x09 /* 1000BASE-T control */
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#define MII_STAT1000 0x0a /* 1000BASE-T status */
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#define MII_ESTATUS 0x0f /* Extended Status */
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#define MII_NCONFIG 0x1c /* Network interface config */
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/* MII register bit settings ************************************************/
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@ -201,7 +223,7 @@
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/* Am79c874 diagnostics register */
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#define AM79C874_DIAG_RXLOCK 0x0100 /* Bit 8: 1=Rcv PLL locked on */
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#define AM79C874_DIAG_RXPASS 0x0200 /* Bit 9: 2=Operating in 100Base-X mode */
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#define AM79C874_DIAG_RXPASS 0x0200 /* Bit 9: 1=Operating in 100Base-X mode */
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#define AM79C874_DIAG_100MBPS 0x0400 /* Bit 10: 1=ANEG result is 100Mbps */
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#define AM79C874_DIAG_FULLDPLX 0x0800 /* Bit 11: 1=ANEG result is full duplex */
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