diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index a62d050a2d..9662e1889e 100755 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -45,6 +45,5 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_usestack.c up_doirq.c up_hardfault.c up_svcall.c CHIP_ASRCS = -CHIP_CSRCS = stm32_start.c -# stm32_irq.c stm32_gpio.c stm32_timerisr.c stm32_lowputc.c \ -# stm32_serial.c stm32_spi.c stm32_dumpgpio.c +CHIP_CSRCS = stm32_start.c stm32_lowputc.c stm32_serial.c +# stm32_irq.c stm32_gpio.c stm32_timerisr.c stm32_spi.c stm32_dumpgpio.c diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/stm32/stm32_lowputc.c new file mode 100644 index 0000000000..4ed14ee231 --- /dev/null +++ b/arch/arm/src/stm32/stm32_lowputc.c @@ -0,0 +1,176 @@ +/************************************************************************** + * arch/arm/src/stm32/stm32_lowputc.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "stm32_internal.h" + +/************************************************************************** + * Private Definitions + **************************************************************************/ + +/* Configuration **********************************************************/ + +/* Is there a serial console? */ + +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && !defined(CONFIG_USART1_DISABLE) +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && !defined(CONFIG_USART2_DISABLE) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && !defined(CONFIG_USART3_DISABLE) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* Select USART parameters for the selected console */ + +#if defined(CONFIG_USART1_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +#else +# error "No CONFIG_USARTn_SERIAL_CONSOLE Setting" +#endif + +/* Calculate BAUD rate from the SYS clock */ + +/************************************************************************** + * Private Types + **************************************************************************/ + +/************************************************************************** + * Private Function Prototypes + **************************************************************************/ + +/************************************************************************** + * Global Variables + **************************************************************************/ + +/************************************************************************** + * Private Variables + **************************************************************************/ + +/************************************************************************** + * Private Functions + **************************************************************************/ + +/************************************************************************** + * Public Functions + **************************************************************************/ + +/************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + **************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_CONSOLE + /* Wait until the TX FIFO is not full */ + + + /* Then send the character */ +#endif +} + +/************************************************************************** + * Name: up_lowsetup + * + * Description: + * This performs basic initialization of the USART used for the serial + * console. Its purpose is to get the console output availabe as soon + * as possible. + * + **************************************************************************/ + +void up_lowsetup(void) +{ + /* Enable the selected USARTs and configure GPIO pins need byed the + * the selected USARTs. NOTE: The serial driver later depends on + * this pin configuration -- whether or not a serial console is selected. + */ + +#ifndef CONFIG_USART1_DISABLE +#endif + +#ifndef CONFIG_USART1_DISABLE +#endif + +#ifndef CONFIG_USART2_DISABLE +#endif + + /* Enable and configure the selected console device */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_USART_CONFIG) +#endif +} + + diff --git a/arch/arm/src/stm32/stm32_memorymap.h b/arch/arm/src/stm32/stm32_memorymap.h index 48fdd235aa..3aaca34977 100755 --- a/arch/arm/src/stm32/stm32_memorymap.h +++ b/arch/arm/src/stm32/stm32_memorymap.h @@ -117,7 +117,7 @@ #define STM32_RCC_BASE 0x40021000 /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */ /* 0x40021400 - 0x40021fff: Reserved */ #define STM32_OTGFS_BASE 0x50000000 /* 0x50000000 - 0x500003ff: USB OTG FS */ -#define STM32_FLASH_BASE 0x40022000 /* 0x40022000 - 0x400223ff: Flash memory interface */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000 - 0x400223ff: Flash memory interface */ #define STM32_CRC_BASE 0x40028000 /* 0x40023000 - 0x400233ff: RC */ /* 0x40023400 - 0x40027fff: Reserved */ #define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */ diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c new file mode 100644 index 0000000000..59970eb007 --- /dev/null +++ b/arch/arm/src/stm32/stm32_serial.c @@ -0,0 +1,864 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_serial.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "os_internal.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ + +/* Is there a USART enabled? */ + +#if defined(CONFIG_USART1_DISABLE) && defined(CONFIG_USART2_DISABLE) && defined(CONFIG_USART3_DISABLE) +# error "No USARTs enabled" +#endif + +/* Is there a serial console? */ + +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && !defined(CONFIG_USART1_DISABLE) +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && !defined(CONFIG_USART2_DISABLE) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && !defined(CONFIG_USART3_DISABLE) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#ifdef CONFIG_USE_SERIALDRIVER + +/* Which USART with be tty0/console and which tty1? */ + +#if defined(CONFIG_USART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_USART1port /* USART1 is console */ +# define TTYS0_DEV g_USART1port /* USART1 is ttyS0 */ +# ifndef CONFIG_USART2_DISABLE +# define TTYS1_DEV g_USART2port /* USART2 is ttyS1 */ +# ifndef CONFIG_USART3_DISABLE +# define TTYS2_DEV g_USART3port /* USART3 is ttyS2 */ +# else +# undef TTYS1_DEV /* No ttyS2 */ +# endif +# else +# ifndef CONFIG_USART3_DISABLE +# define TTYS1_DEV g_USART3port /* USART3 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# endif +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_USART2port /* USART2 is console */ +# define TTYS0_DEV g_USART2port /* USART2 is ttyS0 */ +# ifndef CONFIG_USART1_DISABLE +# define TTYS1_DEV g_USART1port /* USART1 is ttyS1 */ +# ifndef CONFIG_USART3_DISABLE +# define TTYS2_DEV g_USART3port /* USART3 is ttyS2 */ +# else +# undef TTYS1_DEV /* No ttyS2 */ +# endif +# else +# ifndef CONFIG_USART3_DISABLE +# define TTYS1_DEV g_USART3port /* USART3 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# endif +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_USART3port /* USART3 is console */ +# define TTYS0_DEV g_USART3port /* USART3 is ttyS0 */ +# ifndef CONFIG_USART1_DISABLE +# define TTYS1_DEV g_USART1port /* USART1 is ttyS1 */ +# ifndef CONFIG_USART2_DISABLE +# define TTYS2_DEV g_USART2port /* USART2 is ttyS2 */ +# else +# undef TTYS1_DEV /* No ttyS2 */ +# endif +# else +# ifndef CONFIG_USART2_DISABLE +# define TTYS1_DEV g_USART2port /* USART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# undef TTYS2_DEV /* No ttyS2 */ +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uint32 USARTbase; /* Base address of USART registers */ + uint32 baud; /* Configured baud */ + uint32 im; /* Saved IM value */ + ubyte irq; /* IRQ associated with this USART */ + ubyte parity; /* 0=none, 1=odd, 2=even */ + ubyte bits; /* Number of bits (7 or 8) */ + boolean stopbits2; /* TRUE: Configure with 2 stop bits instead of 1 */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_setup(struct USART_dev_s *dev); +static void up_shutdown(struct USART_dev_s *dev); +static int up_attach(struct USART_dev_s *dev); +static void up_detach(struct USART_dev_s *dev); +static int up_interrupt(int irq, void *context); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct USART_dev_s *dev, uint32 *status); +static void up_rxint(struct USART_dev_s *dev, boolean enable); +static boolean up_rxavailable(struct USART_dev_s *dev); +static void up_send(struct USART_dev_s *dev, int ch); +static void up_txint(struct USART_dev_s *dev, boolean enable); +static boolean up_txready(struct USART_dev_s *dev); +static boolean up_txempty(struct USART_dev_s *dev); + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +struct USART_ops_s g_USART_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifndef CONFIG_USART1_DISABLE +static char g_USART1rxbuffer[CONFIG_USART1_RXBUFSIZE]; +static char g_USART1txbuffer[CONFIG_USART1_TXBUFSIZE]; +#endif +#ifndef CONFIG_USART2_DISABLE +static char g_USART2rxbuffer[CONFIG_USART2_RXBUFSIZE]; +static char g_USART2txbuffer[CONFIG_USART2_TXBUFSIZE]; +#endif +#ifndef CONFIG_USART3_DISABLE +static char g_USART3rxbuffer[CONFIG_USART3_RXBUFSIZE]; +static char g_USART3txbuffer[CONFIG_USART3_TXBUFSIZE]; +#endif + +/* This describes the state of the STM32 USART1 ports. */ + +#ifndef CONFIG_USART1_DISABLE +static struct up_dev_s g_USART1priv = +{ + .USARTbase = STM32_USART1_BASE, + .baud = CONFIG_USART1_BAUD, + .irq = STM32_IRQ_USART1, + .parity = CONFIG_USART1_PARITY, + .bits = CONFIG_USART1_BITS, + .stopbits2 = CONFIG_USART1_2STOP, +}; + +static USART_dev_t g_USART1port = +{ + .recv = + { + .size = CONFIG_USART1_RXBUFSIZE, + .buffer = g_USART1rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART1_TXBUFSIZE, + .buffer = g_USART1txbuffer, + }, + .ops = &g_USART_ops, + .priv = &g_USART1priv, +}; +#endif + +/* This describes the state of the STM32 USART2 port. */ + +#ifndef CONFIG_USART2_DISABLE +static struct up_dev_s g_USART2priv = +{ + .USARTbase = STM32_USART2_BASE, + .baud = CONFIG_USART2_BAUD, + .irq = STM32_IRQ_USART2, + .parity = CONFIG_USART2_PARITY, + .bits = CONFIG_USART2_BITS, + .stopbits2 = CONFIG_USART2_2STOP, +}; + +static USART_dev_t g_USART2port = +{ + .recv = + { + .size = CONFIG_USART2_RXBUFSIZE, + .buffer = g_USART2rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART2_TXBUFSIZE, + .buffer = g_USART2txbuffer, + }, + .ops = &g_USART_ops, + .priv = &g_USART2priv, +}; +#endif + +/* This describes the state of the STM32 USART3 port. */ + +#ifndef CONFIG_USART3_DISABLE +static struct up_dev_s g_USART3priv = +{ + .USARTbase = STM32_USART3_BASE, + .baud = CONFIG_USART3_BAUD, + .irq = STM32_IRQ_USART3, + .parity = CONFIG_USART3_PARITY, + .bits = CONFIG_USART3_BITS, + .stopbits2 = CONFIG_USART3_2STOP, +}; + +static USART_dev_t g_USART3port = +{ + .recv = + { + .size = CONFIG_USART3_RXBUFSIZE, + .buffer = g_USART3rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART3_TXBUFSIZE, + .buffer = g_USART3txbuffer, + }, + .ops = &g_USART_ops, + .priv = &g_USART3priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32 up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->USARTbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, uint32 value) +{ + putreg32(value, priv->USARTbase + offset); +} + +/**************************************************************************** + * Name: up_disableusartint + ****************************************************************************/ + +static inline void up_disableusartint(struct up_dev_s *priv, uint32 *im) +{ + /* Return the current interrupt mask value */ + + if (im) + { + *im = priv->im; + } + + /* Disable all interrupts */ + + priv->im = 0; +} + +/**************************************************************************** + * Name: up_restoreusartint + ****************************************************************************/ + +static inline void up_restoreusartint(struct up_dev_s *priv, uint32 im) +{ + priv->im = im; +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the USART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int up_setup(struct USART_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + + /* Note: The logic here depends on the fact that that the USART module + * was enabled and the GPIOs were configured in up_lowsetup(). + */ + + /* Disable the USART */ + + /* Calculate BAUD rate from the SYS clock */ + + /* Set the USART to interrupt whenever the TX FIFO is almost empty or when + * any character is received. + */ + + /* Flush the Rx and Tx FIFOs */ + + /* Enable Rx interrupts from the USART except for Tx interrupts. We don't want + * Tx interrupts until we have something to send. We will check for serial + * errors as part of Rx interrupt processing (no interrupts will be received + * yet because the interrupt is still disabled at the interrupt controller. + */ + + /* Enable the FIFOs */ + +#ifdef CONFIG_SUPPRESS_USART_CONFIG +#endif + + /* Enable Rx, Tx, and the USART */ + +#ifdef CONFIG_SUPPRESS_USART_CONFIG +#endif + + /* Set up the cache IM value */ + +// priv->im = + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the USART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct USART_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disableusartint(priv, NULL); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the USART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int up_attach(struct USART_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, up_interrupt); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ + + up_enable_irq(priv->irq); + } + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach USART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct USART_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the USART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * approprite USART_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context) +{ + struct USART_dev_s *dev = NULL; + struct up_dev_s *priv; + int passes; + boolean handled; + +#ifndef CONFIG_USART1_DISABLE + if (g_USART1priv.irq == irq) + { + dev = &g_USART1port; + } + else +#endif +#ifndef CONFIG_USART2_DISABLE + if (g_USART2priv.irq == irq) + { + dev = &g_USART2port; + } + else +#endif +#ifndef CONFIG_USART3_DISABLE + if (g_USART3priv.irq == irq) + { + dev = &g_USART3port; + } + else +#endif + { + PANIC(OSERR_INTERNAL); + } + priv = (struct up_dev_s*)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = TRUE; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = FALSE; + + /* Get the masked USART status and clear the pending interrupts. */ + + /* Handle incoming, receive bytes (with or without timeout) */ + + { + /* Rx buffer not empty ... process incoming bytes */ + + uart_recvchars(dev); + handled = TRUE; + } + + /* Handle outgoing, transmit bytes */ + + { + /* Tx FIFO not full ... process outgoing bytes */ + + uart_xmitchars(dev); + handled = TRUE; + } + } + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + struct inode *inode = filep->f_inode; + struct USART_dev_s *dev = inode->i_private; + int ret = OK; + + switch (cmd) + { + case TIOCSERGSTRUCT: + { + struct up_dev_s *user = (struct up_dev_s*)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct up_dev_s)); + } + } + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the USART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct USART_dev_s *dev, uint32 *status) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32 rxd; + + /* Get the Rx byte plux error information. Return those in status */ + + *status = rxd; + + /* Then return the actual received byte */ + + return rxd & 0xff; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct USART_dev_s *dev, boolean enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + if (enable) + { + /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx + * timeout occurs. + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS +// priv->im |= ; +#endif + } + else + { +// priv->im &= ~(); + } +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return TRUE if the receive fifo is not empty + * + ****************************************************************************/ + +static boolean up_rxavailable(struct USART_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return 0; +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the USART + * + ****************************************************************************/ + +static void up_send(struct USART_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct USART_dev_s *dev, boolean enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + irqstate_t flags; + + flags = irqsave(); + if (enable) + { + /* Set to receive an interrupt when the TX fifo is half emptied */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS +// priv->im |= ; + up_serialout(priv, stm32_USART_IM_OFFSET, priv->im); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note that the may recurse and that priv->im + * may be altered. + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + +// priv->im &= ~(); + } + irqrestore(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return TRUE if the tranmsit fifo is not full + * + ****************************************************************************/ + +static boolean up_txready(struct USART_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return 0; +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return TRUE if the transmit fifo is empty + * + ****************************************************************************/ + +static boolean up_txempty(struct USART_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Performs the low level USART initialization early in + * debug so that the serial console will be available + * during bootup. This must be called before up_serialinit. + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* NOTE: All GPIO configuration for the USARTs was performed in + * up_lowsetup + */ + + /* Disable all USARTS */ + + up_disableusartint(TTYS0_DEV.priv, NULL); +#ifdef TTYS1_DEV + up_disableusartint(TTYS1_DEV.priv, NULL); +#endif +#ifdef TTYS2_DEV + up_disableusartint(TTYS2_DEV.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_CONSOLE + CONSOLE_DEV.isconsole = TRUE; + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_CONSOLE + (void)usart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all USARTs */ + + (void)usart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + (void)usart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)usart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + uint32 im; + + up_disableusartint(priv, &im); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + up_restoreusartint(priv, im); +#endif + return ch; +} + +#else /* CONFIG_USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} + +#endif /* CONFIG_USE_SERIALDRIVER */ diff --git a/configs/stm3210e-eval/ostest/defconfig b/configs/stm3210e-eval/ostest/defconfig index c55c11329a..8822f6de90 100755 --- a/configs/stm3210e-eval/ostest/defconfig +++ b/configs/stm3210e-eval/ostest/defconfig @@ -96,35 +96,43 @@ CONFIG_STM32_BUILDROOT=y # # STM32F103Z specific serial device driver settings # -# CONFIG_UARTn_DISABLE - select to disable all support for +# CONFIG_USARTn_DISABLE - select to disable all support for # the UART -# CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the -# console and ttys0 (default is the UART0). -# CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received. +# CONFIG_USARTn_SERIAL_CONSOLE - selects the USARTn for the +# console and ttys0 (default is the USART1). +# CONFIG_USARTn_RXBUFSIZE - Characters are buffered as received. # This specific the size of the receive buffer -# CONFIG_UARTn_TXBUFSIZE - Characters are buffered before +# CONFIG_USARTn_TXBUFSIZE - Characters are buffered before # being sent. This specific the size of the transmit buffer -# CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be -# CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8. -# CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity -# CONFIG_UARTn_2STOP - Two stop bits +# CONFIG_USARTn_BAUD - The configure BAUD of the UART. Must be +# CONFIG_USARTn_BITS - The number of bits. Must be either 7 or 8. +# CONFIG_USARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity +# CONFIG_USARTn_2STOP - Two stop bits # -CONFIG_UART0_DISABLE=n -CONFIG_UART1_DISABLE=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_UART1_SERIAL_CONSOLE=n -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART0_BAUD=115200 -CONFIG_UART1_BAUD=115200 -CONFIG_UART0_BITS=8 -CONFIG_UART1_BITS=8 -CONFIG_UART0_PARITY=0 -CONFIG_UART1_PARITY=0 -CONFIG_UART0_2STOP=0 -CONFIG_UART1_2STOP=0 +CONFIG_USART1_DISABLE=n +CONFIG_USART2_DISABLE=y +CONFIG_USART3_DISABLE=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART2_SERIAL_CONSOLE=n +CONFIG_USART3_SERIAL_CONSOLE=n +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART2_TXBUFSIZE=256 +CONFIG_USART3_TXBUFSIZE=256 +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART2_RXBUFSIZE=256 +CONFIG_USART3_RXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART2_BAUD=115200 +CONFIG_USART3_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART2_BITS=8 +CONFIG_USART3_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART2_PARITY=0 +CONFIG_USART3_PARITY=0 +CONFIG_USART1_2STOP=0 +CONFIG_USART2_2STOP=0 +CONFIG_USART3_2STOP=0 # # STM32F103Z specific SSI device driver settings diff --git a/configs/stm3210e-eval/ostest/ld.script b/configs/stm3210e-eval/ostest/ld.script index fd0014c209..0e318f7ccd 100755 --- a/configs/stm3210e-eval/ostest/ld.script +++ b/configs/stm3210e-eval/ostest/ld.script @@ -34,11 +34,12 @@ ****************************************************************************/ /* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of FLASH beginning at 0x2000:0000*/ + * 64Kb of SRAM beginning at address 0x2000:0000 + */ MEMORY { - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K }