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Fix some MIPS software interrupt enabling issues

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4067 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-10-29 02:29:13 +00:00
parent 64fba1740e
commit 44dc775b08
3 changed files with 581 additions and 578 deletions
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2
arch/mips/include/mips32/cp0.h
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@ -278,7 +278,7 @@
# define CP0_CAUSE_IP5 (0x13 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 3 */
# define CP0_CAUSE_IP6 (0x14 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 4 */
# define CP0_CAUSE_IP7 (0x15 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 5, timer or performance counter interrupt */
#define CP0_CAUSE_WP (1 << 22 Watch exception was deferred
#define CP0_CAUSE_WP (1 << 22) /* Watch exception was deferred
#define CP0_CAUSE_IV (1 << 23) /* Bit 23: Interrupt exception uses special interrupt vector */
#define CP0_CAUSE_CE_SHIFT (28) /* Bits 28-29: Coprocessor unit number fo Coprocessor Unusable exception */
#define CP0_CAUSE_CE_MASK (3 << CP0_CAUSE_CE_SHIFT)

2
arch/mips/src/mips32/up_irq.c
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@ -83,7 +83,7 @@ irqstate_t irqsave(void)
status &= ~CP0_STATUS_IM_MASK; /* Clear all interrupt mask bits */
status |= CP0_STATUS_IM_SWINTS; /* Keep S/W interrupts enabled */
cp0_putstatus(status); /* Disable interrupts */
return ret; /* Return status before interrtupts disabled */
return ret; /* Return status before interrupts disabled */
}
/****************************************************************************

7
arch/mips/src/pic32mx/pic32mx-irq.c
View File

@ -136,16 +136,19 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Interrupts are enabled by setting the IE bit in the CP0 status register */
regval = 0;
asm volatile("ei %0" : "=r"(regval));
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Then enable all interrupt levels */
irqrestore(CP0_STATUS_IM_ALL);
#else
/* Enable only software interrupts */
irqrestore(CP0_STATUS_IM_SWINTS);
#endif
}