diff --git a/arch/arm/src/efm32/Kconfig b/arch/arm/src/efm32/Kconfig index 631e526505..2ca920c330 100644 --- a/arch/arm/src/efm32/Kconfig +++ b/arch/arm/src/efm32/Kconfig @@ -1,57 +1,141 @@ -# -# arch/arm/src/efm32/Kconfig -# - -if ARCH_CHIP_EFM32 - -comment "EFM32 Configuration Options" - -choice - prompt "EFM32 Chip Selection" - default ARCH_CHIP_EFM32TG840F32 - -config ARCH_CHIP_EFM32TG840F32 - bool "EFM32TG840F32" - select EFM32_EFM32TG - select ARCH_CORTEXM3 - ---help--- - This chip is a Tiny Gecko with 32 KB flash and 4 KB RAM in a QFN64 - package - -config ARCH_CHIP_EFM32G880F128 - bool "EFM32G880F128" - select EFM32_EFM32G - select ARCH_CORTEXM3 - ---help--- - This chip is a Gecko with 128KiB flash and 16KiB RAM in a LQFP100 - package - -config ARCH_CHIP_EFM32G890F128 - bool "EFM32G890F128" - select EFM32_EFM32G - select ARCH_CORTEXM3 - ---help--- - This chip is a Gecko with 128KiB flash and 16KiB RAM in a BGA112 - package - -config ARCH_CHIP_EFM32GG332F1024 - bool "EFM32GG332F1024" - select EFM32_EFM32GG - select ARCH_CORTEXM3 - ---help--- - This chip is a Giant Gecko with 1024KiB flash and 128KiB RAM in a - QFP64 package. - -endchoice - -config EFM32_EFM32TG -bool n - -config EFM32_EFM32G -bool n - -config EFM32_EFM32GG -bool n - -endif - +# +# arch/arm/src/efm32/Kconfig +# + +if ARCH_CHIP_EFM32 + +comment "EFM32 Configuration Options" + +choice + prompt "EFM32 Chip Selection" + default ARCH_CHIP_EFM32TG840F32 + +config ARCH_CHIP_EFM32TG840F32 + bool "EFM32TG840F32" + select EFM32_EFM32TG + select ARCH_CORTEXM3 + ---help--- + This chip is a Tiny Gecko with 32 KB flash and 4 KB RAM in a QFN64 + package + +config ARCH_CHIP_EFM32G880F128 + bool "EFM32G880F128" + select EFM32_EFM32G + select ARCH_CORTEXM3 + ---help--- + This chip is a Gecko with 128KiB flash and 16KiB RAM in a LQFP100 + package + +config ARCH_CHIP_EFM32G890F128 + bool "EFM32G890F128" + select EFM32_EFM32G + select ARCH_CORTEXM3 + ---help--- + This chip is a Gecko with 128KiB flash and 16KiB RAM in a BGA112 + package + +config ARCH_CHIP_EFM32GG332F1024 + bool "EFM32GG332F1024" + select EFM32_EFM32GG + select ARCH_CORTEXM3 + ---help--- + This chip is a Giant Gecko with 1024KiB flash and 128KiB RAM in a + QFP64 package. + +endchoice + +# These hidden selections represent automatically selected MCU families and, +# in turn, select general capabilities of the MCU family + +config EFM32_EFM32TG + bool n + +config EFM32_EFM32G + bool n + select EFM32_HAVE_USART2 + select EFM32_HAVE_UART0 + select EFM32_HAVE_LEUART1 + +config EFM32_EFM32GG + bool n + select EFM32_HAVE_USART2 + select EFM32_HAVE_UART0 + select EFM32_HAVE_UART1 + select EFM32_HAVE_LEUART1 + +menu "EFM32 Peripheral Support" + +# These "hidden" settings determine is a peripheral option is available for +# the selection MCU + +config EFM32_HAVE_USART2 + bool + default n + +config EFM32_HAVE_UART0 + bool + default n + +config EFM32_HAVE_UART1 + bool + default n + +config EFM32_HAVE_LEUART1 + bool + default n + +# When there are multiple instances of a device, these "hidden" settings +#will automatically be selected and will represent the 'OR' of the +# instances selected. + +# selection MCU + +config EFM32_UART + bool + default n + +# Then, these are the actual, selectable peripheral options + +config EFM32_UART0 + bool "USART0" + default n + select ARCH_HAVE_USART0 + select EFM32_UART + +config EFM32_UART1 + bool "USART1" + default n + select ARCH_HAVE_USART1 + select EFM32_UART + +config EFM32_UART2 + bool "USART2" + default n + depends on EFM32_HAVE_USART2 + select ARCH_HAVE_USART2 + select EFM32_UART + +config EFM32_UART0 + bool "UART0" + default n + select ARCH_HAVE_UART0 + select EFM32_UART + +config EFM32_UART1 + bool "UART1" + default n + select ARCH_HAVE_UART1 + select EFM32_UART + +config EFM32_LEUART0 + bool "Low energy UART0" + default n + select EFM32_UART + +config EFM32_LEUART1 + bool "Low energy UART1" + default n + select EFM32_HAVE_LEUART1 + select EFM32_UART + +endif diff --git a/arch/arm/src/efm32/chip.h b/arch/arm/src/efm32/chip.h index f7effac650..207ffa17c1 100644 --- a/arch/arm/src/efm32/chip.h +++ b/arch/arm/src/efm32/chip.h @@ -62,10 +62,6 @@ # endif #endif -/* Include the chip memory map. */ - -//#include "chip/efm32_memorymap.h" - /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/arch/arm/src/efm32/chip/efm32_memorymap.h b/arch/arm/src/efm32/chip/efm32_memorymap.h new file mode 100644 index 0000000000..62e0a24f82 --- /dev/null +++ b/arch/arm/src/efm32/chip/efm32_memorymap.h @@ -0,0 +1,56 @@ +/************************************************************************************ + * arch/arm/src/efm32/chip/efm32_memorymap.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_EFM32_EFM32TG) +# include "chip/efm32tg_memorymap.h" +#elif defined(CONFIG_EFM32_EFM32G) +# include "chip/efm32g_memorymap.h" +#elif defined(CONFIG_EFM32_EFM32GG) +# include "chip/efm32gg_memorymap.h" +#else +# error "Unsupported EFM32 memory map" +#endif + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_MEMORYMAP_H */ diff --git a/arch/arm/src/efm32/chip/efm32g_memorymap.h b/arch/arm/src/efm32/chip/efm32g_memorymap.h new file mode 100644 index 0000000000..595bd96887 --- /dev/null +++ b/arch/arm/src/efm32/chip/efm32g_memorymap.h @@ -0,0 +1,101 @@ +/************************************************************************************ + * arch/arm/src/efm32/chip/efm32g_memorymap.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: "EFM32G Reference Manual, Gecko Series", Energy Micro + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32G_MEMORYMAP_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32G_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Base Addresses */ + +#define EFM32_FLASH_MEM_BASE 0x00000000 /* FLASH base address */ +#define EFM32_RAM_CODE_MEM_BASE 0x10000000 /* RAM_CODE base address */ +#define EFM32_RAM_MEM_BASE 0x20000000 /* RAM base address */ +#define EFM32_PER_MEM_BASE 0x40000000 /* PER base address */ +#define EFM32_AES_MEM_BASE 0x400e0000 /* AES base address */ +#define EFM32_EBI0_BASE 0x80000000 /* EBI Region 0 */ +#define EFM32_EBI1_BASE 0x84000000 /* EBI Region 0 */ +#define EFM32_EBI2_BASE 0x88000000 /* EBI Region 0 */ +#define EFM32_EBI3_BASE 0x8c000000 /* EBI Region 0 */ +#define EFM32_CM3_BASE 0xe0000000 /* CM3 Peripherals */ + +/* Bit banding area */ + +#define EFM32_BITBAND_PER_BASE 0x42000000 /* Peripheral Address Space bit-band area */ +#define EFM32_BITBAND_RAM_BASE 0x22000000 /* SRAM Address Space bit-band area */ + +/* Flash and SRAM Addresses */ + +#define EFM32_FLASH_BASE 0x00000000 /* Flash Base Address */ +#define EFM32_SRAM_BASE 0x20000000 /* SRAM Base Address */ + +/* Peripheral Base Addresses */ + +#define EFM32_VCMP_BASE 0x40000000 /* VCMP base address */ +#define EFM32_ACMP0_BASE 0x40001000 /* ACMP0 base address */ +#define EFM32_ACMP1_BASE 0x40001400 /* ACMP1 base address */ +#define EFM32_ADC0_BASE 0x40002000 /* ADC0 base address */ +#define EFM32_DAC0_BASE 0x40004000 /* DAC0 base address */ +#define EFM32_GPIO_BASE 0x40006000 /* GPIO base address */ +#define EFM32_I2C0_BASE 0x4000a000 /* I2C0 base address */ +#define EFM32_USART0_BASE 0x4000c000 /* USART0 base address */ +#define EFM32_USART1_BASE 0x4000c400 /* USART1 base address */ +#define EFM32_USART2_BASE 0x4000c800 /* USART2 base address */ +#define EFM32_UART0_BASE 0x4000e00 /* UART0 base address */ +#define EFM32_TIMER0_BASE 0x40010000 /* TIMER0 base address */ +#define EFM32_TIMER1_BASE 0x40010400 /* TIMER1 base address */ +#define EFM32_TIMER2_BASE 0x40010800 /* TIMER2 base address */ +#define EFM32_RTC_BASE 0x40080000 /* RTC base address */ +#define EFM32_LETIMER0_BASE 0x40082000 /* LETIMER0 base address */ +#define EFM32_LEUART0_BASE 0x40084000 /* LEUART0 base address */ +#define EFM32_LEUART1_BASE 0x40084400 /* LEUART0 base address */ +#define EFM32_PCNT0_BASE 0x40086000 /* PCNT0 base address */ +#define EFM32_PCNT1_BASE 0x40086400 /* PCNT1 base address */ +#define EFM32_PCNT2_BASE 0x40086800 /* PCNT2 base address */ +#define EFM32_WDOG_BASE 0x40088000 /* WDOG base address */ +#define EFM32_LCD_BASE 0x4008a000 /* LCD base address */ +#define EFM32_MSC_BASE 0x400c0000 /* MSC base address */ +#define EFM32_DMA_BASE 0x400c2000 /* DMA base address */ +#define EFM32_EMU_BASE 0x400c6000 /* EMU base address */ +#define EFM32_CMU_BASE 0x400c8000 /* CMU base address */ +#define EFM32_RMU_BASE 0x400ca000 /* RMU base address */ +#define EFM32_PRS_BASE 0x400cc000 /* PRS base address */ +#define EFM32_AES_BASE 0x400e0000 /* AES base address */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32G_MEMORYMAP_H */ diff --git a/arch/arm/src/efm32/chip/efm32gg_memorymap.h b/arch/arm/src/efm32/chip/efm32gg_memorymap.h new file mode 100644 index 0000000000..b57c96fa3d --- /dev/null +++ b/arch/arm/src/efm32/chip/efm32gg_memorymap.h @@ -0,0 +1,140 @@ +/************************************************************************************ + * arch/arm/src/efm32/chip/efm32gg_memorymap.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Author: Pierre-noel Bouteville + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32GG_MEMORYMAP_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32GG_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Base Addresses */ + +#define EFM32_FLASH_MEM_BASE 0x00000000 /* FLASH base address */ +# define EFM32_FLASH_MEM_BITS 0x00000028 /* FLASH used bits */ +#define EFM32_RAM_CODE_MEM_BASE 0x10000000 /* RAM_CODE base address */ +# define EFM32_RAM_CODE_MEM_BITS 0x00000014 /* RAM_CODE used bits */ +#define EFM32_RAM_MEM_BASE 0x20000000 /* RAM base address */ +# define EFM32_RAM_MEM_BITS 0x00000018 /* RAM used bits */ +#define EFM32_PER_MEM_BASE 0x40000000 /* PER base address */ +# define EFM32_PER_MEM_BITS 0x00000020 /* PER used bits */ +#define EFM32_AES_MEM_BASE 0x400e0000 /* AES base address */ +# define EFM32_AES_MEM_BITS 0x00000010 /* AES used bits */ + +/* Bit banding area */ + +#define EFM32_BITBAND_PER_BASE 0x42000000 /* Peripheral Address Space bit-band area */ +#define EFM32_BITBAND_RAM_BASE 0x22000000 /* SRAM Address Space bit-band area */ + +/* Flash and SRAM Addresses */ + +#define EFM32_FLASH_BASE 0x00000000 /* Flash Base Address */ +#define EFM32_SRAM_BASE 0x20000000 /* SRAM Base Address */ + +/* Peripheral Base Addresses */ + +#define EFM32_VCMP_BASE 0x40000000 /* VCMP base address */ +#define EFM32_ACMP0_BASE 0x40001000 /* ACMP0 base address */ +#define EFM32_ACMP1_BASE 0x40001400 /* ACMP1 base address */ +#define EFM32_ADC0_BASE 0x40002000 /* ADC0 base address */ +#define EFM32_DAC0_BASE 0x40004000 /* DAC0 base address */ +#define EFM32_GPIO_BASE 0x40006000 /* GPIO base address */ +#define EFM32_EBI_BASE 0x40008000 /* EBI base address */ +#define EFM32_I2C0_BASE 0x4000a000 /* I2C0 base address */ +#define EFM32_I2C1_BASE 0x4000a400 /* I2C0 base address */ +#define EFM32_USART0_BASE 0x4000c000 /* USART0 base address */ +#define EFM32_USART1_BASE 0x4000c400 /* USART1 base address */ +#define EFM32_USART2_BASE 0x4000c800 /* USART2 base address */ +#define EFM32_UART0_BASE 0x4000e000 /* UART0 base address */ +#define EFM32_UART1_BASE 0x4000e400 /* UART1 base address */ +#define EFM32_TIMER0_BASE 0x40010000 /* TIMER0 base address */ +#define EFM32_TIMER1_BASE 0x40010400 /* TIMER1 base address */ +#define EFM32_TIMER2_BASE 0x40010800 /* TIMER2 base address */ +#define EFM32_TIMER3_BASE 0x40010c00 /* TIMER3 base address */ +#define EFM32_RTC_BASE 0x40080000 /* RTC base address */ +#define EFM32_BCKRTC_BASE 0x40081000 /* BCKRTC base address */ +#define EFM32_LETIMER0_BASE 0x40082000 /* LETIMER0 base address */ +#define EFM32_LEUART0_BASE 0x40084000 /* LEUART0 base address */ +#define EFM32_LEUART1_BASE 0x40084400 /* LEUART1 base address */ +#define EFM32_PCNT0_BASE 0x40086000 /* PCNT0 base address */ +#define EFM32_PCNT1_BASE 0x40086400 /* PCNT1 base address */ +#define EFM32_PCNT2_BASE 0x40086800 /* PCNT2 base address */ +#define EFM32_WDOG_BASE 0x40088000 /* WDOG base address */ +#define EFM32_LCD_BASE 0x4008a000 /* LCD base address */ +#define EFM32_LESENSE_BASE 0x4008c000 /* LESENSE base address */ +#define EFM32_MSC_BASE 0x400c0000 /* MSC base address */ +#define EFM32_DMA_BASE 0x400c2000 /* DMA base address */ +#define EFM32_USB_BASE 0x400c4000 /* USB base address */ +#define EFM32_EMU_BASE 0x400c6000 /* EMU base address */ +#define EFM32_CMU_BASE 0x400c8000 /* CMU base address */ +#define EFM32_RMU_BASE 0x400ca000 /* RMU base address */ +#define EFM32_PRS_BASE 0x400cc000 /* PRS base address */ +#define EFM32_AES_BASE 0x400e0000 /* AES base address */ + +/* ROM specific region */ + +#define EFM32_ROMTABLE_BASE 0xe00fffd0 /* ROMTABLE base address */ + +/* Flash specific region */ + +#define EFM32_USERDATA_BASE 0x0fe00000 /* User data page base address */ +#define EFM32_LOCKBITS_BASE 0x0fe04000 /* Lock-bits page base address */ +#define EFM32_CALIBRATE_BASE 0x0fe08000 /* CALIBRATE base address */ +#define EFM32_DEVINFO_BASE 0x0fe081b0 /* DEVINFO base address */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32GG_MEMORYMAP_H */ diff --git a/arch/arm/src/efm32/chip/efm32tg_memorymap.h b/arch/arm/src/efm32/chip/efm32tg_memorymap.h new file mode 100644 index 0000000000..d4755d62dc --- /dev/null +++ b/arch/arm/src/efm32/chip/efm32tg_memorymap.h @@ -0,0 +1,128 @@ +/************************************************************************************ + * arch/arm/src/efm32/chip/efm32tg_memorymap.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Author: Pierre-noel Bouteville + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM3TG_MEMORYMAP_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM3TG_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Base addresses */ + +#define EFM32_FLASH_MEM_BASE 0x00000000 /* FLASH base address */ +# define EFM32_FLASH_MEM_BITS 0x00000028 /* FLASH used bits */ +#define EFM32_RAM_CODE_MEM_BASE 0x10000000 /* RAM_CODE base address */ +# define EFM32_RAM_CODE_MEM_BITS 0x00000014 /* RAM_CODE used bits */ +#define EFM32_RAM_MEM_BASE 0x20000000 /* RAM base address */ +# define EFM32_RAM_MEM_BITS 0x00000018 /* RAM used bits */ +#define EFM32_PER_MEM_BASE 0x40000000 /* PER base address */ +# define EFM32_PER_MEM_BITS 0x00000020 /* PER used bits */ +#define EFM32_AES_MEM_BASE 0x400e0000 /* AES base address */ +# define EFM32_AES_MEM_BITS 0x00000010 /* AES used bits */ + +/* Bit banding area */ + +#define EFM32_BITBAND_PER_BASE 0x42000000 /* Peripheral Address Space bit-band area */ +#define EFM32_BITBAND_RAM_BASE 0x22000000 /* SRAM Address Space bit-band area */ + +/* Flash and SRAM Addresses */ + +#define EFM32_FLASH_BASE 0x00000000 /* Flash Base Address */ +#define EFM32_SRAM_BASE 0x20000000 /* SRAM Base Address */ + +/* Peripheral base address */ + +#define EFM32_VCMP_BASE 0x40000000 /* VCMP base address */ +#define EFM32_ACMP0_BASE 0x40001000 /* ACMP0 base address */ +#define EFM32_ACMP1_BASE 0x40001400 /* ACMP1 base address */ +#define EFM32_ADC0_BASE 0x40002000 /* ADC0 base address */ +#define EFM32_DAC0_BASE 0x40004000 /* DAC0 base address */ +#define EFM32_GPIO_BASE 0x40006000 /* GPIO base address */ +#define EFM32_I2C0_BASE 0x4000a000 /* I2C0 base address */ +#define EFM32_USART0_BASE 0x4000c000 /* USART0 base address */ +#define EFM32_USART1_BASE 0x4000c400 /* USART1 base address */ +#define EFM32_TIMER0_BASE 0x40010000 /* TIMER0 base address */ +#define EFM32_TIMER1_BASE 0x40010400 /* TIMER1 base address */ +#define EFM32_RTC_BASE 0x40080000 /* RTC base address */ +#define EFM32_LEUART0_BASE 0x40084000 /* LEUART0 base address */ +#define EFM32_LETIMER0_BASE 0x40082000 /* LETIMER0 base address */ +#define EFM32_PCNT0_BASE 0x40086000 /* PCNT0 base address */ +#define EFM32_WDOG_BASE 0x40088000 /* WDOG base address */ +#define EFM32_LCD_BASE 0x4008a000 /* LCD base address */ +#define EFM32_LESENSE_BASE 0x4008c000 /* LESENSE base address */ +#define EFM32_MSC_BASE 0x400c0000 /* MSC base address */ +#define EFM32_DMA_BASE 0x400c2000 /* DMA base address */ +#define EFM32_CMU_BASE 0x400c8000 /* CMU base address */ +#define EFM32_EMU_BASE 0x400c6000 /* EMU base address */ +#define EFM32_RMU_BASE 0x400ca000 /* RMU base address */ +#define EFM32_PRS_BASE 0x400cc000 /* PRS base address */ +#define EFM32_AES_BASE 0x400e0000 /* AES base address */ + +/* ROM specific region */ + +#define EFM32_ROMTABLE_BASE 0xe00fffd0 /* ROMTABLE base address */ + +/* Flash specific region */ + +#define EFM32_USERDATA_BASE 0x0fe00000 /* User data page base address */ +#define EFM32_LOCKBITS_BASE 0x0fe04000 /* Lock-bits page base address */ +#define EFM32_CALIBRATE_BASE 0x0fe08000 /* CALIBRATE base address */ +#define EFM32_DEVINFO_BASE 0x0fe081b0 /* DEVINFO base address */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM3TG_MEMORYMAP_H */ diff --git a/configs/efm32-g8xx-stk/README.txt b/configs/efm32-g8xx-stk/README.txt index 284f7d745f..b81df54ff3 100644 --- a/configs/efm32-g8xx-stk/README.txt +++ b/configs/efm32-g8xx-stk/README.txt @@ -57,6 +57,55 @@ LEDs on a small proportion of the time. *** LED2 may also flicker normally if signals are processed. +Serial Console +============== + + The EFM32G890F128 support the following options for serial output: + + ------- -- ---- + US0_RX #0 PE11 + US0_RX #1 PE6 + US0_RX #2 PC10 + + US0_TX #0 PE10 + US0_TX #1 PE7 + US0_TX #2 PC11 + ------- -- ---- + US1_RX #0 PC1 + US1_RX #1 PD1 + + US1_TX #0 PC0 + US1_TX #1 PD0 + ------- -- ---- + US2_RX #0 PC3 + US2_RX #1 PB4 + + US2_TX #0 PC2 + US2_TX #1 PB3 + ------- -- ---- + U0_RX #1 PE1 + U0_RX #2 PA4 + + U0_TX #0 PF6 + U0_TX #1 PE0 + U0_TX #2 PA3 + U0_TX #3 PC14 + ------- -- ---- + LEU0_RX #0 PD5 + LEU0_RX #1 PB14 + LEU0_RX #2 PE15 + + LEU0_TX #0 PD4 + LEU0_TX #1 PB13 + LEU0_TX #2 PE14 + ------- -- ---- + LEU1_RX #0 PC7 + LEU1_RX #1 PA6 + + LEU1_TX #0 PC6 + LEU1_TX #1 PA5 + ------- -- ---- + Configurations ============== Each EFM32 Gecko Starter Kit configuration is maintained in a sub-director