Add UDPHS header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2502 42af7a65-404d-4744-a932-0658087f49c3
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# define SAM3U_USART2_BASE 0x40098000 /* 0x40098000-0x4009bfff: USART2 */
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# define SAM3U_USART3_BASE 0x4009c000 /* 0x4009c000-0x4009ffff: USART3 */
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/* 0x400a0000-0x400a3fff: Reserved */
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# define SAM3U_UDPHPS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: USB Device High Speed */
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# define SAM3U_UDPHS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: USB Device High Speed */
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# define SAM3U_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: 12-bit ADC Controller */
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# define SAM3U_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: 10-bit ADC Controller */
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# define SAM3U_DMAC_BASE 0x400b0000 /* 0x400b0000-0x400b3fff: DMA controller */
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370
arch/arm/src/sam3u/sam3u_udphs.h
Executable file
370
arch/arm/src/sam3u/sam3u_udphs.h
Executable file
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/****************************************************************************************
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* arch/arm/src/sam3u/sam3u_udphs.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H
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#define __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "sam3u_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* UDPHS register offsets ***************************************************************/
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#define SAM3U_UDPHS_CTRL_OFFSET 0x00 /* UDPHS Control Register */
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#define SAM3U_UDPHS_FNUM_OFFSET 0x04 /* UDPHS Frame Number Register */
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/* 0x08-0x0C: Reserved */
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#define SAM3U_UDPHS_IEN_OFFSET 0x10 /* UDPHS Interrupt Enable Register */
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#define SAM3U_UDPHS_INTSTA_OFFSET 0x14 /* UDPHS Interrupt Status Register */
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#define SAM3U_UDPHS_CLRINT_OFFSET 0x18 /* UDPHS Clear Interrupt Register */
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#define SAM3U_UDPHS_EPTRST_OFFSET 0x1c /* UDPHS Endpoints Reset Register */
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/* 0x20-0xcc: Reserved */
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#define SAM3U_UDPHS_TST_OFFSET 0xe0 /* UDPHS Test Register */
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/* 0xE4-0xE8: Reserved */
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#define SAM3U_UDPHS_IPNAME1_OFFSET 0xf0 /* UDPHS Name1 Register */
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#define SAM3U_UDPHS_IPNAME2_OFFSET 0xf4 /* UDPHS Name2 Register */
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#define SAM3U_UDPHS_IPFEATURES_OFFSET 0xf8 /* UDPHS Features Register */
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/* Endpoint registers: Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180,
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* 0x1a0, and 0x1c0
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*/
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#define SAM3U_UDPHSEP_OFFSET(n) (0x100+((n)<<5))
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#define SAM3U_UDPHSEP_CFG_OFFSET 0x00 /* UDPHS Endpoint Configuration Register */
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#define SAM3U_UDPHSEP_CTLENB_OFFSET 0x04 /* UDPHS Endpoint Control Enable Register */
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#define SAM3U_UDPHSEP_CTLDIS_OFFSET 0x08 /* UDPHS Endpoint Control Disable Register */
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#define SAM3U_UDPHSEP_CTL_OFFSET 0x0c /* UDPHS Endpoint Control Register */
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/* 0x10: Reserved */
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#define SAM3U_UDPHSEP_SETSTA_OFFSET 0x14 /* UDPHS Endpoint Set Status Register */
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#define SAM3U_UDPHSEP_CLRSTA_OFFSET 0x18 /* UDPHS Endpoint Clear Status Register */
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#define SAM3U_UDPHSEP_STA_OFFSET 0x1c /* UDPHS Endpoint Status Register */
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/* 0x1e0-0x300: Reserved */
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/* 0x300-0x30c: Reserved */
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/* DMA Channel Registers: Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and
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* 0x360. NOTE that there is no DMA channel 0.
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*/
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#define SAM3U_UDPHSDMA_OFFSET(n) (0x310+((n)<<4))
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#define SAM3U_UDPHSDMA_NXTDSC_OFFSET 0x00 /* UDPHS DMA Next Descriptor Address Register */
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#define SAM3U_UDPHSDMA_ADDRESS_OFFSET 0x04 /* UDPHS DMA Channel Address Register */
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#define SAM3U_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */
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#define SAM3U_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */
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/* UDPHS register adresses **************************************************************/
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#define SAM3U_UDPHS_CTRL (SAM3U_UDPHS_BASE+SAM3U_UDPHS_CTRL_OFFSET)
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#define SAM3U_UDPHS_FNUM (SAM3U_UDPHS_BASE+SAM3U_UDPHS_FNUM_OFFSET)
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#define SAM3U_UDPHS_IEN (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IEN_OFFSET)
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#define SAM3U_UDPHS_INTSTA (SAM3U_UDPHS_BASE+SAM3U_UDPHS_INTSTA_OFFSET)
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#define SAM3U_UDPHS_CLRINT (SAM3U_UDPHS_BASE+ SAM3U_UDPHS_CLRINT_OFFSET)
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#define SAM3U_UDPHS_EPTRST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_EPTRST_OFFSET)
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#define SAM3U_UDPHS_TST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_TST_OFFSET)
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#define SAM3U_UDPHS_IPNAME1 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME1_OFFSET)
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#define SAM3U_UDPHS_IPNAME2 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME2_OFFSET)
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#define SAM3U_UDPHS_IPFEATURES (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPFEATURES_OFFSET)
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/* Endpoint registers */
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#define SAM3U_UDPHSEP_BASE(n)) (SAM3U_UDPHS_BASE+SAM3U_UDPHSEP_OFFSET(n))
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#define SAM3U_UDPHSEP_CFG(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CFG_OFFSET)
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#define SAM3U_UDPHSEP_CTLENB(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLENB_OFFSET)
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#define SAM3U_UDPHSEP_CTLDIS(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLDIS_OFFSET)
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#define SAM3U_UDPHSEP_CTL(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTL_OFFSET)
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#define SAM3U_UDPHSEP_SETSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_SETSTA_OFFSET)
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#define SAM3U_UDPHSEP_CLRSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CLRSTA_OFFSET)
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#define SAM3U_UDPHSEP_STA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_STA_OFFSET)
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/* DMA Channel Registers*/
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#define SAM3U_UDPHSDMA_BASE(n) (SAM3U_UDPHS_BASE+SAM3U_UDPHSDMA_OFFSET(n))
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#define SAM3U_UDPHSDMA_NXTDSC(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_NXTDSC_OFFSET)
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#define SAM3U_UDPHSDMA_ADDRESS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_ADDRESS_OFFSET)
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#define SAM3U_UDPHSDMA_CONTROL(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_CONTROL_OFFSET)
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#define SAM3U_UDPHSDMA_STATUS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_STATUS_OFFSET)
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/* UDPHS register bit definitions *******************************************************/
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/* UDPHS Control Register */
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#define UDPHS_CTRL_DEVADDR_SHIFT (0) /* Bits 0-6: UDPHS Address */
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#define UDPHS_CTRL_DEVADDR_MASK (0x7f << UDPHS_CTRL_DEVADDR_SHIFT)
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#define UDPHS_CTRL_FADDREN (1 << 7) /* Bit 7: Function Address Enable */
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#define UDPHS_CTRL_ENUDPHS (1 << 8) /* Bit 8: UDPHS Enable */
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#define UDPHS_CTRL_DETACH (1 << 9) /* Bit 9: Detach Command */
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#define UDPHS_CTRL_REWAKEUP (1 << 10) /* Bit 10: Send Remote Wake Up */
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#define UDPHS_CTRL_PULLDDIS (1 << 11) /* Bit 11: Pull-Down Disable */
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/* UDPHS Frame Number Register */
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#define UDPHS_FNUM_MICROFRAMENUM_SHIFT (0) /* Bits 0-2: Microframe Num */
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#define UDPHS_FNUM_MICROFRAMENUM_MASK (7 << UDPHS_FNUM_MICROFRAMENUM_SHIFT)
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#define UDPHS_FNUM_FRAMENUMBER_SHIFT (3) /* Bits 3-7: Frame Number in Packet Field Formats */
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#define UDPHS_FNUM_FRAMENUMBER_MASK (31 << UDPHS_FNUM_FRAMENUMBER_SHIFT)
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#define UDPHS_FNUM_FNUMERR_SHIFT (8) /* Bits 8-13: Frame Number CRC Error */
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#define UDPHS_FNUM_FNUMERR_MASK (63 << UDPHS_FNUM_FNUMERR_SHIFT)
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/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, and UDPHS Clear
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* Interrupt Register common bit-field definitions
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*/
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#define USBPHS_INT_DETSUSPD (1 << 1) /* Bit 1: Suspend Interrupt (Common) */
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#define USBPHS_INT_MICROSOF (1 << 2) /* Bit 2: Micro-SOF Interrupt (Common) */
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#define USBPHS_INT_INTSOF (1 << 3) /* Bit 3: SOF Interrupt (Common) */
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#define USBPHS_INT_ENDRESET (1 << 4) /* Bit 4: End Of Reset Interrupt (Common) */
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#define USBPHS_INT_WAKEUP (1 << 5) /* Bit 5: Wake Up CPU Interrupt (Common) */
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#define USBPHS_INT_ENDOFRSM (1 << 6) /* Bit 6: End Of Resume Interrupt (Common) */
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#define USBPHS_INT_UPSTRRES (1 << 7) /* Bit 7: Upstream Resume Interrupt (Common) */
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#define USBPHS_INT_EPT(n) (1 << ((n)+8))
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#define USBPHS_INT_EPT0 (1 << 8) /* Bit 8: Endpoint 0 Interrupt (not Clear) */
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#define USBPHS_INT_EPT1 (1 << 9) /* Bit 9: Endpoint 1 Interrupt (not Clear) */
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#define USBPHS_INT_EPT2 (1 << 10) /* Bit 10: Endpoint 2 Interrupt (not Clear) */
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#define USBPHS_INT_EPT3 (1 << 11) /* Bit 11: Endpoint 3 Interrupt (not Clear) */
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#define USBPHS_INT_EPT4 (1 << 12) /* Bit 12: Endpoint 4 Interrupt (not Clear) */
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#define USBPHS_INT_EPT5 (1 << 13) /* Bit 13: Endpoint 5 Interrupt (not Clear) */
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#define USBPHS_INT_EPT6 (1 << 13) /* Bit 14: Endpoint 6 Interrupt (not Clear) */
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#define USBPHS_INT_DMA(n) (1<<((n)+24))
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#define USBPHS_INT_DMA1 (1 << 25) /* Bit 25: DMA Channel 1 Interrupt (not Clear) */
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#define USBPHS_INT_DMA2 (1 << 26) /* Bit 26: DMA Channel 2 Interrupt (not Clear) */
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#define USBPHS_INT_DMA3 (1 << 27) /* Bit 27: DMA Channel 3 Interrupt (not Clear) */
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#define USBPHS_INT_DMA4 (1 << 28) /* Bit 28: DMA Channel 4 Interrupt (not Clear) */
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#define USBPHS_INT_DMA5 (1 << 29) /* Bit 29: DMA Channel 5 Interrupt (not Clear) */
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#define USBPHS_INT_DMA6 (1 << 30) /* Bit 30: DMA Channel 6 Interrupt (not Clear) */
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/* UDPHS Endpoints Reset Register */
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#define UDPHS_EPTRST_EPT(n) (1<<(n)) /* Bit 0-6: Endpoint n Reset */
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/* UDPHS Test Register */
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#define UDPHS_TST_SPEEDCFG_SHIFT (0) /* Bits 0-1: Speed Configuration */
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#define UDPHS_TST_SPEEDCFG_MASK (3 << UDPHS_TST_SPEEDCFG_SHIFT)
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00 Normal Mode
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10 Force High Speed
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11 Force Full Speed
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#define UDPHS_TST_TSTJ (1 << 2) /* Bit 2: Test J Mode */
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#define UDPHS_TST_TSTK (1 << 3) /* Bit 3: Test K Mode */
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#define UDPHS_TST_TSTPKT (1 << 4) /* Bit 4: Test Packet Mo */
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#define UDPHS_TST_OPMODE2 (1 << 5) /* Bit 5: OpMode2 */
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/* UDPHS Features Register */
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#define UDPHS_IPFEATURES_EPTNBRMAX_SHIFT (0) /* Bits 0-3: Max Number of Endpoints */
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#define UDPHS_IPFEATURES_EPTNBRMAX_MASK (15 << UDPHS_IPFEATURES_EPTNBRMAX_SHIFT)
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#define UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT (4) /* Bits 4-6: Number of DMA Channels */
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#define UDPHS_IPFEATURES_DMACHANNELNBR_MASK (7 << UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT)
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#define UDPHS_IPFEATURES_DMABSIZ (1 << 7) /* Bit 7: DMA Buffer Size */
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#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT (8) /* Bits 8-11: DMA FIFO Depth in Words */
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#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_MASK (15 << UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT)
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# define UDPHS_IPFEATURES_DMAFIFOWDDEPTH(n) ((n)&15)
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#define UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT (12) /* Bits 12-14: DPRAM Size */
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#define UDPHS_IPFEATURES_FIFOMAXSIZE_MASK (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT)
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# define UDPHS_IPFEATURES_FIFOMAXSIZE_128b (0 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 128 bytes */
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# define UDPHS_IPFEATURES_FIFOMAXSIZE_256b (1 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 256 bytes */
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# define UDPHS_IPFEATURES_FIFOMAXSIZE_512b (2 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 512 bytes */
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# define UDPHS_IPFEATURES_FIFOMAXSIZE_1Kb (3 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 1024 bytes */
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# define UDPHS_IPFEATURES_FIFOMAXSIZE_2Kb (4 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 2048 bytes */
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# define UDPHS_IPFEATURES_FIFOMAXSIZE_4Kb (5 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 4096 bytes */
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# define UDPHS_IPFEATURES_FIFOMAXSIZE_8Kb (6 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 8192 bytes */
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# define UDPHS_IPFEATURES_FIFOMAXSIZE_16Kb (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 16384 bytes */
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#define UDPHS_IPFEATURES_BWDPRAM (1 << 15) /* Bit 15: DPRAM Byte Write Capability */
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#define UDPHS_IPFEATURES_DATAB168 (1 << 15) /* Bit 15: UTMI DataBus16_8 */
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#define UDPHS_IPFEATURES_ISOEPT(n) (1<<((n)+16)
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#define UDPHS_IPFEATURES_ISOEPT1 (1 << 17) /* Bit 17: EP1 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT2 (1 << 18) /* Bit 18: EP2 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT3 (1 << 19) /* Bit 19: EP3 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT4 (1 << 20) /* Bit 20: EP4 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT5 (1 << 21) /* Bit 21: EP5 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT6 (1 << 22) /* Bit 22: EP6 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT7 (1 << 23) /* Bit 23: EP7 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT8 (1 << 24) /* Bit 24: EP8 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT9 (1 << 25) /* Bit 25: EP9 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT0 (1 << 26) /* Bit 26: EP10 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT1 (1 << 27) /* Bit 27: EP11 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT2 (1 << 28) /* Bit 28: EP12 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT3 (1 << 29) /* Bit 29: EP13 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT4 (1 << 30) /* Bit 30: EP14 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT5 (1 << 31) /* Bit 31: EP15 High B/W Isoc Capability */
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/* UDPHS Endpoint Configuration Register (0-6) */
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#define UDPHSEP_CFG_SIZE_SHIFT (0) /* Bits 0-2: Endpoint Size */
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#define UDPHSEP_CFG_SIZE_MASK (7 << UDPHSEP_CFG_SIZE_SHIFT)
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# define UDPHSEP_CFG_SIZE_8b (0 << UDPHSEP_CFG_SIZE_SHIFT) /* 8 bytes */
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# define UDPHSEP_CFG_SIZE_16b (1 << UDPHSEP_CFG_SIZE_SHIFT) /* 16 bytes */
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# define UDPHSEP_CFG_SIZE_32b (2 << UDPHSEP_CFG_SIZE_SHIFT) /* 32 bytes */
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# define UDPHSEP_CFG_SIZE_16b (3 << UDPHSEP_CFG_SIZE_SHIFT) /* 64 bytes */
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# define UDPHSEP_CFG_SIZE_128b (4 << UDPHSEP_CFG_SIZE_SHIFT) /* 128 bytes */
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# define UDPHSEP_CFG_SIZE_256b (5 << UDPHSEP_CFG_SIZE_SHIFT) /* 256 bytes */
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# define UDPHSEP_CFG_SIZE_512b (6 << UDPHSEP_CFG_SIZE_SHIFT) /* 512 bytes */
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# define UDPHSEP_CFG_SIZE_1Kb (7 << UDPHSEP_CFG_SIZE_SHIFT) /* 1024 bytes */
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#define UDPHSEP_CFG_DIR (1 << 3) /* Bit 3: Endpoint Direction */
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#define UDPHSEP_CFG_TYPE_SHIFT (4) /* Bits 4-5: Endpoint Type */
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#define UDPHSEP_CFG_TYPE_MASK (3 << UDPHSEP_CFG_TYPE_SHIFT)
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# define UDPHSEP_CFG_TYPE_CNTRL (0 << UDPHSEP_CFG_TYPE_SHIFT) /* Control endpoint */
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# define UDPHSEP_CFG_TYPE_ISOC (1 << UDPHSEP_CFG_TYPE_SHIFT) /* Isochronous endpoint */
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# define UDPHSEP_CFG_TYPE_BULK (2 << UDPHSEP_CFG_TYPE_SHIFT) /* Bulk endpoint */
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# define UDPHSEP_CFG_TYPE_INTR (3 << UDPHSEP_CFG_TYPE_SHIFT) /* Interrupt endpoint */
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#define UDPHSEP_CFG_BKNUMBER_SHIFT (6) /* Bits 6-7: Number of Banks */
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#define UDPHSEP_CFG_BKNUMBER_MASK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT)
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# define UDPHSEP_CFG_BKNUMBER_0BANK (0 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Zero bank (unmapped) */
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||||
# define UDPHSEP_CFG_BKNUMBER_1BANK (1 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* One bank (bank 0) */
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# define UDPHSEP_CFG_BKNUMBER_2BANK (2 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Double bank (bank 0-1) */
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# define UDPHSEP_CFG_BKNUMBER_3BANK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Triple bank (bank 0-2) */
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#define UDPHSEP_CFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Of Transaction per Microframe */
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#define UDPHSEP_CFG_NBTRANS_MASK (3 << UDPHSEP_CFG_NBTRANS_SHIFT)
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||||
#define UDPHSEP_CFG_MAPD (1 << 31) /*Bit 31: Endpoint Mapped */
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||||
|
||||
/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control Disable Register,
|
||||
* and UDPHS Endpoint Control Register common bit-field definitions
|
||||
*/
|
||||
|
||||
#define UDPHSEP_INT_EPT (1 << 0) /* Bit 0: Endpoint Enable/Disable */
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||||
#define UDPHSEP_INT_AUTOVALID (1 << 1) /* Bit 1: Packet Auto-Valid */
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||||
#define UDPHSEP_INT_INTDISDMA (1 << 3) /* Bit 3: Interrupts Disable DMA */
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||||
#define UDPHSEP_INT_NYETDIS (1 << 4) /* Bit 4: NYET Disable (HS Bulk OUT EPs) */
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||||
#define UDPHSEP_INT_DATAXRX (1 << 6) /* Bit 6: DATAx Interrupt Enable (High B/W Isoc OUT EPs) */
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||||
#define UDPHSEP_INT_MDATARX (1 << 7) /* Bit 7: MDATA Interrupt Enable (High B/W Isoc OUT EPs) */
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||||
#define UDPHSEP_INT_ERROVFLW (1 << 8) /* Bit 8: Overflow Error Interrupt */
|
||||
#define UDPHSEP_INT_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Interrupt */
|
||||
#define UDPHSEP_INT_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Interrupt */
|
||||
#define UDPHSEP_INT_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Interrupt */
|
||||
#define UDPHSEP_INT_ERRTRANS (1 << 11) /* Bit 11: Transaction Error Interrupt */
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||||
#define UDPHSEP_INT_RXSETUP (1 << 12) /* Bit 12: Received SETUP Interrupt */
|
||||
#define UDPHSEP_INT_ERRFLISO (1 << 12) /* Bit 12: Error Flow Interrupt */
|
||||
#define UDPHSEP_INT_STALLSNT (1 << 13) /* Bit 13: Stall Sent Interrupt */
|
||||
#define UDPHSEP_INT_ERRCRISO (1 << 13) /* Bit 13: ISO CRC Error Error Interrupt */
|
||||
#define UDPHSEP_INT_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Interrupt */
|
||||
#define UDPHSEP_INT_NAKIN (1 << 14) /* Bit 14: NAKIN Interrupt */
|
||||
#define UDPHSEP_INT_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Interrupt */
|
||||
#define UDPHSEP_INT_NAKOUT (1 << 15) /* Bit 15: NAKOUT Interrupt */
|
||||
#define UDPHSEP_INT_BUSYBANK (1 << 18) /* Bit 18: Busy Bank Interrupt */
|
||||
#define UDPHSEP_INT_SHRTPCKT (1 << 31) /* Bit 31: Short Packet Send/Short Packet Interrupt */
|
||||
|
||||
/* UDPHS Endpoint Set Status Register */
|
||||
|
||||
#define UDPHSEP_SETSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Set */
|
||||
#define UDPHSEP_SETSTA_KILLBANK (1 << 9) /* Bit 9: KILL Bank Set (for IN Endpoint) */
|
||||
#define UDPHSEP_SETSTA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Set */
|
||||
|
||||
/* UDPHS Endpoint Clear Status Register */
|
||||
|
||||
#define UDPHSEP_CLRSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Clear */
|
||||
#define UDPHSEP_CLRSTA_TOGGLESQ (1 << 6) /* Bit 6: Data Toggle Clear */
|
||||
#define UDPHSEP_CLRSTA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Clear */
|
||||
#define UDPHSEP_CLRSTA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Clear */
|
||||
#define UDPHSEP_CLRSTA_RXSETUP (1 << 12) /* Bit 12: Received SETUP Clear */
|
||||
#define UDPHSEP_CLRSTA_ERRFLISO (1 << 12) /* Bit 12: Error Flow Clear */
|
||||
#define UDPHSEP_CLRSTA_STALL_NT (1 << 13) /* Bit 13: Stall Sent Clear */
|
||||
#define UDPHSEP_CLRSTA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Clear */
|
||||
#define UDPHSEP_CLRSTA_NAKIN (1 << 14) /* Bit 14: NAKIN Clear */
|
||||
#define UDPHSEP_CLRSTA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Clear */
|
||||
#define UDPHSEP_CLRSTA_NAKOUT (1 << 15) /* Bit 15: NAKOUT Clear */
|
||||
|
||||
/* UDPHS Endpoint Status Register */
|
||||
|
||||
#define UDPHSEP_STA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request */
|
||||
#define UDPHSEP_STA_TOGGLESQSTA_SHIFT (6) /* Bits 6-7: Toggle Sequencing */
|
||||
#define UDPHSEP_STA_TOGGLESQSTA_MASK (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT)
|
||||
# define UDPHSEP_STA_TOGGLESQSTA_DATA0 (0 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data0 */
|
||||
# define UDPHSEP_STA_TOGGLESQSTA_DATA1 (1 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data1 */
|
||||
# define UDPHSEP_STA_TOGGLESQSTA_DATA2 (2 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data2 (High B/W Isoc EP) */
|
||||
# define UDPHSEP_STA_TOGGLESQSTA_MDATA (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* MData (High B/W Isoc EP) */
|
||||
#define UDPHSEP_STA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */
|
||||
#define UDPHSEP_STA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data */
|
||||
#define UDPHSEP_STA_KILLBANK (1 << 9) /* Bit 9: KILL Bank */
|
||||
#define UDPHSEP_STA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete */
|
||||
#define UDPHSEP_STA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready */
|
||||
#define UDPHSEP_STA_ERRTRANS (1 << 11) /* Bit 11: Transaction Error */
|
||||
#define UDPHSEP_STA_RXSETUP (1 << 12) /* Bit 12: Received SETUP */
|
||||
#define UDPHSEP_STA_ERRFLISO (1 << 12) /* Bit 12: Error Flow */
|
||||
#define UDPHSEP_STA_STALLSNT (1 << 13) /* Bit 13: Stall Sent */
|
||||
#define UDPHSEP_STA_ERRCRISO (1 << 13) /* Bit 13: CRC ISO Error */
|
||||
#define UDPHSEP_STA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error */
|
||||
#define UDPHSEP_STA_NAKIN (1 << 14) /* Bit 14: NAK IN */
|
||||
#define UDPHSEP_STA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error */
|
||||
#define UDPHSEP_STA_NAKOUT (1 << 15) /* Bit 15: NAK OUT */
|
||||
#define UDPHSEP_STA_CURRENTBANK_SHIFT (16) /* Bits 16-17: Current Bank */
|
||||
#define UDPHSEP_STA_CURRENTBANK_MASK (3 << UDPHSEP_STA_CURRENTBANK_MASK)
|
||||
#define UDPHSEP_STA_CONTROLDIR_SHIFT (16) /* Bits 16-17: Control Direction */
|
||||
#define UDPHSEP_STA_CONTROLDIR_MASK (3 << UDPHSEP_STA_CONTROLDIR_SHIFT)
|
||||
#define UDPHSEP_STA_BUSYBANKSTA_SHIFT (18) /* Bits 18-19: Busy Bank Number */
|
||||
#define UDPHSEP_STA_BUSYBANKSTA_MASK (3 << UDPHSEP_STA_BUSYBANKSTA_SHIFT)
|
||||
#define UDPHSEP_STA_BYTECOUNT_SHIFT (20) /* Bits 20-23: UDPHS Byte Count */
|
||||
#define UDPHSEP_STA_BYTECOUNT_MASK (15 << UDPHSEP_STA_BYTECOUNT_SHIFT)
|
||||
#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet
|
||||
|
||||
/* UDPHS DMA Channel Control Register */
|
||||
|
||||
#define UDPHSDMA_CONTROL_CHANNENB (1 << 0) /* Bit 0: Channel Enable Command */
|
||||
#define UDPHSDMA_CONTROL_LDNXTDSC (1 << 1) /* Bit 1: Load Next Channel Xfr Desc Enable (Command) */
|
||||
#define UDPHSDMA_CONTROL_ENDTREN (1 << 2) /* Bit 2: End of Transfer Enable (Control) */
|
||||
#define UDPHSDMA_CONTROL_ENDBEN (1 << 3) /* Bit 3: End of Buffer Enable (Control) */
|
||||
#define UDPHSDMA_CONTROL_ENDTRIT (1 << 4) /* Bit 4: End of Transfer Interrupt Enable */
|
||||
#define UDPHSDMA_CONTROL_ENDBUFFIT (1 << 5) /* Bit 5: End of Buffer Interrupt Enable */
|
||||
#define UDPHSDMA_CONTROL_DESCLDIT (1 << 6) /* Bit 6: Descriptor Loaded Interrupt Enab */
|
||||
#define UDPHSDMA_CONTROL_BURSTLCK (1 << 7) /* Bit 7: Burst Lock Ena */
|
||||
#define UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT (16) /* Bits 16-31: Buffer Byte Length (Write-only) */
|
||||
#define UDPHSDMA_CONTROL_BUFFLENGTH_MASK (0xffff << UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT)
|
||||
|
||||
/* UDPHS DMA Channel Status Register */
|
||||
|
||||
#define UDPHSDMA_STATUS_CHANNENB (1 << 0) /* Bit 0: Channel Enable Status */
|
||||
#define UDPHSDMA_STATUS_CHANNACT (1 << 1) /* Bit 1: Channel Active Status */
|
||||
#define UDPHSDMA_STATUS_ENDTRST (1 << 4) /* Bit 4: End of Channel Transfer Status */
|
||||
#define UDPHSDMA_STATUS_ENDBFST (1 << 5) /* Bit 5: End of Channel Buffer Status */
|
||||
#define UDPHSDMA_STATUS_DESCLDST (1 << 6) /* Bit 6: Descriptor Loaded Status */
|
||||
#define UDPHSDMA_STATUS_BUFFCOUNT_SHIFT (16) /* Bits 16-31: Buffer Byte Count */
|
||||
#define UDPHSDMA_STATUS_BUFFCOUNT_MASK (0xffff << UDPHSDMA_STATUS_BUFFCOUNT_SHIFT)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H */
|
||||
Loading…
Reference in New Issue
Block a user