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riscv/esp32c3: Add ESP32-C3 WLAN netcard driver

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This commit is contained in:
Dong Heng 2021-03-08 18:00:09 +08:00 committed by Alan Carvalho de Assis
parent b2f5031e96
commit 458caf2732
22 changed files with 8365 additions and 27 deletions
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5
arch/risc-v/Kconfig
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@ -45,6 +45,11 @@ config ARCH_CHIP_ESP32C3
select RV32IM_HW_MULDIV
select ARCH_VECNOTIRQ
select ARCH_HAVE_RESET
select LIBC_ARCH_MEMCHR
select LIBC_ARCH_MEMCMP
select LIBC_ARCH_MEMCCMP
select LIBC_ARCH_MEMMOVE
select LIBC_ARCH_MEMSET
---help---
Espressif ESP32-C3 (RV32IMC).

4
arch/risc-v/include/esp32c3/irq.h
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@ -127,6 +127,10 @@
#define ESP32C3_CPUINT_MIN 1
#define ESP32C3_CPUINT_MAX 31
/* Reserved CPU interrupt for specific drivers */
#define ESP32C3_CPUINT_WMAC 1 /* Wi-Fi MAC */
/* IRQ numbers. */
/* ecall is dispatched like normal interrupts. It occupies an IRQ number. */

2
arch/risc-v/src/esp32c3/.gitignore vendored Normal file
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@ -0,0 +1,2 @@
/esp-wireless-drivers-3rdparty
/*.zip

94
arch/risc-v/src/esp32c3/Kconfig
View File

@ -152,6 +152,10 @@ config ESP32C3_CPU_FREQ_MHZ
default 80 if ESP32C3_CPU_FREQ_80
default 160 if ESP32C3_CPU_FREQ_160
config ESP32C3_RT_TIMER
bool "Real-time Timer"
default n
menu "ESP32-C3 Peripheral Support"
config ESP32C3_UART
@ -235,6 +239,16 @@ config ESP32C3_RWDT
to have the RTC module reset, please, use the Timers' Module WDTs.
They will only reset Main System.
config ESP32C3_WIRELESS
bool "Wireless"
default n
select NET
select ARCH_PHY_INTERRUPT
select ESP32C3_RT_TIMER
select ESP32C3_TIMER0
---help---
Enable Wireless support
endmenu # ESP32-C3 Peripheral Support
menu "I2C Configuration"
@ -285,4 +299,84 @@ endif # ESP32C3_UART1
endmenu
menu "Real-Time Timer"
depends on ESP32C3_RT_TIMER
config ESP32C3_RT_TIMER_TASK_NAME
string "Timer task name"
default "rt_timer"
config ESP32C3_RT_TIMER_TASK_PRIORITY
int "Timer task priority"
default 223 # Lower than high priority workqueue
config ESP32C3_RT_TIMER_TASK_STACK_SIZE
int "Timer task stack size"
default 2048
endmenu # Real-Time Timer
menu "Wi-Fi configuration"
depends on ESP32C3_WIRELESS
config ESP32C3_WIFI_STATIC_RXBUF_NUM
int "Wi-Fi static RX buffer number"
default 10
config ESP32C3_WIFI_DYNAMIC_RXBUF_NUM
int "Wi-Fi dynamic RX buffer number"
default 32
config ESP32C3_WIFI_DYNAMIC_TXBUF_NUM
int "Wi-Fi dynamic TX buffer number"
default 32
config ESP32C3_WIFI_TX_AMPDU
bool "Wi-Fi TX AMPDU"
default y
config ESP32C3_WIFI_RX_AMPDU
bool "Wi-Fi RX AMPDU"
default y
config ESP32C3_WIFI_RXBA_AMPDU_WZ
int "Wi-Fi RX BA AMPDU windown size"
default 6
config ESP32C3_WLAN_RXBUF_NUM
int "WLAN netcard RX buffer number"
default 16
config ESP32C3_WIFI_CONNECT_TIMEOUT
int "Connect timeout by second"
default 10
help
Max waiting time of connecting to AP.
config ESP32C3_WIFI_SAVE_PARAM
bool "Save Wi-Fi Parameters"
default n
depends on !DISABLE_MOUNTPOINT
help
If you enable this option, Wi-Fi adapter parameters will be saved
into the file system instead of computing them each time.
These parameters mainly contains:
- SSID
- Password
- BSSID
- PMK(compute when connecting)
- Author mode
- MAC address
- Wi-Fi hardware configuration parameters
config ESP32C3_WIFI_FS_MOUNTPT
string "Save Wi-Fi Parameters"
default "/mnt/esp/wifi"
depends on ESP32C3_WIFI_SAVE_PARAM
help
Mount point of Wi-Fi storage file system.
endmenu # ESP32C3_WIRELESS
endif # ARCH_CHIP_ESP32C3

41
arch/risc-v/src/esp32c3/Make.defs
View File

@ -75,4 +75,43 @@ CHIP_CSRCS += esp32c3_tim.c
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += esp32c3_tim_lowerhalf.c
endif
endif
endif
ifeq ($(CONFIG_ESP32C3_RT_TIMER),y)
CHIP_CSRCS += esp32c3_rt_timer.c
endif
ifeq ($(CONFIG_ESP32C3_WIRELESS),y)
WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty
WIRELESS_DRV_ID = 3cc7f67
WIRELESS_DRV_ZIP = $(WIRELESS_DRV_ID).zip
WIRELESS_DRV_URL = https://github.com/espressif/esp-wireless-drivers-3rdparty/archive
$(WIRELESS_DRV_ZIP):
$(Q) echo "Downloading: ESP Wireless Drivers"
$(Q) curl -L $(WIRELESS_DRV_URL)/$(WIRELESS_DRV_ZIP) -o chip/$(WIRELESS_DRV_ZIP)
chip/$(WIRELESS_DRV_UNPACK): $(WIRELESS_DRV_ZIP)
$(Q) echo "Unpacking: ESP Wireless Drivers"
$(Q) unzip -oqq chip/$(WIRELESS_DRV_ZIP) -d chip/
$(Q) mv chip/$(WIRELESS_DRV_UNPACK)-$(WIRELESS_DRV_ID)* chip/$(WIRELESS_DRV_UNPACK)
$(Q) touch chip/$(WIRELESS_DRV_UNPACK)
context:: chip/$(WIRELESS_DRV_UNPACK)
clean_context::
$(call DELFILE, chip/$(WIRELESS_DRV_ZIP))
$(call DELDIR, chip/$(WIRELESS_DRV_UNPACK))
INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include)
INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include$(DELIM)esp32c3)
CHIP_CSRCS += esp32c3_wlan.c esp32c3_wifi_adapter.c
EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)libs$(DELIM)esp32c3
EXTRA_LIBS += -lcore -lnet80211 -lpp -lsmartconfig -lcoexist -lespnow -lphy -lwpa_supplicant -lwapi
# Due to some Wi-Fi related libraries, the option is need to avoid linking too much
# unused functions.
LDFLAGS += --gc-sections
endif

95
arch/risc-v/src/esp32c3/esp32c3_irq.c
View File

@ -54,6 +54,18 @@
#define CPUINT_UNASSIGNED 0xff
/* Wi-Fi reserved CPU interrupt bit */
#ifdef CONFIG_ESP32C3_WIRELESS
# define CPUINT_WMAC_MAP (1 << ESP32C3_CPUINT_WMAC)
#else
# define CPUINT_WMAC_MAP 0
#endif
/* Reserved CPU interrupt bits */
#define CPUINT_RESERVED_MAPS (CPUINT_WMAC_MAP)
/****************************************************************************
* Public Data
****************************************************************************/
@ -82,6 +94,17 @@ void up_irqinitialize(void)
memset(g_cpuint_map, CPUINT_UNASSIGNED, ESP32C3_CPUINT_MAX);
/**
* Initialize specific driver's CPU interrupt ID:
* Object | CPU INT | Pheripheral
* | |
* Wi-Fi | 1 | 1
*/
#ifdef CONFIG_ESP32C3_WIRELESS
g_cpuint_map[ESP32C3_CPUINT_WMAC] = ESP32C3_PERIPH_WIFI_MAC_NMI;
#endif
/* Clear all peripheral interrupts from "bootloader" */
for (periphid = 0; periphid < ESP32C3_NPERIPHERALS; periphid++)
@ -166,6 +189,50 @@ void up_disable_irq(int cpuint)
leave_critical_section(irqstate);
}
/****************************************************************************
* Name: esp32c3_bind_irq
*
* Description:
* Bind IRQ and resource with given parameters.
*
* Input Parameters:
* cpuint - CPU interrupt ID
* periphid - Peripheral ID
* prio - Interrupt priority
* flags - Interrupt flags
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32c3_bind_irq(uint8_t cpuint, uint8_t periphid, uint8_t prio,
uint32_t flags)
{
/* Disable the CPU interrupt. */
resetbits(1 << cpuint, INTERRUPT_CPU_INT_ENABLE_REG);
/* Set the interrupt priority. */
putreg32(prio, INTERRUPT_CPU_INT_PRI_0_REG + cpuint * 4);
/* Set the interrupt type (Edge or Level). */
if (flags & ESP32C3_INT_EDGE)
{
setbits(1 << cpuint, INTERRUPT_CPU_INT_TYPE_REG);
}
else
{
resetbits(1 << cpuint, INTERRUPT_CPU_INT_TYPE_REG);
}
/* Map the CPU interrupt ID to the peripheral. */
putreg32(cpuint, DR_REG_INTERRUPT_BASE + periphid * 4);
}
/****************************************************************************
* Name: esp32c3_request_irq
*
@ -198,6 +265,11 @@ int esp32c3_request_irq(uint8_t periphid, uint8_t prio, uint32_t flags)
/* Skip over enabled interrupts. NOTE: bit 0 is reserved. */
regval = getreg32(INTERRUPT_CPU_INT_ENABLE_REG);
/* Skip over reserved CPU interrupts */
regval |= CPUINT_RESERVED_MAPS;
for (cpuint = 1; cpuint <= ESP32C3_CPUINT_MAX; cpuint++)
{
if (!(regval & (1 << cpuint)))
@ -224,28 +296,9 @@ int esp32c3_request_irq(uint8_t periphid, uint8_t prio, uint32_t flags)
g_cpuint_map[cpuint] = periphid;
/* Set the interrupt priority. */
/* Configure IRQ */
putreg32(prio, INTERRUPT_CPU_INT_PRI_0_REG + cpuint * 4);
/* Set the interrupt type (Edge or Level). */
if (flags & ESP32C3_INT_EDGE)
{
setbits(1 << cpuint, INTERRUPT_CPU_INT_TYPE_REG);
}
else
{
resetbits(1 << cpuint, INTERRUPT_CPU_INT_TYPE_REG);
}
/* Map the CPU interrupt ID to the peripheral. */
putreg32(cpuint, DR_REG_INTERRUPT_BASE + periphid * 4);
/* Disable the CPU interrupt. */
resetbits(1 << cpuint, INTERRUPT_CPU_INT_ENABLE_REG);
esp32c3_bind_irq(cpuint, periphid, prio, flags);
}
else
{

20
arch/risc-v/src/esp32c3/esp32c3_irq.h
View File

@ -47,6 +47,26 @@
void up_irqinitialize(void);
/****************************************************************************
* Name: esp32c3_bind_irq
*
* Description:
* Bind IRQ and resource with given parameters.
*
* Input Parameters:
* cpuint - CPU interrupt ID
* periphid - Peripheral ID
* prio - Interrupt priority
* flags - Interrupt flags
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32c3_bind_irq(uint8_t cpuint, uint8_t periphid, uint8_t prio,
uint32_t flags);
/****************************************************************************
* Name: esp32c3_request_irq
*

678
arch/risc-v/src/esp32c3/esp32c3_rt_timer.c Normal file
View File

@ -0,0 +1,678 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/esp32c3_rt_timer.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this args for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <fcntl.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/kthread.h>
#include <nuttx/kmalloc.h>
#include <nuttx/semaphore.h>
#include "hardware/esp32c3_soc.h"
#include "esp32c3_tim.h"
#include "esp32c3_rt_timer.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_SCHED_HPWORKPRIORITY
# if CONFIG_ESP32C3_RT_TIMER_TASK_PRIORITY >= CONFIG_SCHED_HPWORKPRIORITY
# error "RT timer priority should be smaller that high-prio workqueue"
# endif
#endif
#define RT_TIMER_TASK_NAME CONFIG_ESP32C3_RT_TIMER_TASK_NAME
#define RT_TIMER_TASK_PRIORITY CONFIG_ESP32C3_RT_TIMER_TASK_PRIORITY
#define RT_TIMER_TASK_STACK_SIZE CONFIG_ESP32C3_RT_TIMER_TASK_STACK_SIZE
#define ESP32C3_TIMER_PRESCALER (APB_CLK_FREQ / (1000 * 1000))
/****************************************************************************
* Private Data
****************************************************************************/
static int s_pid;
static sem_t s_toutsem;
static struct list_node s_runlist;
static struct list_node s_toutlist;
static struct esp32c3_tim_dev_s *s_esp32c3_tim_dev;
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: start_rt_timer
*
* Description:
* Start timer by inserting it into running list and reset hardware timer
* alarm value if this timer in head of list.
*
* Input Parameters:
* timer - RT timer pointer
* timeout - Timeout value
* repeat - If the timer run repeat
*
* Returned Value:
* None.
*
****************************************************************************/
static void start_rt_timer(FAR struct rt_timer_s *timer,
uint64_t timeout,
bool repeat)
{
irqstate_t flags;
struct rt_timer_s *p;
bool inserted = false;
uint64_t counter;
struct esp32c3_tim_dev_s *tim = s_esp32c3_tim_dev;
flags = enter_critical_section();
/* Only idle timer can be started */
if (timer->state == RT_TIMER_IDLE)
{
/* Calculate the timer's alarm value */
ESP32C3_TIM_GETCTR(tim, &counter);
timer->timeout = timeout;
timer->alarm = timer->timeout + counter;
if (repeat)
{
timer->flags |= RT_TIMER_REPEAT;
}
else
{
timer->flags &= ~RT_TIMER_REPEAT;
}
/** Scan timer list and insert the new timer into previous
* node of timer whose alarm value is larger than new one
*/
list_for_every_entry(&s_runlist, p, struct rt_timer_s, list)
{
if (p->alarm > timer->alarm)
{
list_add_before(&p->list, &timer->list);
inserted = true;
break;
}
}
/* If not find a larger one, insert new timer into tail of list */
if (!inserted)
{
list_add_tail(&s_runlist, &timer->list);
}
timer->state = RT_TIMER_READY;
/* If this timer is in head of list */
if (timer == container_of(s_runlist.next, struct rt_timer_s, list))
{
/* Reset hardware timer alarm */
ESP32C3_TIM_SETALRVL(tim, timer->alarm);
ESP32C3_TIM_SETALRM(tim, true);
}
}
leave_critical_section(flags);
}
/****************************************************************************
* Name: stop_rt_timer
*
* Description:
* Stop timer by removing it from running list and reset hardware timer
* alarm value if this timer is in head of list.
*
* Input Parameters:
* timer - RT timer pointer
*
* Returned Value:
* None.
*
****************************************************************************/
static void stop_rt_timer(FAR struct rt_timer_s *timer)
{
irqstate_t flags;
bool ishead;
struct rt_timer_s *next_timer;
uint64_t alarm;
struct esp32c3_tim_dev_s *tim = s_esp32c3_tim_dev;
flags = enter_critical_section();
/**
* Function "start" can set timer to be repeat, and function "stop"
* should remove this feature although it is not in ready state.
*/
timer->flags &= ~RT_TIMER_REPEAT;
/* Only ready timer can be stopped */
if (timer->state == RT_TIMER_READY)
{
/* Check if timer is in head of list */
if (timer == container_of(s_runlist.next, struct rt_timer_s, list))
{
ishead = true;
}
else
{
ishead = false;
}
list_delete(&timer->list);
timer->state = RT_TIMER_IDLE;
/* If timer is in in head of list */
if (ishead)
{
/* If list is not empty */
if (!list_is_empty(&s_runlist))
{
/* Reset hardware timer alarm value to be next timer's */
next_timer = container_of(s_runlist.next,
struct rt_timer_s,
list);
alarm = next_timer->alarm;
ESP32C3_TIM_SETALRVL(tim, alarm);
ESP32C3_TIM_SETALRM(tim, true);
}
}
}
leave_critical_section(flags);
}
/****************************************************************************
* Name: delete_rt_timer
*
* Description:
* Delete timer by removing it from list, then set the timer's state
* to be "RT_TIMER_DELETE", inserting into work list to let rt-timer
* thread to delete it and free resource.
*
* Input Parameters:
* timer - RT timer pointer
*
* Returned Value:
* None.
*
****************************************************************************/
static void delete_rt_timer(FAR struct rt_timer_s *timer)
{
irqstate_t flags;
flags = enter_critical_section();
if (timer->state == RT_TIMER_READY)
{
stop_rt_timer(timer);
}
else if (timer->state == RT_TIMER_TIMEOUT)
{
list_delete(&timer->list);
}
else if (timer->state == RT_TIMER_DELETE)
{
goto exit;
}
list_add_after(&s_toutlist, &timer->list);
timer->state = RT_TIMER_DELETE;
exit:
leave_critical_section(flags);
}
/****************************************************************************
* Name: rt_timer_thread
*
* Description:
* RT timer working thread, it wait for a timeout semaphore, scan
* the timeout list and process all timers in this list.
*
* Input Parameters:
* argc - Not used
* argv - Not used
*
* Returned Value:
* 0.
*
****************************************************************************/
static int rt_timer_thread(int argc, FAR char *argv[])
{
int ret;
irqstate_t flags;
struct rt_timer_s *timer;
enum rt_timer_state_e raw_state;
while (1)
{
/* Waiting for timers timeout */
ret = nxsem_wait(&s_toutsem);
if (ret)
{
tmrerr("ERROR: Wait s_toutsem error=%d\n", ret);
assert(0);
}
/* Enter critical to check global timer timeout list */
flags = enter_critical_section();
/* Process all timers in list */
while (!list_is_empty(&s_toutlist))
{
/* Get first timer in list */
timer = container_of(s_toutlist.next, struct rt_timer_s, list);
/* Cache the raw state to decide how to deal with this timer */
raw_state = timer->state;
/* Delete timer from list */
list_delete(&timer->list);
/* Set timer's state to be let it to able to restart by user */
timer->state = RT_TIMER_IDLE;
/* Leave from critical to start to call "callback" function */
leave_critical_section(flags);
if (raw_state == RT_TIMER_TIMEOUT)
{
timer->callback(timer->arg);
}
else if (raw_state == RT_TIMER_DELETE)
{
kmm_free(timer);
}
/* Enter critical for next scanning list */
flags = enter_critical_section();
if (raw_state == RT_TIMER_TIMEOUT)
{
/* Check if timer is repeat */
if (timer->flags & RT_TIMER_REPEAT)
{
start_rt_timer(timer, timer->timeout, true);
}
}
}
leave_critical_section(flags);
}
return 0;
}
/****************************************************************************
* Name: rt_timer_isr
*
* Description:
* Hardware timer interrupt service function.
*
* Input Parameters:
* irq - Not used
* context - Not used
* arg - Not used
*
* Returned Value:
* 0.
*
****************************************************************************/
static int rt_timer_isr(int irq, void *context, void *arg)
{
irqstate_t flags;
struct rt_timer_s *timer;
uint64_t alarm;
uint64_t counter;
struct esp32c3_tim_dev_s *tim = s_esp32c3_tim_dev;
/* Clear interrupt register status */
ESP32C3_TIM_ACKINT(tim);
/* Wake up thread to process timeout timers */
nxsem_post(&s_toutsem);
flags = enter_critical_section();
/* Check if there is timer running */
if (!list_is_empty(&s_runlist))
{
/**
* When stop/delete timer, in the same time the hardware timer
* interrupt triggers, function "stop/delete" remove the timer
* from running list, so the 1st timer is not which triggers.
*/
timer = container_of(s_runlist.next, struct rt_timer_s, list);
ESP32C3_TIM_GETCTR(tim, &counter);
if (timer->alarm <= counter)
{
/**
* Remove first timer in running list and add it into
* timeout list.
*
* Set the timer's state to be RT_TIMER_TIMEOUT to avoid
* other operation.
*/
list_delete(&timer->list);
timer->state = RT_TIMER_TIMEOUT;
list_add_after(&s_toutlist, &timer->list);
/* Check if thers is timer running */
if (!list_is_empty(&s_runlist))
{
/* Reset hardware timer alarm with next timer's alarm value */
timer = container_of(s_runlist.next, struct rt_timer_s, list);
alarm = timer->alarm;
ESP32C3_TIM_SETALRVL(tim, alarm);
ESP32C3_TIM_SETALRM(tim, true);
}
}
}
leave_critical_section(flags);
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rt_timer_create
*
* Description:
* Create RT timer by into timer creation arguments
*
* Input Parameters:
* args - Input RT timer creation arguments
* timer_handle - Output RT timer handle pointer
*
* Returned Value:
* 0 is returned on success. Otherwise, a negated errno value is returned.
*
****************************************************************************/
int rt_timer_create(FAR const struct rt_timer_args_s *args,
FAR struct rt_timer_s **timer_handle)
{
struct rt_timer_s *timer;
timer = (struct rt_timer_s *)kmm_malloc(sizeof(*timer));
if (!timer)
{
tmrerr("ERROR: Failed to allocate %d bytes\n", sizeof(*timer));
return -ENOMEM;
}
timer->callback = args->callback;
timer->arg = args->arg;
timer->flags = RT_TIMER_NOFLAGS;
timer->state = RT_TIMER_IDLE;
list_initialize(&timer->list);
*timer_handle = timer;
return 0;
}
/****************************************************************************
* Name: rt_timer_start
*
* Description:
* Start RT timer.
*
* Input Parameters:
* timer - RT timer pointer
* timeout - Timeout value
* repeat - If the timer run repeat
*
* Returned Value:
* None
*
****************************************************************************/
void rt_timer_start(FAR struct rt_timer_s *timer,
uint64_t timeout,
bool repeat)
{
stop_rt_timer(timer);
start_rt_timer(timer, timeout, repeat);
}
/****************************************************************************
* Name: rt_timer_stop
*
* Description:
* Stop RT timer.
*
* Input Parameters:
* timer - RT timer pointer
*
* Returned Value:
* None
*
****************************************************************************/
void rt_timer_stop(FAR struct rt_timer_s *timer)
{
stop_rt_timer(timer);
}
/****************************************************************************
* Name: rt_timer_delete
*
* Description:
* Stop and delete RT timer.
*
* Input Parameters:
* timer - RT timer pointer
*
* Returned Value:
* None
*
****************************************************************************/
void rt_timer_delete(FAR struct rt_timer_s *timer)
{
delete_rt_timer(timer);
}
/****************************************************************************
* Name: rt_timer_time_us
*
* Description:
* Get time of RT timer by microsecond.
*
* Input Parameters:
* None
*
* Returned Value:
* Time of RT timer by microsecond.
*
****************************************************************************/
uint64_t rt_timer_time_us(void)
{
uint64_t counter;
struct esp32c3_tim_dev_s *tim = s_esp32c3_tim_dev;
ESP32C3_TIM_GETCTR(tim, &counter);
return counter;
}
/****************************************************************************
* Name: esp32c3_rt_timer_init
*
* Description:
* Initialize ESP32-C3 RT timer.
*
* Input Parameters:
* None
*
* Returned Value:
* 0 is returned on success. Otherwise, a negated errno value is returned.
*
****************************************************************************/
int esp32c3_rt_timer_init(void)
{
int pid;
irqstate_t flags;
struct esp32c3_tim_dev_s *tim;
tim = esp32c3_tim0_init();
if (!tim)
{
tmrerr("ERROR: Failed to initialize ESP32 timer0\n");
return -EINVAL;
}
nxsem_init(&s_toutsem, 0, 0);
pid = kthread_create(RT_TIMER_TASK_NAME,
RT_TIMER_TASK_PRIORITY,
RT_TIMER_TASK_STACK_SIZE,
rt_timer_thread,
NULL);
if (pid < 0)
{
tmrerr("ERROR: Failed to create RT timer task error=%d\n", pid);
esp32c3_tim_deinit(tim);
return pid;
}
list_initialize(&s_runlist);
list_initialize(&s_toutlist);
s_esp32c3_tim_dev = tim;
s_pid = pid;
flags = enter_critical_section();
/**
* ESP32 hardware timer configuration:
* - 1 counter = 1us
* - Counter increase mode
* - Non-reload mode
*/
ESP32C3_TIM_SETPRE(tim, ESP32C3_TIMER_PRESCALER);
ESP32C3_TIM_SETMODE(tim, ESP32C3_TIM_MODE_UP);
ESP32C3_TIM_SETARLD(tim, false);
ESP32C3_TIM_CLEAR(tim);
ESP32C3_TIM_SETISR(tim, rt_timer_isr, NULL);
ESP32C3_TIM_ENABLEINT(tim);
ESP32C3_TIM_START(tim);
leave_critical_section(flags);
return 0;
}
/****************************************************************************
* Name: esp32c3_rt_timer_deinit
*
* Description:
* Deinitialize ESP32-C3 RT timer.
*
* Input Parameters:
* None
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32c3_rt_timer_deinit(void)
{
irqstate_t flags;
flags = enter_critical_section();
ESP32C3_TIM_STOP(s_esp32c3_tim_dev);
s_esp32c3_tim_dev = NULL;
leave_critical_section(flags);
kthread_delete(s_pid);
nxsem_destroy(&s_toutsem);
}

206
arch/risc-v/src/esp32c3/esp32c3_rt_timer.h Normal file
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@ -0,0 +1,206 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/esp32c3_rt_timer.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RT_TIMER_H
#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RT_TIMER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <sys/types.h>
#include <nuttx/list.h>
#define RT_TIMER_NOFLAGS (0) /* Timer support no feature */
#define RT_TIMER_REPEAT (1 << 0) /* Timer is repeat */
/**
* RT timer state
*/
enum rt_timer_state_e
{
RT_TIMER_IDLE, /* Timer is not counting */
RT_TIMER_READY, /* Timer is counting */
RT_TIMER_TIMEOUT, /* Timer is timeout */
RT_TIMER_DELETE /* Timer is to be delete */
};
/**
* RT timer data structure
*/
struct rt_timer_s
{
uint64_t timeout; /* Timeout value */
uint64_t alarm; /* Timeout period */
void (*callback)(void *arg); /* Callback function */
void *arg; /* Private data */
uint16_t flags; /* Support feature */
enum rt_timer_state_e state; /* Mark if timer is started */
struct list_node list; /* Working list */
};
/**
* RT timer creation arguments data structure
*/
struct rt_timer_args_s
{
void (*callback)(void *arg); /* Callback function */
void *arg; /* Private data */
};
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: rt_timer_create
*
* Description:
* Create RT timer by into timer creation arguments
*
* Input Parameters:
* args - Input RT timer creation arguments
* timer_handle - Output RT timer handle pointer
*
* Returned Value:
* 0 is returned on success. Otherwise, a negated errno value is returned.
*
****************************************************************************/
int rt_timer_create(const struct rt_timer_args_s *args,
struct rt_timer_s **timer_handle);
/****************************************************************************
* Name: rt_timer_start
*
* Description:
* Start RT timer.
*
* Input Parameters:
* timer - RT timer pointer
* timeout - Timeout value
* repeat - If the timer run repeat
*
* Returned Value:
* None
*
****************************************************************************/
void rt_timer_start(struct rt_timer_s *timer,
uint64_t timeout,
bool repeat);
/****************************************************************************
* Name: rt_timer_stop
*
* Description:
* Stop RT timer.
*
* Input Parameters:
* timer - RT timer pointer
*
* Returned Value:
* None
*
****************************************************************************/
void rt_timer_stop(struct rt_timer_s *timer);
/****************************************************************************
* Name: rt_timer_delete
*
* Description:
* Stop and delete RT timer.
*
* Input Parameters:
* timer - RT timer pointer
*
* Returned Value:
* None
*
****************************************************************************/
void rt_timer_delete(struct rt_timer_s *timer);
/****************************************************************************
* Name: rt_timer_time_us
*
* Description:
* Get time of RT timer by microsecond.
*
* Input Parameters:
* None
*
* Returned Value:
* Time of RT timer by microsecond.
*
****************************************************************************/
uint64_t rt_timer_time_us(void);
/****************************************************************************
* Name: esp32c3_rt_timer_init
*
* Description:
* Initialize ESP32-C3 RT timer.
*
* Input Parameters:
* None
*
* Returned Value:
* 0 is returned on success. Otherwise, a negated errno value is returned.
*
****************************************************************************/
int esp32c3_rt_timer_init(void);
/****************************************************************************
* Name: esp32c3_rt_timer_deinit
*
* Description:
* Deinitialize ESP32-C3 RT timer.
*
* Input Parameters:
* None
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32c3_rt_timer_deinit(void);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RT_TIMER_H */

36
arch/risc-v/src/esp32c3/esp32c3_tim.c
View File

@ -685,7 +685,7 @@ FAR struct esp32c3_tim_dev_s *esp32c3_tim_init(int timer)
switch (timer)
{
#if defined(CONFIG_ESP32C3_TIMER0)
#if defined(CONFIG_ESP32C3_TIMER0) && !defined(CONFIG_ESP32C3_RT_TIMER)
case 0:
{
tim = &g_esp32c3_tim0_priv;
@ -738,3 +738,37 @@ void esp32c3_tim_deinit(FAR struct esp32c3_tim_dev_s *dev)
tim = (FAR struct esp32c3_tim_priv_s *)dev;
tim->inuse = false;
}
/****************************************************************************
* Name: esp32c3_tim0_init
*
* Description:
* Initialize TIMER0 device, if software real-time timer
* (CONFIG_ESP32C3_RT_TIMER) is enabled.
*
* Parameters:
* None
*
* Returned Values:
* If the initialization is successful, return a pointer to the timer
* driver struct associated to that timer instance.
* In case it fails, return NULL.
*
****************************************************************************/
#ifdef CONFIG_ESP32C3_RT_TIMER
FAR struct esp32c3_tim_dev_s *esp32c3_tim0_init(void)
{
FAR struct esp32c3_tim_priv_s *tim = &g_esp32c3_tim0_priv;
if (tim->inuse == true)
{
tmrerr("ERROR: TIMER0 is already in use\n");
tim = NULL;
}
return (FAR struct esp32c3_tim_dev_s *)tim;
}
#endif

8
arch/risc-v/src/esp32c3/esp32c3_tim.h
View File

@ -135,4 +135,12 @@ struct esp32c3_tim_ops_s
FAR struct esp32c3_tim_dev_s *esp32c3_tim_init(int timer);
void esp32c3_tim_deinit(FAR struct esp32c3_tim_dev_s *dev);
/****************************************************************************
* The Timer0 is used by RT-Timer of wireless driver, so please don't use it
* in any other components.
****************************************************************************/
#ifdef CONFIG_ESP32C3_RT_TIMER
FAR struct esp32c3_tim_dev_s *esp32c3_tim0_init(void);
#endif
#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TIM_H */

4
arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.c
View File

@ -97,7 +97,7 @@ static const struct timer_ops_s g_esp32c3_timer_ops =
.ioctl = NULL,
};
#ifdef CONFIG_ESP32C3_TIMER0
#if defined(CONFIG_ESP32C3_TIMER0) && !defined(CONFIG_ESP32C3_RT_TIMER)
/* TIMER0 lower-half */
static struct esp32c3_timer_lowerhalf_s g_esp32c3_timer0_lowerhalf =
@ -500,7 +500,7 @@ int esp32c3_timer_initialize(FAR const char *devpath, uint8_t timer)
switch (timer)
{
#ifdef CONFIG_ESP32C3_TIMER0
#if defined(CONFIG_ESP32C3_TIMER0) && !defined(CONFIG_ESP32C3_RT_TIMER)
case 0:
{
lower = &g_esp32c3_timer0_lowerhalf;

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arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c Normal file
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242
arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.h Normal file
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@ -0,0 +1,242 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIFI_ADAPTER_H
#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIFI_ADAPTER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Wi-Fi event ID */
enum wifi_adpt_evt_e
{
WIFI_ADPT_EVT_STA_START = 0,
WIFI_ADPT_EVT_STA_CONNECT,
WIFI_ADPT_EVT_STA_DISCONNECT,
WIFI_ADPT_EVT_STA_AUTHMODE_CHANGE,
WIFI_ADPT_EVT_STA_STOP,
WIFI_ADPT_EVT_MAX,
};
/* Wi-Fi event callback function */
typedef void (*wifi_evt_cb_t)(void *p);
typedef void (* wifi_tx_done_cb_t)(uint8_t ifidx, uint8_t *data,
uint16_t *len, bool txstatus);
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp_wifi_adapter_init
*
* Description:
* Initialize ESP32 Wi-Fi adapter
*
* Input Parameters:
* None
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_adapter_init(void);
/****************************************************************************
* Name: esp_wifi_notify_subscribe
*
* Description:
* Enable event notification
*
* Input Parameters:
* pid - Task PID
* event - Signal event data pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_notify_subscribe(pid_t pid, FAR struct sigevent *event);
/****************************************************************************
* Name: esp_wifi_sta_send_data
*
* Description:
* Use Wi-Fi station interface to send 802.3 frame
*
* Input Parameters:
* pbuf - Packet buffer pointer
* len - Packet length
*
* Returned Value:
* 0 if success or others if fail
*
****************************************************************************/
int esp_wifi_sta_send_data(void *pbuf, uint32_t len);
/****************************************************************************
* Name: esp_wifi_sta_register_recv_cb
*
* Description:
* Register Wi-Fi receive packet callback function
*
* Input Parameters:
* input_cb - Receive callback function
*
* Returned Value:
* 0 if success or others if fail
*
****************************************************************************/
int esp_wifi_sta_register_recv_cb(int (*recv_cb)(void *buffer,
uint16_t len,
void *eb));
/****************************************************************************
* Name: esp_wifi_sta_read_mac
*
* Description:
* Read station interface MAC address from efuse
*
* Input Parameters:
* mac - MAC address buffer pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_sta_read_mac(uint8_t *mac);
/****************************************************************************
* Name: esp_wifi_free_eb
*
* Description:
* Free Wi-Fi receive callback input eb pointer
*
* Input Parameters:
* eb - Wi-Fi receive callback input eb pointer
*
* Returned Value:
* None
*
****************************************************************************/
void esp_wifi_free_eb(void *eb);
/****************************************************************************
* Name: esp_wifi_set_password
*
* Description:
* Set Wi-Fi password
*
* Input Parameters:
* pdata - Password buffer pointer
* len - Password length
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_set_password(const uint8_t *pdata, uint8_t len);
/****************************************************************************
* Name: esp_wifi_set_ssid
*
* Description:
* Set Wi-Fi SSID
*
* Input Parameters:
* pdata - SSID buffer pointer
* len - SSID length
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_set_ssid(const uint8_t *pdata, uint8_t len);
/****************************************************************************
* Name: esp_wifi_connect_internal
*
* Description:
* Trigger Wi-Fi connection action
*
* Input Parameters:
* None
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_connect_internal(void);
/****************************************************************************
* Name: esp_wifi_sta_register_txdone_cb
*
* Description:
* Register the txDone callback function of type wifi_tx_done_cb_t
*
* Input Parameters:
* callback - The callback function
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_sta_register_txdone_cb(void *callback);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIFI_ADAPTER_H */

1487
arch/risc-v/src/esp32c3/esp32c3_wlan.c Normal file
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67
arch/risc-v/src/esp32c3/esp32c3_wlan.h Normal file
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@ -0,0 +1,67 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/esp32c3_wlan.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WLAN_H
#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WLAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32c3_wlan_sta_initialize
*
* Description:
* Initialize the ESP32-C3 WLAN station netcard driver
*
* Input Parameters:
* None
*
* Returned Value:
* OK on success; Negated errno on failure.
*
****************************************************************************/
int esp32c3_wlan_sta_initialize(void);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WLAN_H */

644
arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h Normal file
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@ -0,0 +1,644 @@
/****************************************************************************
* arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSCON_H
#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSCON_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32c3_memorymap.h"
#include "esp32c3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000)
/* SYSCON_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
#define SYSCON_SOC_CLK_SEL 0x00000003
#define SYSCON_SOC_CLK_SEL_M ((SYSCON_SOC_CLK_SEL_V) << (SYSCON_SOC_CLK_SEL_S))
#define SYSCON_SOC_CLK_SEL_V 0x3
#define SYSCON_SOC_CLK_SEL_S 14
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
#define SYSCON_RST_TICK_CNT (BIT(12))
#define SYSCON_RST_TICK_CNT_M (BIT(12))
#define SYSCON_RST_TICK_CNT_V 0x1
#define SYSCON_RST_TICK_CNT_S 12
/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
#define SYSCON_CLK_EN (BIT(11))
#define SYSCON_CLK_EN_M (BIT(11))
#define SYSCON_CLK_EN_V 0x1
#define SYSCON_CLK_EN_S 11
/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
#define SYSCON_CLK_320M_EN (BIT(10))
#define SYSCON_CLK_320M_EN_M (BIT(10))
#define SYSCON_CLK_320M_EN_V 0x1
#define SYSCON_CLK_320M_EN_S 10
/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
#define SYSCON_PRE_DIV_CNT 0x000003FF
#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V) << (SYSCON_PRE_DIV_CNT_S))
#define SYSCON_PRE_DIV_CNT_V 0x3FF
#define SYSCON_PRE_DIV_CNT_S 0
#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004)
/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
#define SYSCON_TICK_ENABLE (BIT(16))
#define SYSCON_TICK_ENABLE_M (BIT(16))
#define SYSCON_TICK_ENABLE_V 0x1
#define SYSCON_TICK_ENABLE_S 16
/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
#define SYSCON_CK8M_TICK_NUM 0x000000FF
#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V) << (SYSCON_CK8M_TICK_NUM_S))
#define SYSCON_CK8M_TICK_NUM_V 0xFF
#define SYSCON_CK8M_TICK_NUM_S 8
/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
#define SYSCON_XTAL_TICK_NUM 0x000000FF
#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V) << (SYSCON_XTAL_TICK_NUM_S))
#define SYSCON_XTAL_TICK_NUM_V 0xFF
#define SYSCON_XTAL_TICK_NUM_S 0
#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008)
/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
#define SYSCON_CLK_XTAL_OEN (BIT(10))
#define SYSCON_CLK_XTAL_OEN_M (BIT(10))
#define SYSCON_CLK_XTAL_OEN_V 0x1
#define SYSCON_CLK_XTAL_OEN_S 10
/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
#define SYSCON_CLK40X_BB_OEN (BIT(9))
#define SYSCON_CLK40X_BB_OEN_M (BIT(9))
#define SYSCON_CLK40X_BB_OEN_V 0x1
#define SYSCON_CLK40X_BB_OEN_S 9
/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
#define SYSCON_CLK_DAC_CPU_OEN (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_V 0x1
#define SYSCON_CLK_DAC_CPU_OEN_S 8
/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
#define SYSCON_CLK_ADC_INF_OEN (BIT(7))
#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7))
#define SYSCON_CLK_ADC_INF_OEN_V 0x1
#define SYSCON_CLK_ADC_INF_OEN_S 7
/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
#define SYSCON_CLK_320M_OEN (BIT(6))
#define SYSCON_CLK_320M_OEN_M (BIT(6))
#define SYSCON_CLK_320M_OEN_V 0x1
#define SYSCON_CLK_320M_OEN_S 6
/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
#define SYSCON_CLK160_OEN (BIT(5))
#define SYSCON_CLK160_OEN_M (BIT(5))
#define SYSCON_CLK160_OEN_V 0x1
#define SYSCON_CLK160_OEN_S 5
/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
#define SYSCON_CLK80_OEN (BIT(4))
#define SYSCON_CLK80_OEN_M (BIT(4))
#define SYSCON_CLK80_OEN_V 0x1
#define SYSCON_CLK80_OEN_S 4
/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
#define SYSCON_CLK_BB_OEN (BIT(3))
#define SYSCON_CLK_BB_OEN_M (BIT(3))
#define SYSCON_CLK_BB_OEN_V 0x1
#define SYSCON_CLK_BB_OEN_S 3
/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
#define SYSCON_CLK44_OEN (BIT(2))
#define SYSCON_CLK44_OEN_M (BIT(2))
#define SYSCON_CLK44_OEN_V 0x1
#define SYSCON_CLK44_OEN_S 2
/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
#define SYSCON_CLK22_OEN (BIT(1))
#define SYSCON_CLK22_OEN_M (BIT(1))
#define SYSCON_CLK22_OEN_V 0x1
#define SYSCON_CLK22_OEN_S 1
/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
#define SYSCON_CLK20_OEN (BIT(0))
#define SYSCON_CLK20_OEN_M (BIT(0))
#define SYSCON_CLK20_OEN_V 0x1
#define SYSCON_CLK20_OEN_S 0
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C)
/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V) << (SYSCON_WIFI_BB_CFG_S))
#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_S 0
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010)
/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V) << (SYSCON_WIFI_BB_CFG_2_S))
#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_2_S 0
#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014)
/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V) << (SYSCON_WIFI_CLK_EN_S))
#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_S 0
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018)
/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
#define SYSCON_WIFI_RST 0xFFFFFFFF
#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V) << (SYSCON_WIFI_RST_S))
#define SYSCON_WIFI_RST_V 0xFFFFFFFF
#define SYSCON_WIFI_RST_S 0
#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V) << (SYSTEM_WIFI_CLK_EN_S))
#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN_S 0
/**
* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21
* Bit15 not included here because of the bit now can't be cleared
*/
#define SYSTEM_WIFI_CLK_WIFI_EN 0x0
#define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V) << (SYSTEM_WIFI_CLK_WIFI_EN_S))
#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0
#define SYSTEM_WIFI_CLK_WIFI_EN_S 0
/* Mask for all Bluetooth clock bits - 11, 16, 17 */
#define SYSTEM_WIFI_CLK_BT_EN 0x0
#define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V) << (SYSTEM_WIFI_CLK_BT_EN_S))
#define SYSTEM_WIFI_CLK_BT_EN_V 0x0
#define SYSTEM_WIFI_CLK_BT_EN_S 0
/**
* Mask for clock bits used by both WIFI and Bluetooth,
* bit 0, 3, 6, 7, 8, 9
*/
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
/* Digital team to check */
/* bluetooth baseband bit11 */
#define SYSTEM_BT_BASEBAND_EN BIT(11)
/* bluetooth LC bit16 and bit17 */
#define SYSTEM_BT_LC_EN (BIT(16) | BIT(17))
/* Remaining single bit clock masks */
#define SYSTEM_WIFI_CLK_UNUSED_BIT5 BIT(5)
#define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12)
#define SYSTEM_WIFI_CLK_SDIO_HOST_EN BIT(13)
#define SYSTEM_WIFI_CLK_EMAC_EN BIT(14)
#define SYSTEM_WIFI_CLK_RNG_EN BIT(15)
#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG
#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
/* SYSTEM_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
#define SYSTEM_WIFI_RST 0xFFFFFFFF
#define SYSTEM_WIFI_RST_M ((SYSTEM_WIFI_RST_V) << (SYSTEM_WIFI_RST_S))
#define SYSTEM_WIFI_RST_V 0xFFFFFFFF
#define SYSTEM_WIFI_RST_S 0
#define SYSTEM_BB_REG_RST (BIT(13))
#define SYSTEM_PWR_REG_RST (BIT(12))
#define SYSTEM_BLE_REG_RST (BIT(11))
#define SYSTEM_RW_BTLP_RST (BIT(10))
#define SYSTEM_RW_BTMAC_RST (BIT(9))
#define SYSTEM_MACPWR_RST (BIT(8))
#define SYSTEM_EMAC_RST (BIT(7))
#define SYSTEM_SDIO_RST (BIT(5))
#define SYSTEM_BTMAC_RST (BIT(4))
#define SYSTEM_BT_RST (BIT(3))
#define SYSTEM_MAC_RST (BIT(2))
#define SYSTEM_FE_RST (BIT(1))
#define SYSTEM_BB_RST (BIT(0))
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C)
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
#define SYSCON_PERI_IO_SWAP 0x000000FF
#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V) << (SYSCON_PERI_IO_SWAP_S))
#define SYSCON_PERI_IO_SWAP_V 0xFF
#define SYSCON_PERI_IO_SWAP_S 0
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020)
/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0))
#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0))
#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1
#define SYSCON_EXT_MEM_PMS_LOCK_S 0
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x024)
/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_FLASH_ACE0_ATTR 0x000000FF
#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V) << (SYSCON_FLASH_ACE0_ATTR_S))
#define SYSCON_FLASH_ACE0_ATTR_V 0xFF
#define SYSCON_FLASH_ACE0_ATTR_S 0
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x028)
/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_FLASH_ACE1_ATTR 0x000000FF
#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V) << (SYSCON_FLASH_ACE1_ATTR_S))
#define SYSCON_FLASH_ACE1_ATTR_V 0xFF
#define SYSCON_FLASH_ACE1_ATTR_S 0
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C)
/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_FLASH_ACE2_ATTR 0x000000FF
#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V) << (SYSCON_FLASH_ACE2_ATTR_S))
#define SYSCON_FLASH_ACE2_ATTR_V 0xFF
#define SYSCON_FLASH_ACE2_ATTR_S 0
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x030)
/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_FLASH_ACE3_ATTR 0x000000FF
#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V) << (SYSCON_FLASH_ACE3_ATTR_S))
#define SYSCON_FLASH_ACE3_ATTR_V 0xFF
#define SYSCON_FLASH_ACE3_ATTR_S 0
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x034)
/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V) << (SYSCON_FLASH_ACE0_ADDR_S_S))
#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_S 0
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x038)
/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V) << (SYSCON_FLASH_ACE1_ADDR_S_S))
#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE1_ADDR_S_S 0
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C)
/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V) << (SYSCON_FLASH_ACE2_ADDR_S_S))
#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_S 0
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x040)
/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V) << (SYSCON_FLASH_ACE3_ADDR_S_S))
#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_S 0
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x044)
/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V) << (SYSCON_FLASH_ACE0_SIZE_S))
#define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE0_SIZE_S 0
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x048)
/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V) << (SYSCON_FLASH_ACE1_SIZE_S))
#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE1_SIZE_S 0
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C)
/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V) << (SYSCON_FLASH_ACE2_SIZE_S))
#define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE2_SIZE_S 0
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x050)
/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V) << (SYSCON_FLASH_ACE3_SIZE_S))
#define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE3_SIZE_S 0
#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x054)
/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_SRAM_ACE0_ATTR 0x000000FF
#define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V) << (SYSCON_SRAM_ACE0_ATTR_S))
#define SYSCON_SRAM_ACE0_ATTR_V 0xFF
#define SYSCON_SRAM_ACE0_ATTR_S 0
#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x058)
/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_SRAM_ACE1_ATTR 0x000000FF
#define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V) << (SYSCON_SRAM_ACE1_ATTR_S))
#define SYSCON_SRAM_ACE1_ATTR_V 0xFF
#define SYSCON_SRAM_ACE1_ATTR_S 0
#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x05C)
/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_SRAM_ACE2_ATTR 0x000000FF
#define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V) << (SYSCON_SRAM_ACE2_ATTR_S))
#define SYSCON_SRAM_ACE2_ATTR_V 0xFF
#define SYSCON_SRAM_ACE2_ATTR_S 0
#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x060)
/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_SRAM_ACE3_ATTR 0x000000FF
#define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V) << (SYSCON_SRAM_ACE3_ATTR_S))
#define SYSCON_SRAM_ACE3_ATTR_V 0xFF
#define SYSCON_SRAM_ACE3_ATTR_S 0
#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x064)
/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE0_ADDR_S_M ((SYSCON_SRAM_ACE0_ADDR_S_V) << (SYSCON_SRAM_ACE0_ADDR_S_S))
#define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE0_ADDR_S_S 0
#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x068)
/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE1_ADDR_S_M ((SYSCON_SRAM_ACE1_ADDR_S_V) << (SYSCON_SRAM_ACE1_ADDR_S_S))
#define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE1_ADDR_S_S 0
#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x06C)
/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V) << (SYSCON_SRAM_ACE2_ADDR_S_S))
#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE2_ADDR_S_S 0
#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x070)
/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE3_ADDR_S_M ((SYSCON_SRAM_ACE3_ADDR_S_V) << (SYSCON_SRAM_ACE3_ADDR_S_S))
#define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE3_ADDR_S_S 0
#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x074)
/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE0_SIZE_M ((SYSCON_SRAM_ACE0_SIZE_V) << (SYSCON_SRAM_ACE0_SIZE_S))
#define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE0_SIZE_S 0
#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x078)
/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V) << (SYSCON_SRAM_ACE1_SIZE_S))
#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE1_SIZE_S 0
#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x07C)
/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE2_SIZE_M ((SYSCON_SRAM_ACE2_SIZE_V) << (SYSCON_SRAM_ACE2_SIZE_S))
#define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE2_SIZE_S 0
#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x080)
/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE3_SIZE_M ((SYSCON_SRAM_ACE3_SIZE_V) << (SYSCON_SRAM_ACE3_SIZE_S))
#define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE3_SIZE_S 0
#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x084)
/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F
#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V) << (SYSCON_SPI_MEM_REJECT_CDE_S))
#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F
#define SYSCON_SPI_MEM_REJECT_CDE_S 2
/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1
#define SYSCON_SPI_MEM_REJECT_CLR_S 1
/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
#define SYSCON_SPI_MEM_REJECT_INT (BIT(0))
#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0))
#define SYSCON_SPI_MEM_REJECT_INT_V 0x1
#define SYSCON_SPI_MEM_REJECT_INT_S 0
#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x088)
/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V) << (SYSCON_SPI_MEM_REJECT_ADDR_S))
#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
#define SYSCON_SPI_MEM_REJECT_ADDR_S 0
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x08C)
/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x090)
/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
#define SYSCON_REDCY_ANDOR (BIT(31))
#define SYSCON_REDCY_ANDOR_M (BIT(31))
#define SYSCON_REDCY_ANDOR_V 0x1
#define SYSCON_REDCY_ANDOR_S 31
/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
#define SYSCON_REDCY_SIG0 0x7FFFFFFF
#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V) << (SYSCON_REDCY_SIG0_S))
#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG0_S 0
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x094)
/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
#define SYSCON_REDCY_NANDOR (BIT(31))
#define SYSCON_REDCY_NANDOR_M (BIT(31))
#define SYSCON_REDCY_NANDOR_V 0x1
#define SYSCON_REDCY_NANDOR_S 31
/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
#define SYSCON_REDCY_SIG1 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V) << (SYSCON_REDCY_SIG1_S))
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_S 0
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098)
/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
#define SYSCON_DC_MEM_FORCE_PD (BIT(5))
#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5))
#define SYSCON_DC_MEM_FORCE_PD_V 0x1
#define SYSCON_DC_MEM_FORCE_PD_S 5
/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
#define SYSCON_DC_MEM_FORCE_PU (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_V 0x1
#define SYSCON_DC_MEM_FORCE_PU_S 4
/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3))
#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3))
#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1
#define SYSCON_PBUS_MEM_FORCE_PD_S 3
/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2))
#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2))
#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1
#define SYSCON_PBUS_MEM_FORCE_PU_S 2
/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
#define SYSCON_AGC_MEM_FORCE_PD (BIT(1))
#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1))
#define SYSCON_AGC_MEM_FORCE_PD_V 0x1
#define SYSCON_AGC_MEM_FORCE_PD_S 1
/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
#define SYSCON_AGC_MEM_FORCE_PU (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_V 0x1
#define SYSCON_AGC_MEM_FORCE_PU_S 0
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h1907100 ; */
#define SYSCON_DATE 0xFFFFFFFF
#define SYSCON_DATE_M ((SYSCON_DATE_V) << (SYSCON_DATE_S))
#define SYSCON_DATE_V 0xFFFFFFFF
#define SYSCON_DATE_S 0
#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSCON_H */

66
boards/risc-v/esp32c3/esp32c3-devkit/configs/wapi/defconfig Normal file
View File

@ -0,0 +1,66 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_ARGCAT is not set
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="esp32c3-devkit"
CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y
CONFIG_ARCH_CHIP="esp32c3"
CONFIG_ARCH_CHIP_ESP32C3=y
CONFIG_ARCH_CHIP_ESP32C3WROOM02=y
CONFIG_ARCH_INTERRUPTSTACK=1536
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y
CONFIG_DRIVERS_IEEE80211=y
CONFIG_DRIVERS_WIRELESS=y
CONFIG_ESP32C3_WIRELESS=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=3072
CONFIG_INTELHEX_BINARY=y
CONFIG_NAME_MAX=48
CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDEV_LATEINIT=y
CONFIG_NETDEV_PHY_IOCTL=y
CONFIG_NETDEV_WIRELESS_IOCTL=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ETH_PKTSIZE=1514
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_TCP=y
CONFIG_NET_UDP=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_SIG_DEFAULT=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_SYSTEM_DHCPC_RENEW=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_PING=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WIRELESS=y
CONFIG_WIRELESS_WAPI=y
CONFIG_WIRELESS_WAPI_CMDTOOL=y
CONFIG_WIRELESS_WAPI_STACKSIZE=4096

8
boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.ld
View File

@ -36,6 +36,11 @@ SECTIONS
*(.iram1)
*(.iram1.*)
*(.wifi0iram .wifi0iram.*)
*(.wifirxiram .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
} >iram0_0_seg
/* This section is required to skip .iram0.text area because iram0_0_seg
@ -134,6 +139,9 @@ SECTIONS
*(.rodata)
*(.rodata.*)
*(.srodata.*)
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)

26
boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_rom.ld
View File

@ -1527,7 +1527,6 @@ lmacReachShortLimit = 0x4000161c;
lmacRecycleMPDU = 0x40001620;
lmacRxDone = 0x40001624;
lmacSetTxFrame = 0x40001628;
lmacTxDone = 0x4000162c;
lmacTxFrame = 0x40001630;
mac_tx_set_duration = 0x40001634;
mac_tx_set_htsig = 0x40001638;
@ -1933,3 +1932,28 @@ rom_pll_correct_dcap = 0x40001b1c;
rom_phy_en_hw_set_freq = 0x40001b20;
rom_phy_dis_hw_set_freq = 0x40001b24;
rom_pll_vol_cal = 0x40001b28;
/***************************************
Group memory and string
***************************************/
memset = 0x40000354;
memcpy = 0x40000358;
memmove = 0x4000035c;
memcmp = 0x40000360;
memccpy = 0x400003c4;
memchr = 0x400003c8;
memrchr = 0x400003cc;
strcpy = 0x40000364;
strncpy = 0x40000368;
strcmp = 0x4000036c;
strncmp = 0x40000370;
strlen = 0x40000374;
strstr = 0x40000378;
bzero = 0x4000037c;
/***************************************
Redefine functions
***************************************/
PROVIDE ( esp_rom_delay_us = ets_delay_us );

11
boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c
View File

@ -37,6 +37,8 @@
#include <nuttx/fs/fs.h>
#include "esp32c3_wlan.h"
#include "esp32c3-devkit.h"
/****************************************************************************
@ -143,6 +145,15 @@ int esp32c3_bringup(void)
}
#endif
#ifdef CONFIG_ESP32C3_WIRELESS
ret = esp32c3_wlan_sta_initialize();
if (ret)
{
syslog(LOG_ERR, "ERROR: Failed to initialize Wi-Fi\n");
return ret;
}
#endif
/* If we got here then perhaps not all initialization was successful, but
* at least enough succeeded to bring-up NSH with perhaps reduced
* capabilities.

2
boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_timer.c
View File

@ -56,7 +56,7 @@ int board_tim_init(void)
{
int ret = OK;
#ifdef CONFIG_ESP32C3_TIMER0
#if defined(CONFIG_ESP32C3_TIMER0) && !defined(CONFIG_ESP32C3_RT_TIMER)
ret = esp32c3_timer_initialize("/dev/timer0", ESP32C3_TIMER0);
if (ret < 0)
{