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arch/nrf52: replace all chip-specific conditions with chip-features conditions in all hardware definitions. This gives us a more modular code.

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This commit is contained in:
raiden00pl 2020-08-30 12:23:50 +02:00 committed by Matias N
parent c10a6789c4
commit 45f3aa4ca9
8 changed files with 241 additions and 135 deletions
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18
arch/arm/include/nrf52/nrf52_irq.h
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@ -86,18 +86,30 @@
#define NRF52_IRQ_I2S (NRF52_IRQ_EXTINT+37) /* Inter-IC Sound interface */
#define NRF52_IRQ_FPU (NRF52_IRQ_EXTINT+38) /* FPU interrupt */
#if defined(CONFIG_ARCH_FAMILY_NRF52840)
#ifdef CONFIG_NRF52_HAVE_USBDEV
# define NRF52_IRQ_USBD (NRF52_IRQ_EXTINT+39) /* USB device */
#endif
#ifdef CONFIG_NRF52_HAVE_UART1
# define NRF52_IRQ_UART1 (NRF52_IRQ_EXTINT+40) /* UART/UARTE 1 */
#endif
#ifdef CONFIG_NRF52_HAVE_QSPI
# define NRF52_IRQ_QSPI (NRF52_IRQ_EXTINT+41) /* Quad SPI */
#endif
#ifdef CONFIG_NRF52_HAVE_PWM3
# define NRF52_IRQ_PWM3 (NRF52_IRQ_EXTINT+45) /* Pulse Width Modulation Unit 3 */
#endif
#ifdef CONFIG_NRF52_HAVE_SPI3_MASTER
# define NRF52_IRQ_SPIM3 (NRF52_IRQ_EXTINT+47) /* SPI Master 3 */
#endif
#if defined(CONFIG_ARCH_FAMILY_NRF52840)
#if defined(CONFIG_ARCH_CHIP_NRF52832)
# define NRF52_IRQ_NEXTINT (39)
#elif defined(CONFIG_ARCH_CHIP_NRF52833)
# define NRF52_IRQ_NEXTINT (48)
#elif defined(CONFIG_ARCH_CHIP_NRF52840)
# define NRF52_IRQ_NEXTINT (48)
#else
# define NRF52_IRQ_NEXTINT (39)
# error Unknown NRF52 chip !
#endif
#define NRF52_IRQ_NIRQS (NRF52_IRQ_EXTINT+NRF52_IRQ_NEXTINT)

22
arch/arm/src/nrf52/Kconfig
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@ -14,25 +14,31 @@ config ARCH_CHIP_NRF52832
bool "NRF52832"
select ARCH_FAMILY_NRF52
select ARCH_FAMILY_NRF52832
select NRF52_HAVE_BPROT
config ARCH_CHIP_NRF52833
bool "NRF52832"
select ARCH_FAMILY_NRF52
select ARCH_FAMILY_NRF52833
select NRF52_HAVE_ACL
select NRF52_HAVE_UART1
select NRF52_HAVE_PORT1
select NRF52_HAVE_SPI3_MASTER
select NRF52_HAVE_USBDEV
select NRF52_HAVE_PWM3
config ARCH_CHIP_NRF52840
bool "NRF52840"
select ARCH_FAMILY_NRF52
select ARCH_FAMILY_NRF52840
select NRF52_HAVE_ACL
select NRF52_HAVE_UART1
select NRF52_HAVE_PORT1
select NRF52_HAVE_SPI3_MASTER
select NRF52_HAVE_QSPI
select NRF52_HAVE_USBDEV
select NRF52_HAVE_PWM3
select NRF52_HAVE_CRYPTOCELL
endchoice # NRF52 Chip Selection
@ -56,6 +62,14 @@ config ARCH_FAMILY_NRF52840
# Peripheral support
config NRF52_HAVE_BPROT
bool
default n
config NRF52_HAVE_ACL
bool
default n
config NRF52_HAVE_UART1
bool
default n
@ -76,6 +90,14 @@ config NRF52_HAVE_USBDEV
bool
default n
config NRF52_HAVE_PWM3
bool
default n
config NRF52_HAVE_CRYPTOCELL
bool
default n
# Peripheral Selection
config NRF52_I2C_MASTER

23
arch/arm/src/nrf52/hardware/nrf52_clock.h
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@ -47,6 +47,21 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if defined(CONFIG_ARCH_CHIP_NRF52832)
# undef HAVE_CLOCK_CALTIMER_EVENTS
# undef HAVE_CLOCK_HFXODEBOUNCE
#elif defined(CONFIG_ARCH_CHIP_NRF52833)
# define HAVE_CLOCK_CALTIMER_EVENTS
# define HAVE_CLOCK_HFXODEBOUNCE
#elif defined(CONFIG_ARCH_CHIP_NRF52840)
# define HAVE_CLOCK_CALTIMER_EVENTS
# define HAVE_CLOCK_HFXODEBOUNCE
#else
# error Unknown NRF52 chip !
#endif
/* Register offsets *********************************************************/
#define NRF52_CLOCK_TASKS_HFCLKSTART_OFFSET 0x0000 /* Start HFCLK crystal oscillator */
@ -60,7 +75,7 @@
#define NRF52_CLOCK_EVENTS_LFCLKSTARTED_OFFSET 0x0104 /* LFCLK started */
#define NRF52_CLOCK_EVENTS_DONE_OFFSET 0x010c /* Calibration of LFCLK RC oscillator complete event */
#define NRF52_CLOCK_EVENTS_CTTO_OFFSET 0x0110 /* Calibration timer timeout */
#ifdef CONFIG_ARCH_CHIP_NRF52840
#ifdef HAVE_CLOCK_CALTIMER_EVENTS
# define NRF52_CLOCK_EVENTS_CSTARTED_OFFSET 0x0128 /* Calibration timer has been started */
# define NRF52_CLOCK_EVENTS_CTSTOPPED_OFFSET 0x012c /* Calibration timer has been stopped */
#endif
@ -72,7 +87,7 @@
#define NRF52_CLOCK_LFCLKSTAT_OFFSET 0x0418 /* LFCLK status */
#define NRF52_CLOCK_LFCLKSRCCOPY_OFFSET 0x041c /* Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
#define NRF52_CLOCK_LFCLKSRC_OFFSET 0x0518 /* Clock source for the LFCLK */
#ifdef CONFIG_ARCH_CHIP_NRF52840
#ifdef HAVE_CLOCK_HFXODEBOUNCE
# define NRF52_CLOCK_HFXODEBOUNCE_OFFSET 0x0528 /* HFXO debounce time */
#endif
#define NRF52_CLOCK_CTIV_OFFSET 0x0538 /* Calibration timer interval */
@ -91,7 +106,7 @@
#define NRF52_CLOCK_EVENTS_LFCLKSTARTED (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_LFCLKSTARTED_OFFSET)
#define NRF52_CLOCK_EVENTS_DONE (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_DONE_OFFSET)
#define NRF52_CLOCK_EVENTS_CTTO (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_CTTO_OFFSET)
#ifdef CONFIG_ARCH_CHIP_NRF52840
#ifdef HAVE_CLOCK_CALTIMER_EVENTS
# define NRF52_CLOCK_EVENTS_CSTARTED (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_CSTARTED_OFFSET)
# define NRF52_CLOCK_EVENTS_CSTOPPED (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_CSTOPPED_OFFSET)
#endif
@ -103,7 +118,7 @@
#define NRF52_CLOCK_LFCLKSTAT (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKSTAT_OFFSET)
#define NRF52_CLOCK_LFCLKSRCCOPY (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKSRCCOPY_OFFSET)
#define NRF52_CLOCK_LFCLKSRC (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKSRC_OFFSET)
#ifdef CONFIG_ARCH_CHIP_NRF52840
#ifdef HAVE_CLOCK_HFXODEBOUNCE
# define NRF52_CLOCK_HFXODEBOUNCE (NRF52_CLOCK_BASE + NRF52_CLOCK_HFXODEBOUNCE_OFFSET)
#endif
#define NRF52_CLOCK_CTIV (NRF52_CLOCK_BASE + NRF52_CLOCK_CTIV_OFFSET)

2
arch/arm/src/nrf52/hardware/nrf52_gpio.h
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@ -48,7 +48,7 @@
* Pre-processor Definitions
************************************************************************************/
#ifdef CONFIG_ARCH_CHIP_NRF52840
#ifdef CONFIG_NRF52_HAVE_PORT1
# define NRF52_GPIO_NPORTS 2
# define NRF52_GPIO_PORT0 0
# define NRF52_GPIO_PORT1 1

19
arch/arm/src/nrf52/hardware/nrf52_memorymap.h
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@ -61,7 +61,7 @@
#define NRF52_CLOCK_BASE 0x40000000
#define NRF52_POWER_BASE 0x40000000
#ifdef CONFIG_ARCH_CHIP_NRF52832
#ifdef CONFIG_NRF52_HAVE_BPROT
# define NRF52_BPROT_BASE 0x40000000
#endif
#define NRF52_RADIO_BASE 0x40001000
@ -112,7 +112,7 @@
#define NRF52_TIMER4_BASE 0x4001b000
#define NRF52_PWM0_BASE 0x4001c000
#define NRF52_PDM_BASE 0x4001d000
#ifdef CONFIG_ARCH_CHIP_NRF52840
#ifdef CONFIG_NRF52_HAVE_ACL
# define NRF52_ACL_BASE 0x4001e000
#endif
#define NRF52_NVMC_BASE 0x4001e000
@ -126,23 +126,30 @@
#define NRF52_RTC2_BASE 0x40024000
#define NRF52_I2S_BASE 0x40025000
#define NRF52_FPU_BASE 0x40026000
#ifdef CONFIG_ARCH_CHIP_NRF52840
#ifdef CONFIG_NRF52_HAVE_USBDEV
# define NRF52_USBD_BASE 0x40027000
#endif
#ifdef CONFIG_NRF52_HAVE_UART1
# define NRF52_UART1_BASE 0x40028000
# define NRF52_UARTE1_BASE 0x40028000
#endif
#ifdef CONFIG_NRF52_HAVE_QSPI
# define NRF52_QSPI_BASE 0x40029000
#endif
#ifdef CONFIG_NRF52_HAVE_PWM3
# define NRF52_PWM3_BASE 0x4002d000
#endif
#ifdef CONFIG_NRF52_HAVE_SPI3_MASTER
# define NRF52_SPIM3_BASE 0x4002f000
#endif
/* AHB Peripherals */
#define NRF52_GPIO_P0_BASE 0x50000000
#ifdef CONFIG_ARCH_CHIP_NRF52840
#ifdef CONFIG_NRF52_HAVE_PORT1
# define NRF52_GPIO_P1_BASE 0x50000300
#endif
#ifdef CONFIG_ARCH_CHIP_NRF52840
#ifdef CONFIG_NRF52_HAVE_CRYPTOCELL
# define NRF52_CCHOSTRGF_BASE 0x5002a000
# define NRF52_CRYPTOCELL_BASE 0x5002a000
#endif

215
arch/arm/src/nrf52/hardware/nrf52_radio.h
View File

@ -32,84 +32,100 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if defined(CONFIG_ARCH_CHIP_NRF52832)
# define HAVE_RADIO_NRF250KBIT
# undef HAVE_RADIO_BLELR
# undef HAVE_RADIO_IEEE802154
#elif defined(CONFIG_ARCH_CHIP_NRF52833)
# undef HAVE_RADIO_NRF250KBIT
# define HAVE_RADIO_BLELR
# define HAVE_RADIO_IEEE802154
#elif defined(CONFIG_ARCH_CHIP_NRF52840)
# undef HAVE_RADIO_NRF250KBIT
# define HAVE_RADIO_BLELR
# define HAVE_RADIO_IEEE802154
#else
# error Unknown NRF52 chip !
#endif
/* Register offsets *********************************************************/
#define NRF52_RADIO_TASKS_TXEN_OFFSET 0x0000 /* Enable RADIO in TX mode */
#define NRF52_RADIO_TASKS_RXEN_OFFSET 0x0004 /* Enable RADIO in RX mode */
#define NRF52_RADIO_TASKS_START_OFFSET 0x0008 /* Start RADIO */
#define NRF52_RADIO_TASKS_STOP_OFFSET 0x000C /* Stop RADIO */
#define NRF52_RADIO_TASKS_DISABLE_OFFSET 0x0010 /* Disable RADIO */
#define NRF52_RADIO_TASKS_RSSISTART_OFFSET 0x0014 /* Start the RSSI and take one single sample of the receive signal strength */
#define NRF52_RADIO_TASKS_RSSISTOP_OFFSET 0x0018 /* Stop the RSSI measurement */
#define NRF52_RADIO_TASKS_BCSTART_OFFSET 0x001c /* Start the bit counter */
#define NRF52_RADIO_TASKS_BCSTOP_OFFSET 0x0020 /* Stop the bit counter */
#define NRF52_RADIO_TASKS_EDSTART_OFFSET 0x0024 /* Start the energy detect measurement used in IEEE 802.15.4 mode */
#define NRF52_RADIO_TASKS_EDSTOP_OFFSET 0x0028 /* Stop the energy detect measurement */
#define NRF52_RADIO_TASKS_CCASTART_OFFSET 0x002c /* Start the clear channel assessment used in IEEE 802.15.4 mode */
#define NRF52_RADIO_TASKS_CCASTOP_OFFSET 0x0030 /* Stop the clear channel assessment */
#define NRF52_RADIO_EVENTS_READY_OFFSET 0x0100 /* RADIO has ramped up and is ready to be started */
#define NRF52_RADIO_EVENTS_ADDRESS_OFFSET 0x0104 /* Address sent or received */
#define NRF52_RADIO_EVENTS_PAYLOAD_OFFSET 0x0108 /* Packet payload sent or received */
#define NRF52_RADIO_EVENTS_END_OFFSET 0x010c /* Packet sent or received */
#define NRF52_RADIO_EVENTS_DISABLED_OFFSET 0x0110 /* RADIO has been disabled */
#define NRF52_RADIO_EVENTS_DEVMATCH_OFFSET 0x0114 /* A device address match occurred on the last received packet */
#define NRF52_RADIO_EVENTS_DEVMISS_OFFSET 0x0118 /* No device address match occurred on the last received packet */
#define NRF52_RADIO_EVENTS_RSSIEND_OFFSET 0x011c /* Sampling of receive signal strength complete */
#define NRF52_RADIO_EVENTS_BCMATCH_OFFSET 0x0128 /* Bit counter reached bit count value */
#define NRF52_RADIO_EVENTS_CRCOK_OFFSET 0x0130 /* Packet received with CRC ok */
#define NRF52_RADIO_EVENTS_CRCERROR_OFFSET 0x0134 /* Packet received with CRC error */
#define NRF52_RADIO_EVENTS_FRAMESTART_OFFSET 0x0138 /* IEEE 802.15.4 length field received */
#define NRF52_RADIO_EVENTS_EDEND_OFFSET 0x013c /* Sampling of energy detection complete */
#define NRF52_RADIO_EVENTS_EDSTOPPED_OFFSET 0x0140 /* The sampling of energy detection has stopped */
#define NRF52_RADIO_EVENTS_CCAIDLE_OFFSET 0x0144 /* Wireless medium in idle - clear to send */
#define NRF52_RADIO_EVENTS_CCABUSY_OFFSET 0x0148 /* Wireless medium busy - do not send */
#define NRF52_RADIO_EVENTS_CCASTOPPED_OFFSET 0x014c /* The CCA has stopped */
#define NRF52_RADIO_EVENTS_RATEBOOST_OFFSET 0x0150 /* Ble_LR CI field received */
#define NRF52_RADIO_EVENTS_TXREADY_OFFSET 0x0154 /* RADIO has ramped up and is ready to be started TX path */
#define NRF52_RADIO_EVENTS_RXREADY_OFFSET 0x0158 /* RADIO has ramped up and is ready to be started RX path */
#define NRF52_RADIO_EVENTS_MHRMATCH_OFFSET 0x015c /* MAC header match found */
#define NRF52_RADIO_EVENTS_PHYEND_OFFSET 0x016c /* Last bit is sent on air */
#define NRF52_RADIO_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */
#define NRF52_RADIO_INTENSET_OFFSET 0x0304 /* Enable interrupt */
#define NRF52_RADIO_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
#define NRF52_RADIO_CRCSTATUS_OFFSET 0x0400 /* CRC status */
#define NRF52_RADIO_RXMATCH_OFFSET 0x0408 /* Received address */
#define NRF52_RADIO_RXCRC_OFFSET 0x040c /* CRC field of previously received packet */
#define NRF52_RADIO_DAI_OFFSET 0x0410 /* Device address match index */
#define NRF52_RADIO_PDUSTAT_OFFSET 0x0414 /* Payload status */
#define NRF52_RADIO_PACKETPTR_OFFSET 0x0504 /* Packet pointer */
#define NRF52_RADIO_FREQUENCY_OFFSET 0x0508 /* Frequency */
#define NRF52_RADIO_TXPOWER_OFFSET 0x050c /* Output power */
#define NRF52_RADIO_MODE_OFFSET 0x0510 /* Data rate and modulation */
#define NRF52_RADIO_PCNF0_OFFSET 0x0514 /* Packet configuration register 0 */
#define NRF52_RADIO_PCNF1_OFFSET 0x0518 /* Packet configuration register 1 */
#define NRF52_RADIO_BASE0_OFFSET 0x051c /* Base address 0 */
#define NRF52_RADIO_BASE1_OFFSET 0x0520 /* Base address 1 */
#define NRF52_RADIO_PREFIX0_OFFSET 0x0524 /* Prefixes bytes for logical addresses 0-3 */
#define NRF52_RADIO_PREFIX1_OFFSET 0x0528 /* Prefixes bytes for logical addresses 4-7 */
#define NRF52_RADIO_TXADDRESS_OFFSET 0x052c /* Transmit address select */
#define NRF52_RADIO_RXADDRESSES_OFFSET 0x0530 /* Receive address select */
#define NRF52_RADIO_CRCCNF_OFFSET 0x0534 /* CRC configuration */
#define NRF52_RADIO_CRCPOLY_OFFSET 0x0538 /* CRC polynomial */
#define NRF52_RADIO_CRCINIT_OFFSET 0x053c /* CRC initial value */
#define NRF52_RADIO_TIFS_OFFSET 0x0544 /* Interframe spacing in μs */
#define NRF52_RADIO_RSSISAMPLE_OFFSET 0x0548 /* RSSI sample */
#define NRF52_RADIO_STATE_OFFSET 0x0550 /* Current radio state */
#define NRF52_RADIO_DATAWHITEIV_OFFSET 0x0554 /* Data whitening initial value */
#define NRF52_RADIO_BCC_OFFSET 0x0560 /* Bit counter compare */
#define NRF52_RADIO_TASKS_TXEN_OFFSET 0x0000 /* Enable RADIO in TX mode */
#define NRF52_RADIO_TASKS_RXEN_OFFSET 0x0004 /* Enable RADIO in RX mode */
#define NRF52_RADIO_TASKS_START_OFFSET 0x0008 /* Start RADIO */
#define NRF52_RADIO_TASKS_STOP_OFFSET 0x000C /* Stop RADIO */
#define NRF52_RADIO_TASKS_DISABLE_OFFSET 0x0010 /* Disable RADIO */
#define NRF52_RADIO_TASKS_RSSISTART_OFFSET 0x0014 /* Start the RSSI and take one single sample of the receive signal strength */
#define NRF52_RADIO_TASKS_RSSISTOP_OFFSET 0x0018 /* Stop the RSSI measurement */
#define NRF52_RADIO_TASKS_BCSTART_OFFSET 0x001c /* Start the bit counter */
#define NRF52_RADIO_TASKS_BCSTOP_OFFSET 0x0020 /* Stop the bit counter */
#define NRF52_RADIO_TASKS_EDSTART_OFFSET 0x0024 /* Start the energy detect measurement used in IEEE 802.15.4 mode */
#define NRF52_RADIO_TASKS_EDSTOP_OFFSET 0x0028 /* Stop the energy detect measurement */
#define NRF52_RADIO_TASKS_CCASTART_OFFSET 0x002c /* Start the clear channel assessment used in IEEE 802.15.4 mode */
#define NRF52_RADIO_TASKS_CCASTOP_OFFSET 0x0030 /* Stop the clear channel assessment */
#define NRF52_RADIO_EVENTS_READY_OFFSET 0x0100 /* RADIO has ramped up and is ready to be started */
#define NRF52_RADIO_EVENTS_ADDRESS_OFFSET 0x0104 /* Address sent or received */
#define NRF52_RADIO_EVENTS_PAYLOAD_OFFSET 0x0108 /* Packet payload sent or received */
#define NRF52_RADIO_EVENTS_END_OFFSET 0x010c /* Packet sent or received */
#define NRF52_RADIO_EVENTS_DISABLED_OFFSET 0x0110 /* RADIO has been disabled */
#define NRF52_RADIO_EVENTS_DEVMATCH_OFFSET 0x0114 /* A device address match occurred on the last received packet */
#define NRF52_RADIO_EVENTS_DEVMISS_OFFSET 0x0118 /* No device address match occurred on the last received packet */
#define NRF52_RADIO_EVENTS_RSSIEND_OFFSET 0x011c /* Sampling of receive signal strength complete */
#define NRF52_RADIO_EVENTS_BCMATCH_OFFSET 0x0128 /* Bit counter reached bit count value */
#define NRF52_RADIO_EVENTS_CRCOK_OFFSET 0x0130 /* Packet received with CRC ok */
#define NRF52_RADIO_EVENTS_CRCERROR_OFFSET 0x0134 /* Packet received with CRC error */
#define NRF52_RADIO_EVENTS_FRAMESTART_OFFSET 0x0138 /* IEEE 802.15.4 length field received */
#define NRF52_RADIO_EVENTS_EDEND_OFFSET 0x013c /* Sampling of energy detection complete */
#define NRF52_RADIO_EVENTS_EDSTOPPED_OFFSET 0x0140 /* The sampling of energy detection has stopped */
#define NRF52_RADIO_EVENTS_CCAIDLE_OFFSET 0x0144 /* Wireless medium in idle - clear to send */
#define NRF52_RADIO_EVENTS_CCABUSY_OFFSET 0x0148 /* Wireless medium busy - do not send */
#define NRF52_RADIO_EVENTS_CCASTOPPED_OFFSET 0x014c /* The CCA has stopped */
#define NRF52_RADIO_EVENTS_RATEBOOST_OFFSET 0x0150 /* Ble_LR CI field received */
#define NRF52_RADIO_EVENTS_TXREADY_OFFSET 0x0154 /* RADIO has ramped up and is ready to be started TX path */
#define NRF52_RADIO_EVENTS_RXREADY_OFFSET 0x0158 /* RADIO has ramped up and is ready to be started RX path */
#define NRF52_RADIO_EVENTS_MHRMATCH_OFFSET 0x015c /* MAC header match found */
#define NRF52_RADIO_EVENTS_PHYEND_OFFSET 0x016c /* Last bit is sent on air */
#define NRF52_RADIO_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */
#define NRF52_RADIO_INTENSET_OFFSET 0x0304 /* Enable interrupt */
#define NRF52_RADIO_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
#define NRF52_RADIO_CRCSTATUS_OFFSET 0x0400 /* CRC status */
#define NRF52_RADIO_RXMATCH_OFFSET 0x0408 /* Received address */
#define NRF52_RADIO_RXCRC_OFFSET 0x040c /* CRC field of previously received packet */
#define NRF52_RADIO_DAI_OFFSET 0x0410 /* Device address match index */
#define NRF52_RADIO_PDUSTAT_OFFSET 0x0414 /* Payload status */
#define NRF52_RADIO_PACKETPTR_OFFSET 0x0504 /* Packet pointer */
#define NRF52_RADIO_FREQUENCY_OFFSET 0x0508 /* Frequency */
#define NRF52_RADIO_TXPOWER_OFFSET 0x050c /* Output power */
#define NRF52_RADIO_MODE_OFFSET 0x0510 /* Data rate and modulation */
#define NRF52_RADIO_PCNF0_OFFSET 0x0514 /* Packet configuration register 0 */
#define NRF52_RADIO_PCNF1_OFFSET 0x0518 /* Packet configuration register 1 */
#define NRF52_RADIO_BASE0_OFFSET 0x051c /* Base address 0 */
#define NRF52_RADIO_BASE1_OFFSET 0x0520 /* Base address 1 */
#define NRF52_RADIO_PREFIX0_OFFSET 0x0524 /* Prefixes bytes for logical addresses 0-3 */
#define NRF52_RADIO_PREFIX1_OFFSET 0x0528 /* Prefixes bytes for logical addresses 4-7 */
#define NRF52_RADIO_TXADDRESS_OFFSET 0x052c /* Transmit address select */
#define NRF52_RADIO_RXADDRESSES_OFFSET 0x0530 /* Receive address select */
#define NRF52_RADIO_CRCCNF_OFFSET 0x0534 /* CRC configuration */
#define NRF52_RADIO_CRCPOLY_OFFSET 0x0538 /* CRC polynomial */
#define NRF52_RADIO_CRCINIT_OFFSET 0x053c /* CRC initial value */
#define NRF52_RADIO_TIFS_OFFSET 0x0544 /* Interframe spacing in μs */
#define NRF52_RADIO_RSSISAMPLE_OFFSET 0x0548 /* RSSI sample */
#define NRF52_RADIO_STATE_OFFSET 0x0550 /* Current radio state */
#define NRF52_RADIO_DATAWHITEIV_OFFSET 0x0554 /* Data whitening initial value */
#define NRF52_RADIO_BCC_OFFSET 0x0560 /* Bit counter compare */
#define NRF52_RADIO_DAB_OFFSET(p) (0x0600 + ((p) * 0x4)) /* Device address base segment */
#define NRF52_RADIO_DAP_OFFSET(p) (0x0620 + ((p) * 0x4)) /* Device address prefix */
#define NRF52_RADIO_DACNF_OFFSET 0x0640 /* Device address match configuration */
#define NRF52_RADIO_MHRMATCHCONF_OFFSET 0x0644 /* Search pattern configuration */
#define NRF52_RADIO_MHRMATCHMAS_OFFSET 0x0648 /* Pattern mask */
#define NRF52_RADIO_MODECNF0_OFFSET 0x0650 /* Radio mode configuration register 0 */
#define NRF52_RADIO_SFD_OFFSET 0x0660 /* IEEE 802.15.4 start of frame delimiter */
#define NRF52_RADIO_EDCNT_OFFSET 0x0664 /* IEEE 802.15.4 energy detect loop count */
#define NRF52_RADIO_EDSAMPLE_OFFSET 0x0668 /* IEEE 802.15.4 energy detect level */
#define NRF52_RADIO_CCACTRL_OFFSET 0x066c /* IEEE 802.15.4 clear channel assessment control */
#define NRF52_RADIO_POWER_OFFSET 0x0ffc /* Peripheral power control */
#define NRF52_RADIO_DACNF_OFFSET 0x0640 /* Device address match configuration */
#define NRF52_RADIO_MHRMATCHCONF_OFFSET 0x0644 /* Search pattern configuration */
#define NRF52_RADIO_MHRMATCHMAS_OFFSET 0x0648 /* Pattern mask */
#define NRF52_RADIO_MODECNF0_OFFSET 0x0650 /* Radio mode configuration register 0 */
#define NRF52_RADIO_SFD_OFFSET 0x0660 /* IEEE 802.15.4 start of frame delimiter */
#define NRF52_RADIO_EDCNT_OFFSET 0x0664 /* IEEE 802.15.4 energy detect loop count */
#define NRF52_RADIO_EDSAMPLE_OFFSET 0x0668 /* IEEE 802.15.4 energy detect level */
#define NRF52_RADIO_CCACTRL_OFFSET 0x066c /* IEEE 802.15.4 clear channel assessment control */
#define NRF52_RADIO_POWER_OFFSET 0x0ffc /* Peripheral power control */
/* Register Addresses *******************************************************/
@ -419,20 +435,19 @@
/* MODE Register */
#define RADIO_MODE_SHIFT (0) /* Bits 0-3: Radio data rate and modulation setting (FSK) */
#define RADIO_MODE_SHIFT (0) /* Bits 0-3: Radio data rate and modulation setting (FSK) */
#define RADIO_MODE_MASK (0xf << RADIO_MODE_SHIFT)
#define RADIO_MODE_NRF1MBIT (0x00 << RADIO_MODE_SHIFT) /* 0: 1 Mbit/s Nordic proprietary radio mode */
#define RADIO_MODE_NRF2MBIT (0x01 << RADIO_MODE_SHIFT) /* 1: 2 Mbit/s Nordic proprietary radio mode */
#if defined(CONFIG_ARCH_CHIP_NRF52832)
#ifdef HAVE_RADIO_NRF250KBIT
# define RADIO_MODE_NRF250KBIT (0x02 << RADIO_MODE_SHIFT) /* 2: 250 kbit/s Nordic proprietary radio mode (deprecated) */
# define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */
# define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */
#elif defined(CONFIG_ARCH_CHIP_NRF52840)
# define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */
# define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */
#endif
#define RADIO_MODE_BLE1MBIT (0x03 << RADIO_MODE_SHIFT) /* 3: 1 Mbit/s BLE */
#define RADIO_MODE_BLE2MBIT (0x04 << RADIO_MODE_SHIFT) /* 4: 2 Mbit/s BLE */
#ifdef HAVE_RADIO_BLELR
# define RADIO_MODE_BLELR125KBIT (0x05 << RADIO_MODE_SHIFT) /* 5: Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
# define RADIO_MODE_BLELR500KBIT (0x06 << RADIO_MODE_SHIFT) /* 6: Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
#ifdef HAVE_RADIO_IEEE802154
# define RADIO_MODE_IEEE802154 (0x0f << RADIO_MODE_SHIFT) /* 15: IEEE 802.15.4-2006 250 kbit/s */
#endif
@ -448,8 +463,7 @@
#define RADIO_PCNF0_S1LEN_MASK (0xf << RADIO_PCNF0_S1LEN_SHIFT)
#define RADIO_PCNF0_S1LEN_MAX (0xf)
#define RADIO_PCNF0_S1INCL (1 << 20) /* Bit 20: Include or exclude S1 field in RAM */
#ifdef CONFIG_ARCH_CHIP_NRF52840
#ifdef HAVE_RADIO_BLELR
# define RADIO_PCNF0_CILEN_SHIFT (22) /* Bits 22-23: Length of code indicator - long range */
# define RADIO_PCNF0_CILEN_MASK (0x3 << RADIO_PCNF0_CILEN_SHIFT)
# define RADIO_PCNF0_CILEN_MAX (0x3)
@ -459,10 +473,13 @@
#define RADIO_PCNF0_PLEN_MASK (0x3 << RADIO_PCNF0_PLEN_SHIFT)
# define RADIO_PCNF0_PLEN_8BIT (0 << RADIO_PCNF0_PLEN_SHIFT)
# define RADIO_PCNF0_PLEN_16BIT (1 << RADIO_PCNF0_PLEN_SHIFT)
#ifdef HAVE_RADIO_IEEE802154
# define RADIO_PCNF0_PLEN_32BITZ (2 << RADIO_PCNF0_PLEN_SHIFT)
#endif
#ifdef HAVE_RADIO_BLELR
# define RADIO_PCNF0_PLEN_LONGRANGE (3 << RADIO_PCNF0_PLEN_SHIFT)
#ifdef CONFIG_ARCH_CHIP_NRF52840
#endif
#ifdef HAVE_RADIO_BLELR
# define RADIO_PCNF0_CRCINC_SHIFT (26) /* Bit 26: Indicates if LENGTH field contains CRC */
# define RADIO_PCNF0_CRCINC (1 << RADIO_PCNF0_CRCINC_SHIFT)
# define RADIO_PCNF0_TERMLEN_SHIFT (29) /* Bits 29-30: Length of TERM field in Long Range operation */
@ -507,15 +524,15 @@
# define RADIO_CRCCNF_LEN_2 (2 << RADIO_CRCCNF_LEN_SHIFT)
# define RADIO_CRCCNF_LEN_3 (3 << RADIO_CRCCNF_LEN_SHIFT)
#define RADIO_CRCCNF_SKIPADDR_SHIFT (8) /* Bit 8-9: Include or exclude packet address field out of CRC calculation */
#if defined(CONFIG_ARCH_CHIP_NRF52832)
#ifdef HAVE_RADIO_IEEE802154
# define RADIO_CRCCNF_SKIPADDR_MASK (0x3 << RADIO_CRCCNF_SKIPADDR_SHIFT)
# define RADIO_CRCCNF_SKIPADDR_INCL (0 << RADIO_CRCCNF_SKIPADDR_SHIFT)
# define RADIO_CRCCNF_SKIPADDR_SKIP (1 << RADIO_CRCCNF_SKIPADDR_SHIFT)
# define RADIO_CRCCNF_SKIPADDR_IEEE (3 << RADIO_CRCCNF_SKIPADDR_SHIFT)
#else
# define RADIO_CRCCNF_SKIPADDR_MASK (0x1 << RADIO_CRCCNF_SKIPADDR_SHIFT)
# define RADIO_CRCCNF_SKIPADDR_INCL (0 << RADIO_CRCCNF_SKIPADDR_SHIFT)
# define RADIO_CRCCNF_SKIPADDR_SKIP (1 << RADIO_CRCCNF_SKIPADDR_SHIFT)
#elif defined(CONFIG_ARCH_CHIP_NRF52840)
# define RADIO_CRCCNF_SKIPADDR_MASK (0x3 << RADIO_CRCCNF_SKIPADDR_SHIFT)
# define RADIO_CRCCNF_SKIPADDR_INCL (1 << RADIO_CRCCNF_SKIPADDR_SHIFT)
# define RADIO_CRCCNF_SKIPADDR_SKIP (2 << RADIO_CRCCNF_SKIPADDR_SHIFT)
# define RADIO_CRCCNF_SKIPADDR_IEEE (3 << RADIO_CRCCNF_SKIPADDR_SHIFT)
#endif
/* CRCPOLY Register */
@ -578,20 +595,22 @@
# define RADIO_MODECNF0_DTX_B0 (1 << RADIO_MODECNF0_DTX_SHIFT)
# define RADIO_MODECNF0_DTX_CENTER (2 << RADIO_MODECNF0_DTX_SHIFT)
#ifdef HAVE_RADIO_IEEE802154
/* SFD Register */
#define RADIO_SFD_SHIFT (0) /* Bits 0-7: IEEE 802.15.4 start of frame delimiter */
#define RADIO_SFD_MASK (0xff << RADIO_SFD_SHIFT)
# define RADIO_SFD_SHIFT (0) /* Bits 0-7: IEEE 802.15.4 start of frame delimiter */
# define RADIO_SFD_MASK (0xff << RADIO_SFD_SHIFT)
/* EDCNT Register */
#define RADIO_EDCNT_SHIFT (0) /* Bits 0-20: IEEE 802.15.4 energy detect loop count */
#define RADIO_EDCNT_MASK (0x1fffff << RADIO_EDCNT_SHIFT)
# define RADIO_EDCNT_SHIFT (0) /* Bits 0-20: IEEE 802.15.4 energy detect loop count */
# define RADIO_EDCNT_MASK (0x1fffff << RADIO_EDCNT_SHIFT)
/* EDSAMPLE Register */
#define RADIO_EDSAMPLE_SHIFT (0) /* Bits 0-7: IEEE 802.15.4 energy detect level */
#define RADIO_EDSAMPLE_MASK (0xff << RADIO_EDSAMPLE_SHIFT)
# define RADIO_EDSAMPLE_SHIFT (0) /* Bits 0-7: IEEE 802.15.4 energy detect level */
# define RADIO_EDSAMPLE_MASK (0xff << RADIO_EDSAMPLE_SHIFT)
#endif /* CONFIG_NRF52_HAVE_RADIO_IEEE802154 */
/* CCACTRL Register */

27
arch/arm/src/nrf52/hardware/nrf52_uarte.h
View File

@ -1,4 +1,4 @@
/****************************************************************************
/***************************************************************************
* arch/arm/src/nrf52/hardware/nrf52_uarte.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
@ -36,17 +36,32 @@
#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UARTE_H
#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UARTE_H
/****************************************************************************
/***************************************************************************
* Included Files
***************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf52_memorymap.h"
/****************************************************************************
/***************************************************************************
* Pre-processor Definitions
***************************************************************************/
/* Configuration ***********************************************************/
#if defined(CONFIG_ARCH_CHIP_NRF52832)
# undef HAVE_UART_PARITYTYPE
# undef HAVE_UART_STOPBITS
#elif defined(CONFIG_ARCH_CHIP_NRF52833)
# define HAVE_UART_PARITYTYPE
# define HAVE_UART_STOPBITS
#elif defined(CONFIG_ARCH_CHIP_NRF52840)
# undef HAVE_UART_PARITYTYPE
# define HAVE_UART_STOPBITS
#else
# error Unknown NRF52 chip !
#endif
/* UART/UARTE Register Offsets *********************************************/
#define NRF52_UARTE_TASKS_STARTRX_OFFSET 0x0000 /* Start UART receiver */
@ -347,6 +362,8 @@
# define UART_BAUDRATE_460800 (0x07400000)
# define UART_BAUDRATE_921600 (0x0f000000)
# define UART_BAUDRATE_1000000 (0x10000000)
#else
# error Unknown NRF52 chip !
#endif
/* CONFIG Register */
@ -355,11 +372,11 @@
#define UART_CONFIG_PARITY_SHIFT (1) /* Bits 1-3: Parity */
#define UART_CONFIG_PARITY (7 << UART_CONFIG_PARITY_SHIFT)
#if defined(CONFIG_ARCH_CHIP_NRF52833) || defined(CONFIG_ARCH_CHIP_NRF52840)
#ifdef HAVE_UART_STOPBITS
# define UART_CONFIG_STOP (1 << 4) /* Bit 4: Stop bits */
#endif
#ifdef CONFIG_ARCH_CHIP_NRF52833
#ifdef HAVE_UART_PARITYTYPE
# define UART_CONFIG_PARITYTYPE (1 << 8) /* Bit 8: Parity type */
#endif

50
arch/arm/src/nrf52/hardware/nrf52_uicr.h
View File

@ -1,4 +1,4 @@
/***************************************************************************************************
/***************************************************************************
* arch/arm/src/nrf52/hardware/nrf52_uicr.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
@ -31,40 +31,54 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************************************/
***************************************************************************/
#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UICR_H
#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UICR_H
/***************************************************************************************************
/***************************************************************************
* Included Files
***************************************************************************************************/
***************************************************************************/
#include <nuttx/config.h>
#include "hardware/nrf52_memorymap.h"
/***************************************************************************************************
/***************************************************************************
* Pre-processor Definitions
***************************************************************************************************/
***************************************************************************/
/* UICR Register Offsets ****************************************************************************/
/* Configuration ***********************************************************/
/* Registers for the UICR */
#if defined(CONFIG_ARCH_CHIP_NRF52832)
# undef HAVE_UICR_DEBUGCTRL
# undef HAVE_UICR_REGOUT0
#elif defined(CONFIG_ARCH_CHIP_NRF52833)
# define HAVE_UICR_DEBUGCTRL
# define HAVE_UICR_REGOUT0
#elif defined(CONFIG_ARCH_CHIP_NRF52840)
# define HAVE_UICR_DEBUGCTRL
# define HAVE_UICR_REGOUT0
#else
# error Unknown NRF52 chip !
#endif
/* UICR Register Offsets ***************************************************/
/* 0x000 - 0x010 : UNUSED */
#define NRF52_UICR_NRFFW_OFFSET(x) (0x014 + ((x) * 0x4)) /* Reserved for Nordic firmware design */
#define NRF52_UICR_NRFHW_OFFSET(x) (0x050 + ((x) * 0x4)) /* Reserved for Nordic hardware design */
#define NRF52_UICR_CUSTOMER_OFFSET(x) (0x080 + ((x) * 0x4)) /* Reserved for customer */
#define NRF52_UICR_PSELRESET0_OFFSET 0x200 /* Mapping of the nRESET function */
#define NRF52_UICR_PSELRESET1_OFFSET 0x204 /* Mapping of the nRESET function */
#define NRF52_UICR_APPROTECT_OFFSET 0x208 /* Access port protection */
#define NRF52_UICR_NFCPINS_OFFSET 0x20c /* Setting of pins dedicated to NFC */
#ifdef CONFIG_ARCH_CHIP_NRF52840
# define NRF52_UICR_DEBUGCTRL_OFFSET 0x210 /* Setting of pins dedicated to NFC */
# define NRF52_UICR_REGOUT0_OFFSET 0x304 /* GPIO reference voltage / external voltage */
#define NRF52_UICR_PSELRESET0_OFFSET 0x200 /* Mapping of the nRESET function */
#define NRF52_UICR_PSELRESET1_OFFSET 0x204 /* Mapping of the nRESET function */
#define NRF52_UICR_APPROTECT_OFFSET 0x208 /* Access port protection */
#define NRF52_UICR_NFCPINS_OFFSET 0x20c /* Setting of pins dedicated to NFC */
#ifdef HAVE_UICR_DEBUGCTRL
# define NRF52_UICR_DEBUGCTRL_OFFSET 0x210 /* Setting of pins dedicated to NFC */
#endif
#ifdef HAVE_UICR_REGOUT0
# define NRF52_UICR_REGOUT0_OFFSET 0x304 /* GPIO reference voltage / external voltage */
#endif
/* UICR Register Addresses **************************************************************************/
/* UICR Register Addresses *************************************************/
#define NRF52_UICR_PSELRESET0 (NRF52_UICR_BASE + NRF52_UICR_PSELRESET0_OFFSET)
#define NRF52_UICR_PSELRESET1 (NRF52_UICR_BASE + NRF52_UICR_PSELRESET1_OFFSET)
@ -73,7 +87,7 @@
#define NRF52_UICR_DEBUGCTRL (NRF52_UICR_BASE + NRF52_UICR_DEBUGCTRL_OFFSET)
#define NRF52_UICR_REGOUT0 (NRF52_UICR_BASE + NRF52_UICR_REGOUT0_OFFSET)
/* UICR Register Bitfield Definitions **************************************************************/
/* UICR Register Bitfield Definitions **************************************/
/* REGOUT0 Register */