SAMD20: The basic port is complete but still untested
This commit is contained in:
Gregory Nutt
parent
b219b3c7f6
commit
46348a29bb
@ -69,7 +69,7 @@ endif
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CHIP_ASRCS =
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CHIP_CSRCS = sam_clockconfig.c sam_idle.c sam_irq.c sam_lowputc.c
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CHIP_CSRCS += sam_port.c sam_start.c sam_timerisr.c sam_usart.c
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CHIP_CSRCS += sam_port.c sam_serial.c sam_start.c sam_timerisr.c sam_usart.c
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ifeq ($(CONFIG_NUTTX_KERNEL),y)
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CHIP_CSRCS += sam_userspace.c
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84
arch/arm/src/samd/chip/sam_sercom.h
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84
arch/arm/src/samd/chip/sam_sercom.h
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@ -0,0 +1,84 @@
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/********************************************************************************************
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* arch/arm/src/samd/chip/sam_sercom.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
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* Datasheet", 42129J–SAM–12/2013
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMD_CHIP_SAM_SERCOM_H
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#define __ARCH_ARM_SRC_SAMD_CHIP_SAM_SERCOM_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* Two generic clocks are used by the SERCOM: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The
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* core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while operating as a
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* master, while the slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions.
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* SERCOM modules must share the same slow GCLK channel ID.
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*
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* The baud-rate generator runs off the GCLK_SERCOMx_CORE clock (or, optionally, external
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* clock).
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*/
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#define SERCOM_GCLK_ID_SLOW 12
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#define SERCOM_GCLK_ID_CORE(n) (13+(n))
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# define SERCOM0_GCLK_ID_CORE 13
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# define SERCOM1_GCLK_ID_CORE 14
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# define SERCOM2_GCLK_ID_CORE 15
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# define SERCOM3_GCLK_ID_CORE 16
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# define SERCOM4_GCLK_ID_CORE 17
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# define SERCOM5_GCLK_ID_CORE 18
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMD_CHIP_SAM_SERCOM_H */
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@ -130,6 +130,7 @@
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/* Control A register */
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#define USART_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
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#define USART_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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#define USART_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
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#define USART_CTRLA_MODE_MASK (7 << USART_CTRLA_MODE_SHIFT)
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@ -61,6 +61,7 @@
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#include "chip/sam_usart.h"
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#include "sam_usart.h"
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#include "sam_lowputc.h"
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/****************************************************************************
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* Pre-processor Definitions
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@ -455,17 +456,51 @@ int sam_usart_initialize(const struct sam_usart_config_s * const config)
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irqstate_t flags;
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int ret;
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/* Reset the SERCOM so that we know that it is in its initial state */
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flags = irqsave();
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sam_usart_reset(config);
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/* Just invoke the internal implementation, but with interrupts disabled
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* so that the operation is atomic.
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*/
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flags = irqsave();
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ret = sam_usart_internal(config);
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irqrestore(flags);
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return ret;
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}
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#endif
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/****************************************************************************
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* Name: sam_usart_reset
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*
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* Description:
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* Reset the USART SERCOM. This restores all SERCOM register to the
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* initial state and disables the SERCOM.
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*
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*****************************************************************************/
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#ifdef HAVE_USART
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void sam_usart_reset(const struct sam_usart_config_s * const config)
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{
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uintptr_t regaddr = config->base + SAM_USART_CTRLA_OFFSET;
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uint32_t regval;
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/* Reset the SERCOM by setting the SWRST bit in the CTRLA register. When
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* the reset completes, the SERCOM will registers will be restored to there
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* initial state and the SERCOM will be disabled.
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*/
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regval = getreg32(regaddr);
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regval |= USART_CTRLA_SWRST;
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putreg32(regval, regaddr);
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/* Wait for the reset to complete */
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while ((getreg32(regaddr) & USART_CTRLA_SWRST) != 0);
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}
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#endif
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/****************************************************************************
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* Name: sam_lowputc
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*
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@ -95,6 +95,20 @@ struct sam_usart_config_s;
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int sam_usart_initialize(const struct sam_usart_config_s * const config);
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#endif
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/****************************************************************************
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* Name: sam_usart_reset
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*
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* Description:
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* Reset the USART SERCOM. This restores all SERCOM register to the
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* initial state and disables the SERCOM.
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*
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*****************************************************************************/
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#ifdef HAVE_USART
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struct sam_usart_config_s;
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void sam_usart_reset(const struct sam_usart_config_s * const config);
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#endif
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/****************************************************************************
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* Name: sam_lowputc
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*
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1067
arch/arm/src/samd/sam_serial.c
Normal file
1067
arch/arm/src/samd/sam_serial.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -43,7 +43,6 @@
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#include <nuttx/config.h>
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#include "sam_config.h"
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#include "chip/sam_sercom.h"
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/************************************************************************************
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* Pre-processor Definitions
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/samd/sam_start.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -83,7 +83,6 @@ struct sam_usart_config_s
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uint8_t bits; /* Number of bits (5-9) */
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uint8_t irq; /* SERCOM IRQ number */
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uint8_t gclkgen; /* Source GCLK generator */
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bool isconsole; /* True: The USART is the console device */
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bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
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uint32_t baud; /* Configured baud */
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port_pinset_t pad0; /* Pin configuration for PAD0 */
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