SAMD20: The basic port is complete but still untested

arch/arm/src/samd/Make.defs

@@ -69,7 +69,7 @@ endif
 
 CHIP_ASRCS  = 
 CHIP_CSRCS  = sam_clockconfig.c sam_idle.c sam_irq.c sam_lowputc.c
-CHIP_CSRCS += sam_port.c sam_start.c sam_timerisr.c sam_usart.c
+CHIP_CSRCS += sam_port.c sam_serial.c sam_start.c sam_timerisr.c sam_usart.c
 
 ifeq ($(CONFIG_NUTTX_KERNEL),y)
 CHIP_CSRCS += sam_userspace.c

arch/arm/src/samd/chip/sam_sercom.h

@@ -0,0 +1,84 @@
+/********************************************************************************************
+ * arch/arm/src/samd/chip/sam_sercom.h
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * References:
+ *   "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
+ *   Datasheet", 42129J–SAM–12/2013
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMD_CHIP_SAM_SERCOM_H
+#define __ARCH_ARM_SRC_SAMD_CHIP_SAM_SERCOM_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* Two generic clocks are used by the SERCOM: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW.  The
+ * core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while operating as a
+ * master, while the slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions.
+ * SERCOM modules must share the same slow GCLK channel ID.
+ *
+ * The baud-rate generator runs off the GCLK_SERCOMx_CORE clock (or, optionally, external
+ * clock).
+ */
+
+#define SERCOM_GCLK_ID_SLOW          12
+#define SERCOM_GCLK_ID_CORE(n)       (13+(n))
+#  define SERCOM0_GCLK_ID_CORE       13
+#  define SERCOM1_GCLK_ID_CORE       14
+#  define SERCOM2_GCLK_ID_CORE       15
+#  define SERCOM3_GCLK_ID_CORE       16
+#  define SERCOM4_GCLK_ID_CORE       17
+#  define SERCOM5_GCLK_ID_CORE       18
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAMD_CHIP_SAM_SERCOM_H */

arch/arm/src/samd/chip/sam_usart.h

@@ -130,6 +130,7 @@
 
 /* Control A register */
 
+#define USART_CTRLA_SWRST            (1 << 0)  /* Bit 0:  Software reset */
 #define USART_CTRLA_ENABLE           (1 << 1)  /* Bit 1:  Enable */
 #define USART_CTRLA_MODE_SHIFT       (2)       /* Bits 2-4: Operating Mode */
 #define USART_CTRLA_MODE_MASK        (7 << USART_CTRLA_MODE_SHIFT)

arch/arm/src/samd/sam_lowputc.c

@@ -61,6 +61,7 @@
 #include "chip/sam_usart.h"
 
 #include "sam_usart.h"
+#include "sam_lowputc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -455,17 +456,51 @@ int sam_usart_initialize(const struct sam_usart_config_s * const config)
   irqstate_t flags;
   int ret;
 
+  /* Reset the SERCOM so that we know that it is in its initial state */
+
+  flags = irqsave();
+  sam_usart_reset(config);
+
   /* Just invoke the internal implementation, but with interrupts disabled
    * so that the operation is atomic.
    */
 
-  flags = irqsave();
   ret = sam_usart_internal(config);
   irqrestore(flags);
   return ret;
 }
 #endif
 
+/****************************************************************************
+ * Name: sam_usart_reset
+ *
+ * Description:
+ *   Reset the USART SERCOM.  This restores all SERCOM register to the
+ *   initial state and disables the SERCOM.
+ *
+ *****************************************************************************/
+
+#ifdef HAVE_USART
+void sam_usart_reset(const struct sam_usart_config_s * const config)
+{
+  uintptr_t regaddr = config->base + SAM_USART_CTRLA_OFFSET;
+  uint32_t regval;
+
+  /* Reset the SERCOM by setting the SWRST bit in the CTRLA register.  When
+   * the reset completes, the SERCOM will registers will be restored to there
+   * initial state and the SERCOM will be disabled.
+   */
+
+  regval = getreg32(regaddr);
+  regval |= USART_CTRLA_SWRST;
+  putreg32(regval, regaddr);
+
+  /* Wait for the reset to complete */
+
+  while ((getreg32(regaddr) & USART_CTRLA_SWRST) != 0);
+}
+#endif
+
 /****************************************************************************
  * Name: sam_lowputc
  *

arch/arm/src/samd/sam_lowputc.h

@@ -95,6 +95,20 @@ struct sam_usart_config_s;
 int sam_usart_initialize(const struct sam_usart_config_s * const config);
 #endif
 
+/****************************************************************************
+ * Name: sam_usart_reset
+ *
+ * Description:
+ *   Reset the USART SERCOM.  This restores all SERCOM register to the
+ *   initial state and disables the SERCOM.
+ *
+ *****************************************************************************/
+
+#ifdef HAVE_USART
+struct sam_usart_config_s;
+void sam_usart_reset(const struct sam_usart_config_s * const config);
+#endif
+
 /****************************************************************************
  * Name: sam_lowputc
  *

arch/arm/src/samd/sam_serial.h

@@ -43,7 +43,6 @@
 #include <nuttx/config.h>
 
 #include "sam_config.h"
-#include "chip/sam_sercom.h"
 
 /************************************************************************************
  * Pre-processor Definitions

arch/arm/src/samd/sam_start.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/samd/sam_start.c
  *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without

arch/arm/src/samd/sam_usart.h

@@ -83,7 +83,6 @@ struct sam_usart_config_s
   uint8_t bits;       /* Number of bits (5-9) */
   uint8_t irq;        /* SERCOM IRQ number */
   uint8_t gclkgen;    /* Source GCLK generator */
-  bool isconsole;     /* True: The USART is the console device */
   bool stopbits2;     /* True: Configure with 2 stop bits instead of 1 */
   uint32_t baud;      /* Configured baud */
   port_pinset_t pad0; /* Pin configuration for PAD0 */