SAML21: Add OSC32KCTRL header file
This commit is contained in:
Gregory Nutt
parent
370917bb5c
commit
4648c45218
@ -6,7 +6,7 @@
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Ateml-42385C-SAML21_Datasheet_Preliminary-03/20/15
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -6,7 +6,7 @@
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Ateml-42385C-SAML21_Datasheet_Preliminary-03/20/15
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -6,7 +6,7 @@
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Ateml-42385C-SAML21_Datasheet_Preliminary-03/20/15
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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164
arch/arm/src/samdl/chip/saml_osc32kctrl.h
Normal file
164
arch/arm/src/samdl/chip/saml_osc32kctrl.h
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/********************************************************************************************
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* arch/arm/src/samdl/chip/saml_osc32kctrl.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_OS32KCCTRL_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_OS32KCCTRL_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* OS32KCCTRL register offsets **************************************************************/
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#define SAM_OS32KCCTRL_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */
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#define SAM_OS32KCCTRL_INTENSET_OFFSET 0x0004 /* Interrupt enable set */
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#define SAM_OS32KCCTRL_INTFLAG_OFFSET 0x0008 /* Interrupt flag status and clear */
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#define SAM_OS32KCCTRL_STATUS_OFFSET 0x000c /* Status */
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#define SAM_OS32KCCTRL_RTCCTRL_OFFSET 0x0010 /* RTC clock selection */
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#define SAM_OS32KCCTRL_XOSC32K_OFFSET 0x0014 /* 32kHz external crystal oscillator control */
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#define SAM_OS32KCCTRL_OSC32K_OFFSET 0x0018 /* 32kHz internal oscillator control */
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#define SAM_OS32KCCTRL_OSCULP32K_OFFSET 0x001c /* 32kHz ultra low power internal oscillator control */
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/* OS32KCCTRL register addresses ************************************************************/
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#define SAM_OS32KCCTRL_INTENCLR (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_INTENCLR_OFFSET)
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#define SAM_OS32KCCTRL_INTENSET (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_INTENSET_OFFSET)
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#define SAM_OS32KCCTRL_INTFLAG (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_INTFLAG_OFFSET)
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#define SAM_OS32KCCTRL_STATUS (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_STATUS_OFFSET)
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#define SAM_OS32KCCTRL_RTCCTRL (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_RTCCTRL_OFFSET)
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#define SAM_OS32KCCTRL_XOSC32K (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_XOSC32K_OFFSET)
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#define SAM_OS32KCCTRL_OSC32K (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_OSC32K_OFFSET)
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#define SAM_OS32KCCTRL_OSCULP32K (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_OSCULP32K_OFFSET)
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/* OS32KCCTRL register bit definitions ******************************************************/
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/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and
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* status registers.
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*/
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#define OS32KCCTRL_INT_XOSC32KRDY (1 << 0) /* Bit 0: XOSC32K ready interrupt */
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#define OS32KCCTRL_INT_OSC32KRDY (1 << 1) /* Bit 1: OSC32K ready interrupt */
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#define OS32KCCTRL_INT_ALL (0x00000003)
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/* RTC clock selection */
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#define OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT (0) /* Bits 0-2: RTC clock source selection */
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#define OS32KCCTRL_RTCCTRL_RTCSEL_MASK (7 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT)
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# define OS32KCCTRL_RTCCTRL_RTCSEL_ULP1K (0 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz from 32HKz internal ULP oscillator */
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# define OS32KCCTRL_RTCCTRL_RTCSEL_ULP32K (1 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz internal ULP oscillator */
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# define OS32KCCTRL_RTCCTRL_RTCSEL_OSC1K (2 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz for 32KHz internal oscillator */
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# define OS32KCCTRL_RTCCTRL_RTCSEL_XOSC1K (3 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz for 32KHz external oscillator */
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# define OS32KCCTRL_RTCCTRL_RTCSEL_OSC32K (4 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz external oscillator */
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# define OS32KCCTRL_RTCCTRL_RTCSEL_XOSC312K (5 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz external crystal oscillator */
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/* 32kHz external crystal oscillator control register */
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#define OS32KCCTRL_XOSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
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#define OS32KCCTRL_XOSC32K_XTALEN (1 << 2) /* Bit 2: Crystal oscillator enable */
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#define OS32KCCTRL_XOSC32K_EN32K (1 << 3) /* Bit 3: 32kHz Output enable */
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#define OS32KCCTRL_XOSC32K_EN1K (1 << 4) /* Bit 4: 1kHz Output enable */
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#define OS32KCCTRL_XOSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
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#define OS32KCCTRL_XOSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */
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#define OS32KCCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
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#define OS32KCCTRL_XOSC32K_STARTUP_MASK (7 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT)
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# define OS32KCCTRL_XOSC32K_STARTUP(n) ((n) << OS32KCCTRL_XOSC32K_STARTUP_SHIFT)
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# define OS32KCCTRL_XOSC32K_STARTUP_63MS (0 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 62.592 msec */
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# define OS32KCCTRL_XOSC32K_STARTUP_125MS (1 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 125.092 msec */
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# define OS32KCCTRL_XOSC32K_STARTUP_500MS (2 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 500.092 msec */
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# define OS32KCCTRL_XOSC32K_STARTUP_100MS (3 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 100.0092 msec */
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# define OS32KCCTRL_XOSC32K_STARTUP_200MS (4 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 200.0092 msec */
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# define OS32KCCTRL_XOSC32K_STARTUP_400MS (5 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 400.092 msec */
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# define OS32KCCTRL_XOSC32K_STARTUP_800MS (6 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 800.0092 msec */
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#define OS32KCCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
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/* 32kHz internal oscillator control register */
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#define OS32KCCTRL_OSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
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#define OS32KCCTRL_OSC32K_EN32K (1 << 2) /* Bit 2: 32kHz Output enable */
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#define OS32KCCTRL_OSC32K_EN1K (1 << 3) /* Bit 3: 1kHz Output enable */
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#define OS32KCCTRL_OSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
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#define OS32KCCTRL_OSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */
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#define OS32KCCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
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#define OS32KCCTRL_OSC32K_STARTUP_MASK (7 << OS32KCCTRL_OSC32K_STARTUP_SHIFT)
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# define OS32KCCTRL_OSC32K_STARTUP(n) ((n) << OS32KCCTRL_OSC32K_STARTUP_SHIFT)
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# define OS32KCCTRL_OSC32K_STARTUP_92US (0 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
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# define OS32KCCTRL_OSC32K_STARTUP_122US (1 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
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# define OS32KCCTRL_OSC32K_STARTUP_183US (2 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
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# define OS32KCCTRL_OSC32K_STARTUP_305US (3 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
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# define OS32KCCTRL_OSC32K_STARTUP_549US (4 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
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# define OS32KCCTRL_OSC32K_STARTUP_1MS (5 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
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# define OS32KCCTRL_OSC32K_STARTUP_2MS (6 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
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# define OS32KCCTRL_OSC32K_STARTUP_4MS (7 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
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#define OS32KCCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
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#define OS32KCCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */
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#define OS32KCCTRL_OSC32K_CALIB_MASK (0x7f << OS32KCCTRL_OSC32K_CALIB_SHIFT)
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# define OS32KCCTRL_OSC32K_CALIB(n) ((n) << OS32KCCTRL_OSC32K_CALIB_SHIFT)
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/* 32kHz ultra low power internal oscillator control register */
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#define OS32KCCTRL_OSCULP32K_CALIB_SHIFT (8) /* Bits 0-12: Oscillator Calibration */
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#define OS32KCCTRL_OSCULP32K_CALIB_MASK (31 << OS32KCCTRL_OSCULP32K_CALIB_SHIFT)
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# define OS32KCCTRL_OSCULP32K_CALIB(n) ((n) << OS32KCCTRL_OSCULP32K_CALIB_SHIFT)
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#define OS32KCCTRL_OSCULP32K_WRTLOCK (1 << 7) /* Bit 7: Write Lock */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAML21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_OS32KCCTRL_H */
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@ -6,7 +6,7 @@
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Ateml-42385C-SAML21_Datasheet_Preliminary-03/20/15
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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