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Board specific code moved to boards directory and ipv6 support added

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Added support to crashdump for rx65n on sbram
Board specific code moved to boards directory and ipv6 support added
This commit is contained in:
Gregory Nutt 2020-05-05 18:16:17 -06:00
parent 9607152e68
commit 4664642cf7
36 changed files with 2236 additions and 1470 deletions
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43
arch/renesas/include/rx65n/irq.h
View File

@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/include/rx65n/irq.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_RENESAS_INCLUDE_RX65N_IRQ_H
#define __ARCH_RENESAS_INCLUDE_RX65N_IRQ_H
@ -603,7 +588,7 @@
/* Saved to the stacked by up_vector */
/* Vector table offsets *************************************************************/
/* Vector table offsets */
/* Trap instruction */

41
arch/renesas/include/rx65n/limits.h
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@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/include/rx65n/limits.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_RENESAS_INCLUDE_RX65N_LIMITS_H
#define __ARCH_RENESAS_INCLUDE_RX65N_LIMITS_H

41
arch/renesas/include/rx65n/types.h
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@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/include/rx65n/types.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/* This file should never be included directly but, rather, only indirectly\
* through sys/types.h

2
arch/renesas/src/rx65n/Make.defs
View File

@ -45,7 +45,7 @@ CMN_CSRCS += up_stackframe.c up_udelay.c up_unblocktask.c up_usestack.c
CHIP_ASRCS = rx65n_vector.S
CHIP_CSRCS = rx65n_lowputc.c rx65n_serial.c rx65n_copystate.c rx65n_irq.c
CHIP_CSRCS += rx65n_schedulesigaction.c rx65n_sigdeliver.c rx65n_initialstate.c
CHIP_CSRCS += rx65n_hardware_setup.c rx65n_icu.c rx65n_port.c rx65n_sci.c
CHIP_CSRCS += rx65n_hardware_setup.c rx65n_port.c rx65n_sci.c
CHIP_CSRCS += rx65n_cgc.c rx65n_dumpstate.c rx65n_vector_table.c
CHIP_CSRCS += rx65n_timerisr.c rx65n_sbram.c

41
arch/renesas/src/rx65n/rx65n_cmtw.h
View File

@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cmtw.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Surya Prakash <surya.prakash@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_CMTW_H
#define __ARCH_RENESAS_SRC_RX65N_CMTW_H

43
arch/renesas/src/rx65n/rx65n_cmtw0.h
View File

@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cmtw0.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Surya Prakash <surya.prakash@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_CMTW0_H
#define __ARCH_RENESAS_SRC_RX65N_CMTW0_H
@ -60,7 +45,7 @@
/****************************************************************************
* Public Function Prototypes
***************************************************************************/
****************************************************************************/
/****************************************************************************
* Name: rx65n_cmtw0_create

128
arch/renesas/src/rx65n/rx65n_definitions.h
View File

@ -431,20 +431,64 @@
#define ETH_PSR_LMON (1)
/* EDMAC Transmit Request Register's bit */
#define ETHD_EDRRR_TR (1) /* Transmit Request */
/* EDMAC Receive Request Register's bit */
#define ETHD_EDRRR_RR (1) /* Receive descriptor read,
* and receive function is enabled
*/
/* Transmit Interrupt Setting Register's bit */
#define ETHD_TRIMD_TIS (1) /* Transmit Interrupt is enabled */
#define ETHD_TRIMD_TIM (1<<4) /* Write-back complete interrupt mode */
/* Receive Method Control Register's bit */
/* Receive Method Control Register's bit */
#define ETHD_RMCR_RNR (1) /* EDRRR.RR bit (receive request bit) is not
* set to 0 when one frame has been received
*/
/* FIFO Depth Register's bit */
#define ETHD_FDR_RFD (7) /* Receive FIFO Depth */
#define ETHD_FDR_TFD (7<<8) /* Transmit FIFO Depth */
/* ETHERC/EDMAC Transmit/Receive Status Copy Enable Register's bit */
#define ETHD_TRSCER_RRFCE (1<<4) /* RRF Flag Copy Enable */
#define ETHD_TRSCER_RMAFCE (1<<7) /* RMAF Flag Copy Enable */
/* Broadcast Frame Receive Count Setting Register's field */
#define ETH_BCFRR_BCF (0x0000) /* Broadcast Frame Continuous Receive Count Setting */
/* PHY Interface Register's bit and values */
#define ETH_PIR_MDC (1) /* MII/RMII Management Data Clock */
#define ETH_PIR_MMD (1<<1) /* MII/RMII Management Mode */
#define ETH_PIR_MDO (1<<2) /* MII/RMII Management Data-Out */
#define ETH_PIR_MDI (1<<3) /* MII/RMII Management Data-In */
#define ETH_PIR_RESET_ALL (0x00000000) /* Reset All Flags of PIR */
#define ETH_PIR_SET_MDC (0x00000001) /* Setting MDC of PIR */
#define ETH_PIR_SET_MMD (0x00000002) /* Setting MMD of PIR */
#define ETH_PIR_SET_MMD_MDC (0x00000003) /* Setting MMD and MDC */
#define ETH_PIR_SET_MDO_MMD (0x00000006) /* Setting MDO and MMD */
#define ETH_PIR_SET_MDO_MMD_MDC (0x00000007) /* Setting MDO, MMD and MDC */
/* Ethernet Control Register's bit and value */
#define ETH_PFENET_MII_MODE (0x10)
#define ETH_PFENET_RMII_MODE (0x00)
/* End Ethernet and EDMAC Interface */
/* General Values LED: */
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
# define LED_ON (0)
# define LED_OFF (1)
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
# define LED_ON (1)
# define LED_OFF (0)
#else
# error "No Selection for PORT definition in rx65n_port.c"
#endif
/* Bit Set Values */
#define SET_BIT_HIGH (1)
@ -499,33 +543,33 @@
#define RX65N_RTC_RCR4 (RX65N_RTC_BASE + RX65N_RTC_RCR4_OFFSET)
#define RX65N_RTC_RADJ (RX65N_RTC_BASE + RX65N_RTC_RADJ_OFFSET)
#define RTC_RTC_ALRDIS (0x00)
#define RTC_RCR4_RCKSEL (0x00)
#define RTC_RCR3_RTCEN (0x01)
#define RTC_RCR3_RTCDV (0x02)
#define RTC_RCR2_START (0x01)
#define RTC_RCR2_CNTMD (0x00)
#define RTC_RCR2_RESET (0x01)
#define RTC_ALARM_INT_ENABLE (0x01)
#define RTC_CARRY_INT_ENABLE (0x02)
#define RTC_PERIOD_INT_ENABLE (0x04)
#define RTC_PERIODIC_INT_PERIOD_1 (0xe0)
#define _04_FOUR_READ_COUNT (0x04)
#define RTC_1_64_SEC_CYCLE (0x0005b8d9)
#define _0F_RTC_PRIORITY_LEVEL15 (0x0f)
#define RTC_RCR1_CUP (0x02)
#define RX65N_SUBCLKOSC_SOSCCR (0x00080033)
#define SUBCLKOSC_SOSCCR_SOSTP (0x01)
#define RX65N_SUBCLKOSC_SOSCWTCR (0x0008c293)
#define RTC_SOSCWTCR_VALUE (0x21)
#define RTC_DUMMY_READ (3)
#define _00_RTC_PRIORITY_LEVEL0 (0)
#define _04_RTC_PERIOD_INT_ENABLE (0x04)
#define RTC_RTC_CARRYDIS (0xe5)
#define RTC_RTC_PERDIS (0xe3)
#define RTC_RADJ_INITVALUE (0x0)
#define RTC_RCR2_AADJE (0x10)
#define RTC_RCR2_AADJP (0x20)
#define RTC_RTC_ALRDIS (0x00)
#define RTC_RCR4_RCKSEL (0x00)
#define RTC_RCR3_RTCEN (0x01)
#define RTC_RCR3_RTCDV (0x02)
#define RTC_RCR2_START (0x01)
#define RTC_RCR2_CNTMD (0x00)
#define RTC_RCR2_RESET (0x01)
#define RTC_ALARM_INT_ENABLE (0x01)
#define RTC_CARRY_INT_ENABLE (0x02)
#define RTC_PERIOD_INT_ENABLE (0x04)
#define RTC_PERIODIC_INT_PERIOD_1 (0xe0)
#define _04_FOUR_READ_COUNT (0x04)
#define RTC_1_64_SEC_CYCLE (0x0005b8d9)
#define _0F_RTC_PRIORITY_LEVEL15 (0x0f)
#define RTC_RCR1_CUP (0x02)
#define RX65N_SUBCLKOSC_SOSCCR (0x00080033)
#define SUBCLKOSC_SOSCCR_SOSTP (0x01)
#define RX65N_SUBCLKOSC_SOSCWTCR (0x0008c293)
#define RTC_SOSCWTCR_VALUE (0x21)
#define RTC_DUMMY_READ (3)
#define _00_RTC_PRIORITY_LEVEL0 (0)
#define _04_RTC_PERIOD_INT_ENABLE (0x04)
#define RTC_RTC_CARRYDIS (0xe5)
#define RTC_RTC_PERDIS (0xe3)
#define RTC_RADJ_INITVALUE (0x0)
#define RTC_RCR2_AADJE (0x10)
#define RTC_RCR2_AADJP (0x20)
#if defined(CONFIG_RTC) || defined(CONFIG_RTC_DRIVER)
@ -534,8 +578,8 @@
#endif
#define RX65N_RTC_WAIT_PERIOD 184
#define RTC_RCR2_HR24 (0x40)
#define RTC_PERIODIC_INTERRUPT_2_SEC (0xf)
#define RTC_RCR2_HR24 (0x40)
#define RTC_PERIODIC_INTERRUPT_2_SEC (0xf)
/* StandBy RAM Address */
@ -569,7 +613,9 @@ enum E_RX_SCI
RX_SCI_SISR_OFFSET,
RX_SCI_SPMR_OFFSET,
RX_SCI_THRHL_OFFSET,
RX_SCI_THRL_OFFSET,
RX_SCI_RDRHL_OFFSET,
RX_SCI_RDRL_OFFSET,
RX_SCI_MDDR_OFFSET
};
#endif /* __ASSEMBLER__ */

692
arch/renesas/src/rx65n/rx65n_eth.c
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File diff suppressed because it is too large Load Diff

54
arch/renesas/src/rx65n/rx65n_eth.h
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@ -1,50 +1,36 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_eth.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H
#define __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H
/****************************************************************************
* Included Files
***************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
***************************************************************************/
****************************************************************************/
/* Understood PHY types */
@ -54,10 +40,6 @@
#define EMAC0_INTF 0
/****************************************************************************
* Public Functions
***************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
@ -69,10 +51,6 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
***************************************************************************/
/****************************************************************************
* Function: rx65n_ethinitialize
*
@ -135,4 +113,4 @@ void rx65n_txtimeout_expiry(int argc, uint32_t arg, ...);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H */
#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H */

44
arch/renesas/src/rx65n/rx65n_hardware_setup.c
View File

@ -1,36 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_hardware_setup.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Surya <surya.prakash@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
@ -82,7 +66,6 @@ void r_system_init(void)
/* Set peripheral settings */
r_cgc_create();
r_icu_create();
r_port_create();
#ifdef CONFIG_RX65N_EMAC0
@ -98,9 +81,6 @@ void r_system_init(void)
/* Enable protection */
SYSTEM.PRCR.WORD = 0xa500;
r_config_icu_software_start();
r_config_icu_software2_start();
}
/****************************************************************************

41
arch/renesas/src/rx65n/rx65n_initialstate.c
View File

@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_initialstate.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
****************************************************************************/
/****************************************************************************
* Included Files

43
arch/renesas/src/rx65n/rx65n_lowputc.c
View File

@ -1,35 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_lowputc.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
@ -51,7 +36,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration **********************************************************/
/* Configuration ************************************************************/
/* Is there a serial console? */
@ -160,7 +145,7 @@
#define RX_SMR_VALUE (RX_SMR_MODE|RX_SMR_PARITY|RX_SMR_STOP)
/* Clocking ***************************************************************/
/* Clocking *****************************************************************/
#define RX_DIVISOR (8 * RX_SCI_BAUD)
#define RX_BRR ((RX_PCLKB / RX_DIVISOR) - 1)

41
arch/renesas/src/rx65n/rx65n_macrodriver.h
View File

@ -1,35 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_macrodriver.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
@ -37,7 +22,7 @@
#define __ARCH_RENESAS_SRC_RX65N_STATUS_H
/****************************************************************************
* Pre-processor Definitions
* Included Files
****************************************************************************/
#include "rx65n/iodefine.h"

267
arch/renesas/src/rx65n/rx65n_port.c
View File

@ -25,6 +25,7 @@
#include "rx65n_macrodriver.h"
#include "rx65n_port.h"
#include "arch/board/board.h"
#include "arch/board/rx65n_gpio.h"
/****************************************************************************
* Public Functions
@ -39,87 +40,8 @@
void r_port_create(void)
{
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
/* LED_PORTINIT(0); */
PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT0.PMR.BYTE = 0x00u;
PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
_20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
PORT5.PMR.BYTE = 0x00u;
PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
_80_PDR5_DEFAULT;
PORT7.PMR.BYTE = 0x00u;
PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
PORT9.PMR.BYTE = 0x00u;
PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
PORTJ.PMR.BYTE = 0x00u;
PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
#elif defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
/* LED_PORTINIT(0); */
PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT0.PMR.BYTE = 0x00u;
PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
_20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
PORT5.PMR.BYTE = 0x00u;
PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
_80_PDR5_DEFAULT;
PORT7.PMR.BYTE = 0x00u;
PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
PORT9.PMR.BYTE = 0x00u;
PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
PORTJ.PMR.BYTE = 0x00u;
PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
LED_PORTINIT(0);
/* SCI0(UART) direction */
PORT2.PODR.BIT.B2 = 0; PORT2.PMR.BIT.B2 = 0; PORT2.PDR.BIT.B2 = 1;
/* SCI2(UART) direction */
PORT1.PODR.BIT.B4 = 0; PORT1.PMR.BIT.B4 = 0; PORT1.PDR.BIT.B4 = 1;
/* SCI5(UART) direction */
PORTC.PODR.BIT.B4 = 0; PORTC.PMR.BIT.B4 = 0; PORTC.PDR.BIT.B4 = 1;
/* SCI6(UART) direction */
PORT3.PODR.BIT.B4 = 0; PORT3.PMR.BIT.B4 = 0; PORT3.PDR.BIT.B4 = 1;
/* SCI8(RS485) direction */
PORTC.PODR.BIT.B5 = 0; PORTC.PMR.BIT.B5 = 0; PORTC.PDR.BIT.B5 = 1;
#else
# error "No Selection for PORT definition in rx65n_port.c"
#endif
led_port_create();
sci_port_create();
}
#ifdef CONFIG_RX65N_EMAC0
@ -157,187 +79,4 @@ void r_ether_port_configuration(void)
PORT0.PMR.BIT.B5 = 0;
PORT0.PMR.BIT.B7 = 0;
}
void r_ether_pheriperal_enable(void)
{
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
/* TODO */
#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
/* Set ET0_TX_CLK pin */
MPC.PC4PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B4 = 1u;
/* Set ET0_RX_CLK pin */
MPC.P76PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B6 = 1u;
/* Set ET0_TX_EN pin */
MPC.P80PFS.BYTE = 0x11u;
PORT8.PMR.BIT.BT0 = 1u;
/* Set ET0_ETXD3 pin */
MPC.PC6PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B6 = 1u;
/* Set ET0_ETXD2 pin */
MPC.PC5PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B5 = 1u;
/* Set ET0_ETXD1 pin */
MPC.P82PFS.BYTE = 0x11u;
PORT8.PMR.BIT.B2 = 1u;
/* Set ET0_ETXD0 pin */
MPC.P81PFS.BYTE = 0x11u;
PORT8.PMR.BIT.B1 = 1u;
/* Set ET0_TX_ER pin */
MPC.PC3PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B3 = 1u;
/* Set ET0_RX_DV pin */
MPC.PC2PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B2 = 1u;
/* Set ET0_ERXD3 pin */
MPC.PC0PFS.BYTE = 0x11u;
PORTC.PMR.BIT.BT0 = 1u;
/* Set ET0_ERXD2 pin */
MPC.PC1PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B1 = 1u;
/* Set ET0_ERXD1 pin */
MPC.P74PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B4 = 1u;
/* Set ET0_ERXD0 pin */
MPC.P75PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B5 = 1u;
/* Set ET0_RX_ER pin */
MPC.P77PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B7 = 1u;
/* Set ET0_CRS pin */
MPC.P83PFS.BYTE = 0x11u;
PORT8.PMR.BIT.B3 = 1u;
/* Set ET0_COL pin */
MPC.PC7PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B7 = 1u;
/* Set ET0_MDC pin */
MPC.P72PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B2 = 1u;
/* Set ET0_MDIO pin */
MPC.P71PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B1 = 1u;
/* Set ET0_LINKSTA pin */
MPC.P54PFS.BYTE = 0x11u;
PORT5.PMR.BIT.B4 = 1u;
/* Set ET0_LINKSTA pin */
MPC.P34PFS.BYTE = 0x11u;
PORT3.PMR.BIT.B4 = 1u;
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
/* Set ET0_MDC(PA4_ET_MDC) pin */
MPC.PA4PFS.BYTE = 0x11u;
PORTA.PMR.BIT.B4 = 1u;
/* Set ET0_MDIO(PA3_ET_MDIO) pin */
MPC.PA3PFS.BYTE = 0x11u;
PORTA.PMR.BIT.B3 = 1u;
/* Set REF50CK0 (PB2_ET_CLK) pin */
MPC.PB2PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B2 = 1u;
/* Set RMII0_CRS_DV(PB7_ET_CRS) pin */
MPC.PB7PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B7 = 1u;
/* Set RMII0_RXD0(PB1_ET_RXD0) pin */
MPC.PB1PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B1 = 1u;
/* Set RMII0_RXD1(PB0_ET_RXD1) pin */
MPC.PB0PFS.BYTE = 0x12u;
PORTB.PMR.BIT.BT0 = 1u;
/* Set RMII0_RX_ER(PB3_ET_RXER) pin */
MPC.PB3PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B3 = 1u;
/* Set RMII0_ETXD0(PB5_ET_TXD0) pin */
MPC.PB5PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B5 = 1u;
/* Set RMII0_ETXD1(PB6_ET_TXD1) pin */
MPC.PB6PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B6 = 1u;
/* Set RMII0_TXD_EN(PB4_ET_TXEN) pin */
MPC.PB4PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B4 = 1u;
/* Set RXD2 pin */
MPC.P52PFS.BYTE = 0x0au;
PORT5.PMR.BIT.B2 = 1u;
/* Set TXD2 pin */
PORT5.PODR.BYTE |= 0x01u;
MPC.P50PFS.BYTE = 0x0au;
PORT5.PDR.BYTE |= 0x01u;
/* Set ET0_LINKSTA(PA5_ET_LINK) pin */
MPC.PA5PFS.BYTE = 0x11u;
PORTA.PMR.BIT.B5 = 1u;
/* Set ETHER reset(PA6_ET_RST) pin */
MPC.PA6PFS.BYTE = 0x12u;
PORTA.PMR.BIT.B6 = 1u;
#endif
}
#endif

59
arch/renesas/src/rx65n/rx65n_port.h
View File

@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_port.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_PORT_H
#define __ARCH_RENESAS_SRC_RX65N_PORT_H
@ -283,7 +268,7 @@
/****************************************************************************
* Public Function Prototypes
***************************************************************************/
****************************************************************************/
/****************************************************************************
* Name: r_port_create
@ -317,22 +302,6 @@ void r_port_create(void);
#ifdef CONFIG_RX65N_EMAC0
void r_ether_port_configuration(void);
/****************************************************************************
* Name: r_ether_pheriperal_enable
*
* Description:
* Ethernet Pheriperal enabling
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void r_ether_pheriperal_enable(void);
#endif
#endif /* __ARCH_RENESAS_SRC_RX65N_PORT_H */

12
arch/renesas/src/rx65n/rx65n_rtc.c
View File

@ -91,7 +91,7 @@ struct alm_cbinfo_s
struct prd_cbinfo_s
{
volatile periodiccb_t prd_cb; /* Client callback function */
volatile FAR void *prd_arg; /* Argument to pass with the callback function */
volatile FAR void *prd_arg; /* Argument to pass with the callback function */
};
#endif
@ -562,7 +562,9 @@ int up_rtc_settime(FAR const struct timespec *tp)
volatile uint8_t dummy_byte;
volatile uint16_t dummy_word;
/* Break out the time values (note that the time is set only to units of seconds) */
/* Break out the time values (note that the time is set only to units of
* seconds)
*/
(void)gmtime_r(&tp->tv_sec, &newtime);
rtc_dumptime(&newtime, "Setting time");
@ -1050,7 +1052,7 @@ int rx65n_rtc_cancelperiodic(void)
IEN(RTC, PRD) = 0U;
/* Clear IR flag of PRD interrupt*/
/* Clear IR flag of PRD interrupt */
IR(RTC, PRD) = 0U;
@ -1059,7 +1061,7 @@ int rx65n_rtc_cancelperiodic(void)
RTC.RCR1.BIT.PIE = 0U;
while (0U != RTC.RCR1.BIT.PIE)
{
/* Wait for this write to complete.*/
/* Wait for this write to complete. */
}
return OK;
@ -1071,7 +1073,7 @@ int rx65n_rtc_cancelperiodic(void)
int rx65n_rtc_cancelcarry(void)
{
/* Clear IR flag of CUP interrupt*/
/* Clear IR flag of CUP interrupt */
IR(PERIB, INTB176) = 0U;

6
arch/renesas/src/rx65n/rx65n_schedulesigaction.c
View File

@ -120,18 +120,20 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_pc = g_current_regs[REG_PC];
tcb->xcp.saved_sr = g_current_regs[REG_PSW];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
g_current_regs[REG_PC] = (uint32_t)up_sigdeliver;
g_current_regs[REG_PSW] |= 0x00030000;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
*/
up_copystate(tcb->xcp.regs, (uint32_t *)&g_current_regs);
up_copystate(tcb->xcp.regs, (uint32_t *)g_current_regs);
}
}
@ -150,7 +152,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
tcb->xcp.saved_sr = tcb->xcp.regs[REG_PSW];
tcb->xcp.saved_sr = tcb->xcp.regs[REG_PSW];
/* Then set up to vector to the trampoline with interrupts
* disabled

368
arch/renesas/src/rx65n/rx65n_sci.c
View File

@ -30,6 +30,7 @@
#include "up_arch.h"
#include "up_internal.h"
#include "rx65n_definitions.h"
#include "arch/board/rx65n_gpio.h"
/****************************************************************************
* Public Data
@ -367,163 +368,6 @@ static inline void rx_mpc_disable(void)
SYSTEM.PRCR.WORD = 0xa500u;
}
/****************************************************************************
* Name: sci0_init_port
*
* Description:
* SCI0 Initialization
****************************************************************************/
#ifdef CONFIG_RX65N_SCI0
static inline void sci0_init_port(void)
{
#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
/* Set RXD0 pin (P21) */
MPC.P21PFS.BYTE = 0x0au;
PORT2.PMR.BIT.B1 = 1u;
/* Set TXD0 pin (P20) */
PORT2.PODR.BIT.BT0 = 1u;
MPC.P20PFS.BYTE = 0x0au;
PORT2.PDR.BIT.BT0 = 1u;
PORT2.PMR.BIT.BT0 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
}
#endif
/****************************************************************************
* Name: sci1_init_port
*
* Description:
* SCI1 Initialization
****************************************************************************/
#ifdef CONFIG_RX65N_SCI1
static inline void sci1_init_port(void)
{
#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB
/* Set RXD1 pin (PF2) */
MPC.PF2PFS.BYTE = 0x0au;
PORTF.PMR.BIT.B2 = 1u;
/* Set TXD1 pin (PF1) */
PORTF.PODR.BIT.B1 = 1u;
MPC.PF1PFS.BYTE = 0x0au;
PORTF.PDR.BIT.B1 = 1u;
PORTF.PMR.BIT.B1 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */
#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
/* Set RXD1 pin (P30) */
MPC.P30PFS.BYTE = 0x0au;
PORT3.PMR.BIT.BT0 = 1u;
/* Set TXD1 pin (P26) */
PORT2.PODR.BIT.B6 = 1u;
MPC.P26PFS.BYTE = 0x0au;
PORT2.PDR.BIT.B6 = 1u;
PORT2.PMR.BIT.B6 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
}
#endif
/****************************************************************************
* Name: sci2_init_port
*
* Description:
* SCI2 Initialization
****************************************************************************/
#ifdef CONFIG_RX65N_SCI2
static inline void sci2_init_port(void)
{
#ifdef CONFIG_ARCH_BOARD_RX65N_RSK1MB
/* Set RXD2 pin (P52) */
MPC.P52PFS.BYTE = 0x0au;
PORT5.PMR.BIT.B2 = 1u;
/* Set TXD2 pin (P50) */
PORT5.PODR.BIT.BT0 = 1u;
MPC.P50PFS.BYTE = 0x0au;
PORT5.PDR.BIT.BT0 = 1u;
PORT5.PMR.BIT.BT0 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_RSK1MB */
#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB
/* Set RXD2 pin (P52) */
MPC.P52PFS.BYTE = 0x0au;
PORT5.PMR.BIT.B2 = 1u;
/* Set TXD2 pin (P50) */
PORT5.PODR.BIT.BT0 = 1u;
MPC.P50PFS.BYTE = 0x0au;
PORT5.PDR.BIT.BT0 = 1u;
PORT5.PMR.BIT.BT0 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */
#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
/* Set RXD2 pin (P12) */
MPC.P12PFS.BYTE = 0x0au;
PORT1.PMR.BIT.B2 = 1u;
/* Set TXD2 pin (P13) */
PORT1.PODR.BIT.B3 = 1u;
MPC.P13PFS.BYTE = 0x0au;
PORT1.PDR.BIT.B3 = 1u;
PORT1.PMR.BIT.B3 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
}
#endif
/****************************************************************************
* Name: sci3_init_port
*
* Description:
* SCI3 Initialization
****************************************************************************/
#ifdef CONFIG_RX65N_SCI3
static inline void sci3_init_port(void)
{
/* Set RXD3 pin (PXX)
* MPC.PXXPFS.BYTE = 0x0au;
* PORTX.PMR.BIT.BX = 1u;
* Set TXD3 pin (PXX)
* PORTX.PODR.BIT.BX = 1u;
* MPC.PXXPFS.BYTE = 0x0au;
* PORTX.PDR.BIT.BX = 1u;
* PORTX.PMR.BIT.BX = 1u;
*/
#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
/* Set RXD2 pin (P25) */
MPC.P25PFS.BYTE = 0x0au;
PORT2.PMR.BIT.B5 = 1u;
/* Set TXD2 pin (P23) */
PORT2.PODR.BIT.B3 = 1u;
MPC.P23PFS.BYTE = 0x0au;
PORT2.PDR.BIT.B3 = 1u;
PORT2.PMR.BIT.B3 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
}
#endif
/****************************************************************************
* Name: sci4_init_port
*
@ -546,60 +390,6 @@ static inline void sci4_init_port(void)
}
#endif
/****************************************************************************
* Name: sci5_init_port
*
* Description:
* SCI5 Initialization
****************************************************************************/
#ifdef CONFIG_RX65N_SCI5
static inline void sci5_init_port(void)
{
#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
/* Set RXD3 pin (PC2) */
MPC.PC2PFS.BYTE = 0x0au;
PORTC.PMR.BIT.B2 = 1u;
/* Set TXD3 pin (PC3) */
PORTC.PODR.BIT.B3 = 1u;
MPC.PC3PFS.BYTE = 0x0au;
PORTC.PDR.BIT.B3 = 1u;
PORTC.PMR.BIT.B3 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
}
#endif
/****************************************************************************
* Name: sci6_init_port
*
* Description:
* SCI6 Initialization
****************************************************************************/
#ifdef CONFIG_RX65N_SCI6
static inline void sci6_init_port(void)
{
#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
/* Set RXD6 pin (P33) */
MPC.P33PFS.BYTE = 0x0au;
PORT3.PMR.BIT.B3 = 1u;
/* Set TXD6 pin (P32) */
PORT3.PODR.BIT.B2 = 1u;
MPC.P32PFS.BYTE = 0x0au;
PORT3.PDR.BIT.B2 = 1u;
PORT3.PMR.BIT.B2 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
}
#endif
/****************************************************************************
* Name: sci7_init_port
*
@ -622,46 +412,6 @@ static inline void sci7_init_port(void)
}
#endif
/****************************************************************************
* Name: sci8_init_port
*
* Description:
* SCI8 Initialization
****************************************************************************/
#ifdef CONFIG_RX65N_SCI8
static inline void sci8_init_port(void)
{
#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB
/* Set RXD8 pin (PJ1) */
MPC.PJ1PFS.BYTE = 0x0au;
PORTJ.PMR.BIT.B1 = 1u;
/* Set TXD8 pin (PJ2) */
PORTJ.PODR.BIT.B2 = 1u;
MPC.PJ2PFS.BYTE = 0x0au;
PORTJ.PDR.BIT.B2 = 1u;
PORTJ.PMR.BIT.B2 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */
#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
/* Set RXD8 pin (PC6) */
MPC.PC6PFS.BYTE = 0x0au;
PORTC.PMR.BIT.B6 = 1u;
/* Set TXD8 pin (PC7) */
PORTC.PODR.BIT.B7 = 1u;
MPC.PC7PFS.BYTE = 0x0au;
PORTC.PDR.BIT.B7 = 1u;
PORTC.PMR.BIT.B7 = 1u;
#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
}
#endif
/****************************************************************************
* Name: sci9_init_port
*
@ -728,42 +478,6 @@ static inline void sci11_init_port(void)
}
#endif
/****************************************************************************
* Name: sci12_init_port
*
* Description:
* SCI12 Initialization
****************************************************************************/
#ifdef CONFIG_RX65N_SCI12
static inline void sci12_init_port(void)
{
#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB
/* Set RXD12 pin */
MPC.PE2PFS.BYTE = 0x0cu;
PORTE.PMR.BYTE |= 0x04u;
/* Set TXD12 pin */
PORTE.PODR.BYTE |= 0x02u;
MPC.PE1PFS.BYTE = 0x0cu;
PORTE.PDR.BYTE |= 0x02u;
#endif
/* Set RXD12 pin (PXX)
* MPC.PXXPFS.BYTE = 0x0au;
* PORTX.PMR.BIT.BX = 1u;
* Set TXD12 pin (PXX)
* PORTX.PODR.BIT.BX = 1u;
* MPC.PXXPFS.BYTE = 0x0au;
* PORTX.PDR.BIT.BX = 1u;
* PORTX.PMR.BIT.BX = 1u;
*/
}
#endif
/****************************************************************************
* Name: r_sci0_create
*
@ -906,16 +620,16 @@ void r_sci1_create(void)
{
rx_mpc_enable();
MSTP(SCI1) = 0u; /* Cancel SCI1 module stop state */
IPR(SCI1, RXI1) = 15; /* Set interrupt priority */
IPR(SCI1, TXI1) = 15; /* Set interrupt priority */
SCI1.SCR.BYTE = 0u; /* Clear the control register */
IPR(SCI1, RXI1) = 15; /* Set interrupt priority */
IPR(SCI1, TXI1) = 15; /* Set interrupt priority */
SCI1.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
SCI1.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED;
SCI1.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */
SCI1.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */
SCI1.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */
SCI1.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */
SCI1.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */
SCI1.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */
/* Set control registers */
@ -1035,8 +749,8 @@ void r_sci2_create(void)
{
rx_mpc_enable();
MSTP(SCI2) = 0u; /* Cancel SCI2 module stop state */
IPR(SCI2, RXI2) = 15; /* Set interrupt priority */
IPR(SCI2, TXI2) = 15; /* Set interrupt priority */
IPR(SCI2, RXI2) = 15; /* Set interrupt priority */
IPR(SCI2, TXI2) = 15; /* Set interrupt priority */
SCI2.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@ -1163,8 +877,8 @@ void r_sci3_create(void)
{
rx_mpc_enable();
MSTP(SCI3) = 0u; /* Cancel SCI3 module stop state */
IPR(SCI3, RXI3) = 15; /* Set interrupt priority */
IPR(SCI3, TXI3) = 15; /* Set interrupt priority */
IPR(SCI3, RXI3) = 15; /* Set interrupt priority */
IPR(SCI3, TXI3) = 15; /* Set interrupt priority */
SCI3.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@ -1223,8 +937,8 @@ void r_sci3_stop(void)
{
SCI3.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI3.SCR.BIT.RE = 0u; /* Disable serial receive */
SCI3.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
SCI3.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
SCI3.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
SCI3.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI3, TXI3) = 0u;
ICU.GENBL0.BIT.EN6 = 0u;
IR(SCI3, TXI3) = 0u;
@ -1291,9 +1005,9 @@ MD_STATUS r_sci3_serial_send(uint8_t * const tx_buf, uint16_t tx_num)
void r_sci4_create(void)
{
rx_mpc_enable();
MSTP(SCI4) = 0u; /* Cancel SCI4 module stop state */
IPR(SCI4, RXI4) = 15; /* Set interrupt priority */
IPR(SCI4, TXI4) = 15; /* Set interrupt priority */
MSTP(SCI4) = 0u; /* Cancel SCI4 module stop state */
IPR(SCI4, RXI4) = 15; /* Set interrupt priority */
IPR(SCI4, TXI4) = 15; /* Set interrupt priority */
SCI4.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@ -1423,8 +1137,8 @@ void r_sci5_create(void)
{
rx_mpc_enable();
MSTP(SCI5) = 0u; /* Cancel SCI0 module stop state */
IPR(SCI5, RXI5) = 15; /* Set interrupt priority */
IPR(SCI5, TXI5) = 15; /* Set interrupt priority */
IPR(SCI5, RXI5) = 15; /* Set interrupt priority */
IPR(SCI5, TXI5) = 15; /* Set interrupt priority */
SCI5.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@ -1483,8 +1197,8 @@ void r_sci5_stop(void)
{
SCI5.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI5.SCR.BIT.RE = 0u; /* Disable serial receive */
SCI5.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
SCI5.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
SCI5.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
SCI5.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI5, TXI5) = 0u;
ICU.GENBL0.BIT.EN10 = 0u;
IR(SCI5, TXI5) = 0u;
@ -1612,8 +1326,8 @@ void r_sci6_stop(void)
{
SCI6.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI6.SCR.BIT.RE = 0u; /* Disable serial receive */
SCI6.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
SCI6.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
SCI6.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
SCI6.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI6, TXI6) = 0u;
ICU.GENBL0.BIT.EN12 = 0u;
IR(SCI6, TXI6) = 0u;
@ -1680,9 +1394,9 @@ MD_STATUS r_sci6_serial_send(uint8_t * const tx_buf, uint16_t tx_num)
void r_sci7_create(void)
{
rx_mpc_enable();
MSTP(SCI7) = 0u; /* Cancel SCI7 module stop state */
IPR(SCI7, RXI7) = 15; /* Set interrupt priority */
IPR(SCI7, TXI7) = 15; /* Set interrupt priority */
MSTP(SCI7) = 0u; /* Cancel SCI7 module stop state */
IPR(SCI7, RXI7) = 15; /* Set interrupt priority */
IPR(SCI7, TXI7) = 15; /* Set interrupt priority */
SCI7.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@ -1743,7 +1457,7 @@ void r_sci7_stop(void)
SCI7.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI7.SCR.BIT.RE = 0u; /* Disable serial receive */
SCI7.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
SCI7.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
SCI7.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI7, TXI7) = 0u;
IR(SCI7, TXI7) = 0u;
IEN(SCI7, RXI7) = 0u;
@ -1810,9 +1524,9 @@ MD_STATUS r_sci7_serial_send(uint8_t * const tx_buf, uint16_t tx_num)
void r_sci8_create(void)
{
rx_mpc_enable();
MSTP(SCI8) = 0u; /* Cancel SCI8 module stop state */
IPR(SCI8, RXI8) = 15; /* Set interrupt priority */
IPR(SCI8, TXI8) = 15; /* Set interrupt priority */
MSTP(SCI8) = 0u; /* Cancel SCI8 module stop state */
IPR(SCI8, RXI8) = 15; /* Set interrupt priority */
IPR(SCI8, TXI8) = 15; /* Set interrupt priority */
SCI8.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@ -1873,7 +1587,7 @@ void r_sci8_stop(void)
SCI8.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI8.SCR.BIT.RE = 0u; /* Disable serial receive */
SCI8.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
SCI8.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
SCI8.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI8, TXI8) = 0u;
IR(SCI8, TXI8) = 0u;
IEN(SCI8, RXI8) = 0u;
@ -1940,9 +1654,9 @@ MD_STATUS r_sci8_serial_send(uint8_t * const tx_buf, uint16_t tx_num)
void r_sci9_create(void)
{
rx_mpc_enable();
MSTP(SCI9) = 0u; /* Cancel SCI9 module stop state */
IPR(SCI9, RXI9) = 15; /* Set interrupt priority */
IPR(SCI9, TXI9) = 15; /* Set interrupt priority */
MSTP(SCI9) = 0u; /* Cancel SCI9 module stop state */
IPR(SCI9, RXI9) = 15; /* Set interrupt priority */
IPR(SCI9, TXI9) = 15; /* Set interrupt priority */
SCI9.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@ -2003,7 +1717,7 @@ void r_sci9_stop(void)
SCI9.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI9.SCR.BIT.RE = 0u; /* Disable serial receive */
SCI9.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
SCI9.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
SCI9.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI9, TXI9) = 0u;
IR(SCI9, TXI9) = 0u;
IEN(SCI9, RXI9) = 0u;
@ -2071,8 +1785,8 @@ void r_sci10_create(void)
{
rx_mpc_enable();
MSTP(SCI10) = 0u; /* Cancel SCI10 module stop state */
IPR(SCI10, RXI10) = 15; /* Set interrupt priority */
IPR(SCI10, TXI10) = 15; /* Set interrupt priority */
IPR(SCI10, RXI10) = 15; /* Set interrupt priority */
IPR(SCI10, TXI10) = 15; /* Set interrupt priority */
SCI10.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@ -2201,9 +1915,9 @@ void r_sci11_create(void)
{
rx_mpc_enable();
MSTP(SCI11) = 0u; /* Cancel SCI11 module stop state */
IPR(SCI11, RXI11) = 15; /* Set interrupt priority */
IPR(SCI11, TXI11) = 15; /* Set interrupt priority */
SCI11.SCR.BYTE = 0u; /* Clear the control register */
IPR(SCI11, RXI11) = 15; /* Set interrupt priority */
IPR(SCI11, TXI11) = 15; /* Set interrupt priority */
SCI11.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@ -2330,8 +2044,8 @@ void r_sci12_create(void)
{
rx_mpc_enable();
MSTP(SCI12) = 0u; /* Cancel SCI12 module stop state */
IPR(SCI12, RXI12) = 15; /* Set interrupt priority */
IPR(SCI12, TXI12) = 15; /* Set interrupt priority */
IPR(SCI12, RXI12) = 15; /* Set interrupt priority */
IPR(SCI12, TXI12) = 15; /* Set interrupt priority */
SCI12.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */

43
arch/renesas/src/rx65n/rx65n_sci.h
View File

@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_sci.h
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_SCI_H
#define __ARCH_RENESAS_SRC_RX65N_SCI_H
@ -769,7 +754,7 @@
/****************************************************************************
* Public Function Prototypes
***************************************************************************/
****************************************************************************/
/****************************************************************************
* Name: r_sci0_create

25
arch/renesas/src/rx65n/rx65n_serial.c
View File

@ -28,6 +28,7 @@
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <semaphore.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
@ -255,19 +256,19 @@
struct up_dev_s
{
uint32_t scibase; /* Base address of SCI registers */
uint32_t baud; /* Configured baud */
volatile uint8_t scr; /* Saved SCR value */
volatile uint8_t ssr; /* Saved SR value */
uint8_t xmitirq; /* Base IRQ associated with xmit IRQ */
uint8_t recvirq; /* Base IRQ associated with receive IRQ */
uint32_t scibase; /* Base address of SCI registers */
uint32_t baud; /* Configured baud */
volatile uint8_t scr; /* Saved SCR value */
volatile uint8_t ssr; /* Saved SR value */
uint8_t xmitirq; /* Base IRQ associated with xmit IRQ */
uint8_t recvirq; /* Base IRQ associated with receive IRQ */
uint8_t eriirq;
uint8_t teiirq;
uint32_t grpibase;
uint32_t erimask;
uint32_t teimask;
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
};
@ -1198,7 +1199,9 @@ static int up_eriinterrupt(int irq, void *context, void *arg)
priv->ssr = up_serialin(priv, RX_SCI_SSR_OFFSET);
/* Clear all read related events (probably already done in up_receive)) */
/* Clear all read related events (probably already done in
* up_receive))
*/
priv->ssr &= ~(RX_SCISSR_ORER | RX_SCISSR_FER | RX_SCISSR_PER);
up_serialout(priv, RX_SCI_SSR_OFFSET, priv->ssr);
@ -1223,7 +1226,9 @@ static int up_teiinterrupt(int irq, void *context, void *arg)
priv->ssr = up_serialin(priv, RX_SCI_SSR_OFFSET);
/* Clear all read related events (probably already done in up_receive)) */
/* Clear all read related events (probably already done in
* up_receive))
*/
priv->ssr &= ~(RX_SCISSR_TEND);
up_serialout(priv, RX_SCI_SSR_OFFSET, priv->ssr);

41
arch/renesas/src/rx65n/rx65n_timerisr.c
View File

@ -1,35 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_timerisr.c
*
* Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
* Author: Anjana <anjana@tataelxsi.co.in>
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* http://www.apache.org/licenses/LICENSE-2.0
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
@ -165,6 +150,6 @@ void up_timer_initialize(void)
/* Start the timer */
reg16 = getreg16(RX65N_CMT_CMSTR0_ADDR);
reg16 |= RX65N_CMTCMSTR0_STR0; /* Enable TCNT0 */
reg16 |= RX65N_CMTCMSTR0_STR0; /* Enable TCNT0 */
putreg16(reg16, RX65N_CMT_CMSTR0_ADDR); /* TCNT0 is counting */
}

2
arch/renesas/src/rx65n/rx65n_vector_table.c
View File

@ -210,7 +210,7 @@ const void *except_vectors[] EXVECT_SECT =
r_reserved_exception, /* 0xffffffd8 Reserved */
r_undefined_exception, /* 0xffffffdc Exception */
r_reserved_exception, /* 0xffffffe0 Reserved */
r_floatingpoint_exception, /* 0xffffffe4 Exception */
r_floatingpoint_exception, /* 0xffffffe4 Exception */
r_undefined_exception, /* 0xffffffe8 Reserved */
r_undefined_exception, /* 0xffffffec Reserved */
r_undefined_exception, /* 0xfffffff0 Reserved */

27
boards/renesas/rx65n/rx65n-grrose/README.txt
View File

@ -11,7 +11,32 @@ Contents
- Serial Console
- LEDs
- Networking
- IPv6 Integration
- HTTP Server Integration on IPv4
- DHCP Client Integration on IPv4
- DHCP Server Integration on IPv4
- FTP Server Integration on IPv4
- FTP Client Integration on IPv4
- TFTP Client Integration on IPv4
- Telnet Server Integration on IPv4
- Telnet Client Integration on IPv4
- Ustream Socket Integration on IPv4
- Udgram Socket Integration on IPv4
- SMTP Client Integration on IPv4
- Raw Socket Integration
- Custom User Socket Integration
- IGMPv2 Integration
- Inherit telnet server Integration
- VNC Server Integration
- PPPD Integration
- HTTP Client Integration
- NTP Client Integration
- NFS Client Integration
- MLD Integration
- ICMPv6 AutoConfig Integration
- IP Forwarding Integration for IPv4
- DNS Name Resolution Integration for IPv4
- LINK MONITOR Integration
- RTC
- Debugging

126
boards/renesas/rx65n/rx65n-grrose/configs/ipv6/defconfig Normal file
View File

@ -0,0 +1,126 @@
CONFIG_ARCH_BOARD_RX65N_GRROSE=y
CONFIG_ARCH_BOARD="rx65n-grrose"
CONFIG_ARCH_CHIP_R5F565NEHDFP=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="renesas"
CONFIG_ARCH_CHIP="rx65n"
CONFIG_BOARD_LOOPSPERMSEC=15001
CONFIG_MOTOROLA_SREC=y
CONFIG_ENDIAN_LITTLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_MAX_TASKS=8
CONFIG_DEBUG_FEATURES=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_BUILTIN=y
CONFIG_ETH0_PHY_LAN8720A=y
CONFIG_NET=y
#CONFIG_NETDB_DNSCLIENT=y
#CONFIG_NETDB_DNSSERVER_NOADDR=y
CONFIG_NETDEV_PHY_IOCTL=y
CONFIG_NETDEV_STATISTICS=y
#CONFIG_NETUTILS_TFTPC=y
#CONFIG_NETUTILS_WEBCLIENT=y
#CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
#CONFIG_NET_ICMP=y
#CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NETINIT_MONITOR=y
CONFIG_NETINIT_THREAD=y
CONFIG_NETINIT_RETRYMSEC=2000
CONFIG_NETINIT_SIGNO=18
CONFIG_NUNGET_CHARS=0
CONFIG_PREALLOC_TIMERS=0
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=655360
CONFIG_RAM_START=0x00000000
CONFIG_RAW_BINARY=y
CONFIG_RX65N_SCI0=y
CONFIG_RX65N_SCI1=y
CONFIG_RX65N_SCI2=y
CONFIG_RX65N_SCI5=y
CONFIG_RX65N_SCI6=y
CONFIG_RX65N_SCI8=y
CONFIG_SCI0_SERIALDRIVER=y
CONFIG_SCI0_BAUD=115200
CONFIG_SCI1_SERIAL_CONSOLE=y
CONFIG_SCI1_SERIALDRIVER=y
CONFIG_SCI1_BAUD=115200
CONFIG_SCI2_SERIALDRIVER=y
CONFIG_SCI2_BAUD=115200
CONFIG_SCI5_SERIALDRIVER=y
CONFIG_SCI5_BAUD=921600
CONFIG_SCI6_SERIALDRIVER=y
CONFIG_SCI6_BAUD=115200
CONFIG_SCI8_SERIALDRIVER=y
CONFIG_SCI8_BAUD=115200
CONFIG_RX65N_EMAC=y
CONFIG_RX65N_EMAC0=y
CONFIG_RX65N_EMAC0_PHYSR=30
CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18
CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08
CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14
CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04
CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y
CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c
CONFIG_RX65N_EMAC0_RMII=y
CONFIG_RX65N_EMAC0_PHYADDR=0
CONFIG_SCHED_WORKQUEUE=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_LPWORK=y
CONFIG_SDCLONE_DISABLE=y
#CONFIG_SYSTEM_PING=y
CONFIG_ICU=y
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=1024
CONFIG_IDLETHREAD_STACKSIZE=1024
CONFIG_FS_PROCFS=y
CONFIG_FS_PROCFS_REGISTER=y
CONFIG_NET_ETH_PKTSIZE = 590
CONFIG_RX65N_CMTW0=y
CONFIG_RX65N_PERIB=y
CONFIG_NETUTILS_DHCPC=y
CONFIG_NETUTILS_DHCPD=y
CONFIG_NSH_DHCPC=y
CONFIG_NETINIT_DHCPC=y
CONFIG_SYSTEM_DHCPC_RENEW=y
CONFIG_SYSTEM_NSH_PRIORITY=50
CONFIG_EXAMPLES_SERIALBLASTER=y
CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048
CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50
CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2"
CONFIG_EXAMPLES_SERIALRX=y
CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
CONFIG_EXAMPLES_SERIALRX_PRIORITY=75
CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520
CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0"
CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
CONFIG_DEBUG_NET=y
# CONFIG_NET_IPv4 is not set
CONFIG_NETINIT_IPv6NETMASK_8=0xff80
CONFIG_NET_ICMPv6=y
CONFIG_NET_ICMPv6_NEIGHBOR=y
CONFIG_NET_ICMPv6_SOCKET=y
CONFIG_NET_IPv6=y
CONFIG_SYSTEM_PING6=y
CONFIG_NET_MLD=y
#CONFIG_NET_MCASTGROUP=y
CONFIG_NET_SOLINGER=y

12
boards/renesas/rx65n/rx65n-grrose/include/board.h
View File

@ -56,7 +56,17 @@
/* LED definitions */
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
# define LED_ON (0)
# define LED_OFF (1)
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
# define LED_ON (1)
# define LED_OFF (0)
#else
# error "No Selection for PORT definition in rx65n_port.c"
#endif
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \

232
boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h Normal file
View File

@ -0,0 +1,232 @@
/****************************************************************************
* boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_RENESAS_RX65N_RX65N_GRROSE_INCLUDE_RX65N_GPIO_H
#define __BOARDS_RENESAS_RX65N_RX65N_GRROSE_INCLUDE_RX65N_GPIO_H
#if defined(CONFIG_ARCH_RX65N_GRROSE)
#define PHY_STS_REG 0x1f
#define PHY_STS_REG_AUTO_NEG (1 << 12)
#define PHY_STS_READ_REG PHY_REG_STATUS
#define PHY_STS_BIT_MASK (0x4)
#define PHY_STS_SHIFT_COUNT (0x02)
#else
#define PHY_STS_REG 0x10
#define PHY_STS_REG_LINK (1 << 0)
#define PHY_STS_READ_REG PHY_STS_REG
#define PHY_STS_BIT_MASK (0x1)
#define PHY_STS_SHIFT_COUNT (0x0)
#endif
#if defined(CONFIG_ARCH_RX65N_GRROSE)
#define PHY_SET_MODE_REG PHY_RMII_SET_MODE
#else
#define PHY_SET_MODE_REG PHY_MII_SET_MODE
#endif
#if defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
#define RX65N_MAC_ADDRL 0x00509074
#define RX65N_MAC_ADDRH 0x0000989c
#else
#define RX65N_MAC_ADDRL 0x00000000
#define RX65N_MAC_ADDRH 0x00000000
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sci_port_create
*
* Description:
* Initializes SCI Ports of RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void sci_port_create(void);
/****************************************************************************
* Name: led_port_create
*
* Description:
* Initializes LED Ports of RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void led_port_create(void);
/****************************************************************************
* Name: r_ether_pheriperal_enable
*
* Description:
* Ethernet Peripheral enabling
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_EMAC0
void r_ether_pheriperal_enable(void);
#endif
/****************************************************************************
* Name: sci0_init_port
*
* Description:
* SCI0 Initialization RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI0
void sci0_init_port(void);
#endif
/****************************************************************************
* Name: sci1_init_port
*
* Description:
* SCI1 Initialization RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI1
void sci1_init_port(void);
#endif
/****************************************************************************
* Name: sci2_init_port
*
* Description:
* SCI2 Initialization RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI2
void sci2_init_port(void);
#endif
/****************************************************************************
* Name: sci3_init_port
*
* Description:
* SCI3 Initialization RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI3
void sci3_init_port(void);
#endif
/****************************************************************************
* Name: sci5_init_port
*
* Description:
* SCI5 Initialization RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI5
void sci5_init_port(void);
#endif
/****************************************************************************
* Name: sci6_init_port
*
* Description:
* SCI6 Initialization RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI6
void sci6_init_port(void);
#endif
/****************************************************************************
* Name: sci8_init_port
*
* Description:
* SCI8 Initialization RX65N GRROSE
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI8
void sci8_init_port(void);
#endif
#endif /* __BOARDS_RENESAS_RX65N_RX65N_GRROSE_INCLUDE_RX65N_GPIO_H */

2
boards/renesas/rx65n/rx65n-grrose/src/Makefile
View File

@ -26,7 +26,7 @@ CFLAGS += -I=$(ARCH_SRCDIR)/chip
ASRCS =
AOBJS = $(ASRCS:.asm=$(OBJEXT))
CSRCS = rx65n_appinit.c rx65n_bringup.c rx65n_sbram.c
CSRCS = rx65n_appinit.c rx65n_bringup.c rx65n_sbram.c rx65n_gpio.c
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)

358
boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c Normal file
View File

@ -0,0 +1,358 @@
/****************************************************************************
* boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "rx65n_macrodriver.h"
#include "rx65n_port.h"
#include "arch/board/board.h"
#include "arch/board/rx65n_gpio.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: led_port_create
*
* Description:
* LED Port Initialization for RX65N GRROSE Board
****************************************************************************/
#if defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
void led_port_create(void)
{
/* LED Port initialization of RX65N GRROSE */
LED_PORTINIT(0);
}
/****************************************************************************
* Name: sci_port_create
*
* Description:
* SCI Port Initialization for RX65N GRROSE Board
****************************************************************************/
void sci_port_create(void)
{
/* SCI Port initialization for RX65N-GRROSE */
/* SCI0(UART) direction */
PORT2.PODR.BIT.B2 = 0; PORT2.PMR.BIT.B2 = 0; PORT2.PDR.BIT.B2 = 1;
/* SCI2(UART) direction */
PORT1.PODR.BIT.B4 = 0; PORT1.PMR.BIT.B4 = 0; PORT1.PDR.BIT.B4 = 1;
/* SCI5(UART) direction */
PORTC.PODR.BIT.B4 = 0; PORTC.PMR.BIT.B4 = 0; PORTC.PDR.BIT.B4 = 1;
/* SCI6(UART) direction */
PORT3.PODR.BIT.B4 = 0; PORT3.PMR.BIT.B4 = 0; PORT3.PDR.BIT.B4 = 1;
/* SCI8(RS485) direction */
PORTC.PODR.BIT.B5 = 0; PORTC.PMR.BIT.B5 = 0; PORTC.PDR.BIT.B5 = 1;
}
/****************************************************************************
* Name: r_ether_pheriperal_enable
*
* Description:
* Ethernet Pheriperal enabling
****************************************************************************/
#ifdef CONFIG_RX65N_EMAC0
void r_ether_pheriperal_enable(void)
{
/* Set ET0_MDC(PA4_ET_MDC) pin */
MPC.PA4PFS.BYTE = 0x11u;
PORTA.PMR.BIT.B4 = 1u;
/* Set ET0_MDIO(PA3_ET_MDIO) pin */
MPC.PA3PFS.BYTE = 0x11u;
PORTA.PMR.BIT.B3 = 1u;
/* Set REF50CK0 (PB2_ET_CLK) pin */
MPC.PB2PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B2 = 1u;
/* Set RMII0_CRS_DV(PB7_ET_CRS) pin */
MPC.PB7PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B7 = 1u;
/* Set RMII0_RXD0(PB1_ET_RXD0) pin */
MPC.PB1PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B1 = 1u;
/* Set RMII0_RXD1(PB0_ET_RXD1) pin */
MPC.PB0PFS.BYTE = 0x12u;
PORTB.PMR.BIT.BT0 = 1u;
/* Set RMII0_RX_ER(PB3_ET_RXER) pin */
MPC.PB3PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B3 = 1u;
/* Set RMII0_ETXD0(PB5_ET_TXD0) pin */
MPC.PB5PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B5 = 1u;
/* Set RMII0_ETXD1(PB6_ET_TXD1) pin */
MPC.PB6PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B6 = 1u;
/* Set RMII0_TXD_EN(PB4_ET_TXEN) pin */
MPC.PB4PFS.BYTE = 0x12u;
PORTB.PMR.BIT.B4 = 1u;
/* Set RXD2 pin */
MPC.P52PFS.BYTE = 0x0au;
PORT5.PMR.BIT.B2 = 1u;
/* Set TXD2 pin */
PORT5.PODR.BYTE |= 0x01u;
MPC.P50PFS.BYTE = 0x0au;
PORT5.PDR.BYTE |= 0x01u;
/* Set ET0_LINKSTA(PA5_ET_LINK) pin */
MPC.PA5PFS.BYTE = 0x11u;
PORTA.PMR.BIT.B5 = 1u;
/* Set ETHER reset(PA6_ET_RST) pin */
MPC.PA6PFS.BYTE = 0x12u;
PORTA.PMR.BIT.B6 = 1u;
/* Set VBUS pin for USB */
/* Referred from r_usb_basic_pinset.c */
MPC.P16PFS.BYTE = 0x12u;
/* PORT1.PMR.BYTE |= 0x40; */
PORT1.PMR.BIT.B6 = 1u;
/* Set USB0_OVRCURA pin */
/* GR Rose does not contain any of OVRCURA/B inputs
* MPC.P14PFS.BYTE = 0x12u;
* PORT1.PMR.BIT.B4 = 1u;
*/
}
#endif
/****************************************************************************
* Name: sci0_init_port
*
* Description:
* SCI0 Initialization RX65N GRROSE
****************************************************************************/
#ifdef CONFIG_RX65N_SCI0
inline void sci0_init_port(void)
{
/* Set RXD0 pin (P21) */
MPC.P21PFS.BYTE = 0x0au;
PORT2.PMR.BIT.B1 = 1u;
/* Set TXD0 pin (P20) */
PORT2.PODR.BIT.BT0 = 1u;
MPC.P20PFS.BYTE = 0x0au;
PORT2.PDR.BIT.BT0 = 1u;
PORT2.PMR.BIT.BT0 = 1u;
}
#endif
/****************************************************************************
* Name: sci1_init_port
*
* Description:
* SCI1 Initialization RX65N GRROSE
****************************************************************************/
#ifdef CONFIG_RX65N_SCI1
inline void sci1_init_port(void)
{
/* Set RXD1 pin (P30) */
MPC.P30PFS.BYTE = 0x0au;
PORT3.PMR.BIT.BT0 = 1u;
/* Set TXD1 pin (P26) */
PORT2.PODR.BIT.B6 = 1u;
MPC.P26PFS.BYTE = 0x0au;
PORT2.PDR.BIT.B6 = 1u;
PORT2.PMR.BIT.B6 = 1u;
}
#endif
/****************************************************************************
* Name: sci2_init_port
*
* Description:
* SCI2 Initialization RX65N GRROSE
****************************************************************************/
#ifdef CONFIG_RX65N_SCI2
inline void sci2_init_port(void)
{
/* Set RXD2 pin (P12) */
MPC.P12PFS.BYTE = 0x0au;
PORT1.PMR.BIT.B2 = 1u;
/* Set TXD2 pin (P13) */
PORT1.PODR.BIT.B3 = 1u;
MPC.P13PFS.BYTE = 0x0au;
PORT1.PDR.BIT.B3 = 1u;
PORT1.PMR.BIT.B3 = 1u;
}
#endif
/****************************************************************************
* Name: sci3_init_port
*
* Description:
* SCI3 Initialization RX65N GRROSE
****************************************************************************/
#ifdef CONFIG_RX65N_SCI3
inline void sci3_init_port(void)
{
/* Set RXD3 pin (PXX)
* MPC.PXXPFS.BYTE = 0x0au;
* PORTX.PMR.BIT.BX = 1u;
* Set TXD3 pin (PXX)
* PORTX.PODR.BIT.BX = 1u;
* MPC.PXXPFS.BYTE = 0x0au;
* PORTX.PDR.BIT.BX = 1u;
* PORTX.PMR.BIT.BX = 1u;
*/
/* Set RXD2 pin (P25) */
MPC.P25PFS.BYTE = 0x0au;
PORT2.PMR.BIT.B5 = 1u;
/* Set TXD2 pin (P23) */
PORT2.PODR.BIT.B3 = 1u;
MPC.P23PFS.BYTE = 0x0au;
PORT2.PDR.BIT.B3 = 1u;
PORT2.PMR.BIT.B3 = 1u;
}
#endif
/****************************************************************************
* Name: sci5_init_port
*
* Description:
* SCI5 Initialization RX65N GRROSE
****************************************************************************/
#ifdef CONFIG_RX65N_SCI5
inline void sci5_init_port(void)
{
/* Set RXD3 pin (PC2) */
MPC.PC2PFS.BYTE = 0x0au;
PORTC.PMR.BIT.B2 = 1u;
/* Set TXD3 pin (PC3) */
PORTC.PODR.BIT.B3 = 1u;
MPC.PC3PFS.BYTE = 0x0au;
PORTC.PDR.BIT.B3 = 1u;
PORTC.PMR.BIT.B3 = 1u;
}
#endif
/****************************************************************************
* Name: sci6_init_port
*
* Description:
* SCI6 Initialization RX65N GRROSE
****************************************************************************/
#ifdef CONFIG_RX65N_SCI6
inline void sci6_init_port(void)
{
/* Set RXD6 pin (P33) */
MPC.P33PFS.BYTE = 0x0au;
PORT3.PMR.BIT.B3 = 1u;
/* Set TXD6 pin (P32) */
PORT3.PODR.BIT.B2 = 1u;
MPC.P32PFS.BYTE = 0x0au;
PORT3.PDR.BIT.B2 = 1u;
PORT3.PMR.BIT.B2 = 1u;
}
#endif
/****************************************************************************
* Name: sci8_init_port
*
* Description:
* SCI8 Initialization RX65N GRROSE
****************************************************************************/
#ifdef CONFIG_RX65N_SCI8
inline void sci8_init_port(void)
{
/* Set RXD8 pin (PC6) */
MPC.PC6PFS.BYTE = 0x0au;
PORTC.PMR.BIT.B6 = 1u;
/* Set TXD8 pin (PC7) */
PORTC.PODR.BIT.B7 = 1u;
MPC.PC7PFS.BYTE = 0x0au;
PORTC.PDR.BIT.B7 = 1u;
PORTC.PMR.BIT.B7 = 1u;
}
#endif
#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */

97
boards/renesas/rx65n/rx65n-rsk1mb/include/rx65n_gpio.h Normal file
View File

@ -0,0 +1,97 @@
/****************************************************************************
* boards/renesas/rx65n/rx65n-rsk1mb/include/rx65n_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_RENESAS_RX65N_RX65N_RSK1MB_INCLUDE_RX65N_GPIO_H
#define __BOARDS_RENESAS_RX65N_RX65N_RSK1MB_INCLUDE_RX65N_GPIO_H
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sci_port_create
*
* Description:
* Initializes SCI Ports of RX65N RSK1MB
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void sci_port_create(void);
/****************************************************************************
* Name: led_port_create
*
* Description:
* Initializes LED Ports of RX65N RSK1MB
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void led_port_create(void);
/****************************************************************************
* Name: r_ether_pheriperal_enable
*
* Description:
* Ethernet Peripheral enabling
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_EMAC0
void r_ether_pheriperal_enable(void);
#endif
/****************************************************************************
* Name: sci2_init_port
*
* Description:
* SCI2 Initialization RX65N RSK1MB
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI2
void sci2_init_port(void);
#endif
#endif /* __BOARDS_RENESAS_RX65N_RX65N_RSK1MB_INCLUDE_RX65N_GPIO_H */

127
boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_gpio.c Normal file
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@ -0,0 +1,127 @@
/****************************************************************************
* boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "rx65n_macrodriver.h"
#include "rx65n_port.h"
#include "arch/board/board.h"
#include "arch/board/rx65n_gpio.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: led_port_create
*
* Description:
* Port Initialization for RX65N RSK1MB Board
****************************************************************************/
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
void led_port_create(void)
{
/* LED Port initialization of RX65N RSK1MB */
/* LED_PORTINIT(0); */
PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
PORT0.PMR.BYTE = 0x00u;
PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
_20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
}
/****************************************************************************
* Name: sci_port_create
*
* Description:
* SCI Port Initialization for RX65N RSK2MB Board
****************************************************************************/
void sci_port_create(void)
{
/* SCI Port initialization for RX65N-RSK1MB */
PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
PORT5.PMR.BYTE = 0x00u;
PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
_80_PDR5_DEFAULT;
/* General Purpose I/O Port initialization for RX65N-RSK1MB */
PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT7.PMR.BYTE = 0x00u;
PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
PORT9.PMR.BYTE = 0x00u;
PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
PORTJ.PMR.BYTE = 0x00u;
PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
}
/****************************************************************************
* Name: r_ether_pheriperal_enable
*
* Description:
* Ethernet Peripheral enabling
****************************************************************************/
#ifdef CONFIG_RX65N_EMAC0
void r_ether_pheriperal_enable(void)
{
/* TODO */
}
#endif
/****************************************************************************
* Name: sci2_init_port
*
* Description:
* SCI2 Initialization RX65N RSK1MB
****************************************************************************/
#ifdef CONFIG_RX65N_SCI2
inline void sci2_init_port(void)
{
/* Set RXD2 pin (P52) */
MPC.P52PFS.BYTE = 0x0au;
PORT5.PMR.BIT.B2 = 1u;
/* Set TXD2 pin (P50) */
PORT5.PODR.BIT.BT0 = 1u;
MPC.P50PFS.BYTE = 0x0au;
PORT5.PDR.BIT.BT0 = 1u;
PORT5.PMR.BIT.BT0 = 1u;
}
#endif
#endif /* CONFIG_ARCH_BOARD_RX65N_RSK1MB*/

26
boards/renesas/rx65n/rx65n-rsk2mb/README.txt
View File

@ -11,6 +11,32 @@ Contents
- Serial Console
- LEDs
- Networking
- IPv6 Integration
- HTTP Server Integration on IPv4
- DHCP Client Integration on IPv4
- DHCP Server Integration on IPv4
- FTP Server Integration on IPv4
- FTP Client Integration on IPv4
- TFTP Client Integration on IPv4
- Telnet Server Integration on IPv4
- Telnet Client Integration on IPv4
- Ustream Socket Integration on IPv4
- Udgram Socket Integration on IPv4
- SMTP Client Integration on IPv4
- Raw Socket Integration
- Custom User Socket Integration
- IGMPv2 Integration
- Inherit telnet server Integration
- VNC Server Integration
- PPPD Integration
- HTTP Client Integration
- NTP Client Integration
- NFS Client Integration
- MLD Integration
- ICMPv6 AutoConfig Integration
- IP Forwarding Integration for IPv4
- DNS Name Resolution Integration for IPv4
- LINK MONITOR Integration
- RTC
- Debugging

110
boards/renesas/rx65n/rx65n-rsk2mb/configs/ipv6/defconfig Normal file
View File

@ -0,0 +1,110 @@
CONFIG_ARCH_BOARD_RX65N_RSK2MB=y
CONFIG_ARCH_BOARD="rx65n"
CONFIG_ARCH_CHIP_R5F565NEHDFC=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="renesas"
CONFIG_ARCH_CHIP="rx65n"
CONFIG_BOARD_LOOPSPERMSEC=15001
CONFIG_MOTOROLA_SREC=y
CONFIG_ENDIAN_LITTLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_MAX_TASKS=8
CONFIG_DEBUG_FEATURES=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_BUILTIN=y
CONFIG_ETH0_PHY_DP83620=y
CONFIG_NET=y
#CONFIG_NETDB_DNSCLIENT=y
#CONFIG_NETDB_DNSSERVER_NOADDR=y
CONFIG_NETDEV_PHY_IOCTL=y
CONFIG_NETDEV_STATISTICS=y
#CONFIG_NETUTILS_TFTPC=y
#CONFIG_NETUTILS_WEBCLIENT=y
#CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
#CONFIG_NET_ICMP=y
#CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NETINIT_MONITOR=y
CONFIG_NETINIT_THREAD=y
CONFIG_NETINIT_RETRYMSEC=2000
CONFIG_NETINIT_SIGNO=18
CONFIG_NUNGET_CHARS=0
CONFIG_PREALLOC_TIMERS=0
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=262144
CONFIG_RAM_START=0x00000000
CONFIG_RAW_BINARY=y
CONFIG_SCI2_SERIALDRIVER=y
CONFIG_RX65N_SCI2=y
CONFIG_SCI8_SERIALDRIVER=y
CONFIG_SCI8_SERIAL_CONSOLE=y
CONFIG_RX65N_SCI8=y
CONFIG_RX65N_EMAC=y
CONFIG_RX65N_EMAC0=y
CONFIG_RX65N_EMAC0_PHYSR=30
CONFIG_RX65N_EMAC0_PHYSR_100FD=0x4
CONFIG_RX65N_EMAC0_PHYSR_100HD=0x0
CONFIG_RX65N_EMAC0_PHYSR_10FD=0x6
CONFIG_RX65N_EMAC0_PHYSR_10HD=0x2
CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y
CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x6
CONFIG_RX65N_EMAC0_MII=y
CONFIG_RX65N_EMAC0_PHYADDR=30
CONFIG_SCHED_WORKQUEUE=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_LPWORK=y
CONFIG_SDCLONE_DISABLE=y
#CONFIG_SYSTEM_PING=y
CONFIG_ICU=y
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=1024
CONFIG_FS_PROCFS=y
CONFIG_FS_PROCFS_REGISTER=y
CONFIG_NET_ETH_PKTSIZE = 590
CONFIG_RX65N_CMTW0=y
CONFIG_RX65N_PERIB=y
CONFIG_NETUTILS_DHCPC=y
CONFIG_NETUTILS_DHCPD=y
CONFIG_NSH_DHCPC=y
CONFIG_NETINIT_DHCPC=y
CONFIG_SYSTEM_NSH_PRIORITY=50
CONFIG_EXAMPLES_SERIALBLASTER=y
CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048
CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50
CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2"
CONFIG_EXAMPLES_SERIALRX=y
CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
CONFIG_EXAMPLES_SERIALRX_PRIORITY=75
CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520
CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0"
CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
CONFIG_DEBUG_NET=y
# CONFIG_NET_IPv4 is not set
CONFIG_NETINIT_IPv6NETMASK_8=0xff80
CONFIG_NET_ICMPv6=y
CONFIG_NET_ICMPv6_NEIGHBOR=y
CONFIG_NET_ICMPv6_SOCKET=y
CONFIG_NET_IPv6=y
CONFIG_SYSTEM_PING6=y
CONFIG_NET_MLD=y
#CONFIG_NET_MCASTGROUP=y
CONFIG_NET_SOLINGER=y

12
boards/renesas/rx65n/rx65n-rsk2mb/include/board.h
View File

@ -56,7 +56,17 @@
/* LED definitions */
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
# define LED_ON (0)
# define LED_OFF (1)
#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
# define LED_ON (1)
# define LED_OFF (0)
#else
# error "No Selection for PORT definition in rx65n_port.c"
#endif
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \

177
boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h Normal file
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@ -0,0 +1,177 @@
/****************************************************************************
* boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_RENESAS_RX65N_RX65N_RSK2MB_INCLUDE_RX65N_GPIO_H
#define __BOARDS_RENESAS_RX65N_RX65N_RSK2MB_INCLUDE_RX65N_GPIO_H
#if defined(CONFIG_ARCH_RX65N_RSK2MB)
#define PHY_STS_REG 0x10
#define PHY_STS_REG_LINK (1 << 0)
#define PHY_STS_READ_REG PHY_STS_REG
#define PHY_STS_BIT_MASK (0x1)
#define PHY_STS_SHIFT_COUNT (0x0)
#else
#define PHY_STS_REG 0x1f
#define PHY_STS_REG_AUTO_NEG (1 << 12)
#define PHY_STS_READ_REG PHY_REG_STATUS
#define PHY_STS_BIT_MASK (0x4)
#define PHY_STS_SHIFT_COUNT (0x02)
#endif
#if defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#define PHY_SET_MODE_REG PHY_MII_SET_MODE
#else
#define PHY_SET_MODE_REG PHY_RMII_SET_MODE
#endif
#if defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#define RX65N_MAC_ADDRL 0x00509074
#define RX65N_MAC_ADDRH 0x0000949c
#else
#define RX65N_MAC_ADDRL 0x00000000
#define RX65N_MAC_ADDRH 0x00000000
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sci_port_create
*
* Description:
* Initializes SCI Ports of RX65N RSK2MB
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void sci_port_create(void);
/****************************************************************************
* Name: led_port_create
*
* Description:
* Initializes LED Ports of RX65N RSK2MB
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void led_port_create(void);
/****************************************************************************
* Name: r_ether_pheriperal_enable
*
* Description:
* Ethernet Pheriperal enabling
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_EMAC0
void r_ether_pheriperal_enable(void);
#endif
/****************************************************************************
* Name: sci1_init_port
*
* Description:
* SCI1 Initialization RX65N RSK2MB
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI1
void sci1_init_port(void);
#endif
/****************************************************************************
* Name: sci2_init_port
*
* Description:
* SCI2 Initialization RX65N RSK2MB
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI2
void sci2_init_port(void);
#endif
/****************************************************************************
* Name: sci8_init_port
*
* Description:
* SCI8 Initialization RX65N RSK2MB
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI8
void sci8_init_port(void);
#endif
/****************************************************************************
* Name: sci12_init_port
*
* Description:
* SCI12 Initialization RX65N RSK2MB
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RX65N_SCI12
void sci12_init_port(void);
#endif
#endif /* __BOARDS_RENESAS_RX65N_RX65N_RSK2MB_INCLUDE_RX65N_GPIO_H */

2
boards/renesas/rx65n/rx65n-rsk2mb/src/Makefile
View File

@ -26,7 +26,7 @@ CFLAGS += -I=$(ARCH_SRCDIR)/chip
ASRCS =
AOBJS = $(ASRCS:.asm=$(OBJEXT))
CSRCS = rx65n_appinit.c rx65n_bringup.c rx65n_sbram.c
CSRCS = rx65n_appinit.c rx65n_bringup.c rx65n_sbram.c rx65n_gpio.c
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)

321
boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c Normal file
View File

@ -0,0 +1,321 @@
/****************************************************************************
* boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "rx65n_macrodriver.h"
#include "rx65n_port.h"
#include "arch/board/board.h"
#include "arch/board/rx65n_gpio.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: led_port_create
*
* Description:
* LED Port Initialization for RX65N RSK2MB Board
****************************************************************************/
#if defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
void led_port_create(void)
{
/* LED Port initialization of RX65N RSK2MB */
/* LED_PORTINIT(0); */
PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT7.PMR.BYTE = 0x00u;
PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
}
/****************************************************************************
* Name: sci_port_create
*
* Description:
* SCI Port Initialization for RX65N RSK2MB Board
****************************************************************************/
void sci_port_create(void)
{
/* SCI Port initialization for RX65N-RSK2MB */
PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
PORT5.PMR.BYTE = 0x00u;
PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
_80_PDR5_DEFAULT;
PORTJ.PMR.BYTE = 0x00u;
PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
/* General Purpose I/O Port initialization for RX65N-RSK2MB */
PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT0.PMR.BYTE = 0x00u;
PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
_20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
PORT9.PMR.BYTE = 0x00u;
PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
}
/****************************************************************************
* Name: r_ether_pheriperal_enable
*
* Description:
* Ethernet Pheriperal enabling
****************************************************************************/
#ifdef CONFIG_RX65N_EMAC0
void r_ether_pheriperal_enable(void)
{
/* Set ET0_TX_CLK pin */
MPC.PC4PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B4 = 1u;
/* Set ET0_RX_CLK pin */
MPC.P76PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B6 = 1u;
/* Set ET0_TX_EN pin */
MPC.P80PFS.BYTE = 0x11u;
PORT8.PMR.BIT.BT0 = 1u;
/* Set ET0_ETXD3 pin */
MPC.PC6PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B6 = 1u;
/* Set ET0_ETXD2 pin */
MPC.PC5PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B5 = 1u;
/* Set ET0_ETXD1 pin */
MPC.P82PFS.BYTE = 0x11u;
PORT8.PMR.BIT.B2 = 1u;
/* Set ET0_ETXD0 pin */
MPC.P81PFS.BYTE = 0x11u;
PORT8.PMR.BIT.B1 = 1u;
/* Set ET0_TX_ER pin */
MPC.PC3PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B3 = 1u;
/* Set ET0_RX_DV pin */
MPC.PC2PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B2 = 1u;
/* Set ET0_ERXD3 pin */
MPC.PC0PFS.BYTE = 0x11u;
PORTC.PMR.BIT.BT0 = 1u;
/* Set ET0_ERXD2 pin */
MPC.PC1PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B1 = 1u;
/* Set ET0_ERXD1 pin */
MPC.P74PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B4 = 1u;
/* Set ET0_ERXD0 pin */
MPC.P75PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B5 = 1u;
/* Set ET0_RX_ER pin */
MPC.P77PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B7 = 1u;
/* Set ET0_CRS pin */
MPC.P83PFS.BYTE = 0x11u;
PORT8.PMR.BIT.B3 = 1u;
/* Set ET0_COL pin */
MPC.PC7PFS.BYTE = 0x11u;
PORTC.PMR.BIT.B7 = 1u;
/* Set ET0_MDC pin */
MPC.P72PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B2 = 1u;
/* Set ET0_MDIO pin */
MPC.P71PFS.BYTE = 0x11u;
PORT7.PMR.BIT.B1 = 1u;
/* Set ET0_LINKSTA pin */
MPC.P54PFS.BYTE = 0x11u;
PORT5.PMR.BIT.B4 = 1u;
/* Set ET0_LINKSTA pin */
MPC.P34PFS.BYTE = 0x11u;
PORT3.PMR.BIT.B4 = 1u;
/* Set VBUS pin for USB */
/* Referred from r_usb_basic_pinset.c */
MPC.P16PFS.BYTE = 0x12u;
/* PORT1.PMR.BYTE |= 0x40; */
PORT1.PMR.BIT.B6 = 1u;
/* Set USB0_OVRCURA pin */
MPC.P14PFS.BYTE = 0x12u;
PORT1.PMR.BIT.B4 = 1u;
}
#endif
/****************************************************************************
* Name: sci1_init_port
*
* Description:
* SCI1 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_SCI1
inline void sci1_init_port(void)
{
/* Set RXD1 pin (PF2) */
MPC.PF2PFS.BYTE = 0x0au;
PORTF.PMR.BIT.B2 = 1u;
/* Set TXD1 pin (PF1) */
PORTF.PODR.BIT.B1 = 1u;
MPC.PF1PFS.BYTE = 0x0au;
PORTF.PDR.BIT.B1 = 1u;
PORTF.PMR.BIT.B1 = 1u;
}
#endif
/****************************************************************************
* Name: sci2_init_port
*
* Description:
* SCI2 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_SCI2
inline void sci2_init_port(void)
{
/* Set RXD2 pin (P52) */
MPC.P52PFS.BYTE = 0x0au;
PORT5.PMR.BIT.B2 = 1u;
/* Set TXD2 pin (P50) */
PORT5.PODR.BIT.BT0 = 1u;
MPC.P50PFS.BYTE = 0x0au;
PORT5.PDR.BIT.BT0 = 1u;
PORT5.PMR.BIT.BT0 = 1u;
}
#endif
/****************************************************************************
* Name: sci8_init_port
*
* Description:
* SCI8 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_SCI8
inline void sci8_init_port(void)
{
/* Set RXD8 pin (PJ1) */
MPC.PJ1PFS.BYTE = 0x0au;
PORTJ.PMR.BIT.B1 = 1u;
/* Set TXD8 pin (PJ2) */
PORTJ.PODR.BIT.B2 = 1u;
MPC.PJ2PFS.BYTE = 0x0au;
PORTJ.PDR.BIT.B2 = 1u;
PORTJ.PMR.BIT.B2 = 1u;
}
#endif
/****************************************************************************
* Name: sci12_init_port
*
* Description:
* SCI12 Initialization RX65N RSK2MB
****************************************************************************/
#ifdef CONFIG_RX65N_SCI12
inline void sci12_init_port(void)
{
/* Set RXD12 pin */
MPC.PE2PFS.BYTE = 0x0cu;
PORTE.PMR.BYTE |= 0x04u;
/* Set TXD12 pin */
PORTE.PODR.BYTE |= 0x02u;
MPC.PE1PFS.BYTE = 0x0cu;
PORTE.PDR.BYTE |= 0x02u;
/* Set RXD12 pin (PXX)
* MPC.PXXPFS.BYTE = 0x0au;
* PORTX.PMR.BIT.BX = 1u;
* Set TXD12 pin (PXX)
* PORTX.PODR.BIT.BX = 1u;
* MPC.PXXPFS.BYTE = 0x0au;
* PORTX.PDR.BIT.BX = 1u;
* PORTX.PMR.BIT.BX = 1u;
*/
}
#endif
#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */