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arch/arm/src/stm32/chip/stm32_i2c.h: Fix typo in last PR noted by David Sidrane

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This commit is contained in:
Gregory Nutt 2019-05-15 09:34:50 -06:00
parent 8ce1f1a67b
commit 4676470dd7
3 changed files with 7 additions and 5 deletions
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4
arch/arm/src/stm32/chip/stm32_i2c.h
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@ -37,8 +37,8 @@
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H
/* There are 2 main types of I2C IP cores among STM32 chips:
* 1. STM32 ADC IPv1 - F1, F2, F4 and L1
* 2. STM32 ADC IPv2 - G0, L0, F0, F3, F7, H7 and L4
* 1. STM32 I2C IPv1 - F1, F2, F4 and L1
* 2. STM32 I2C IPv2 - G0, L0, F0, F3, F7, H7 and L4
*/
#if defined(CONFIG_STM32_HAVE_IP_I2C_V1)

7
arch/arm/src/stm32/chip/stm32_i2c_v1.h
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@ -71,7 +71,7 @@
# define STM32_I2C1_CCR (STM32_I2C1_BASE+STM32_I2C_CCR_OFFSET)
# define STM32_I2C1_TRISE (STM32_I2C1_BASE+STM32_I2C_TRISE_OFFSET)
# ifdef STM32_I2C_FLTR_OFFSET
# define STM32_I2C1_FLTR (STM32_I2C1_BASE+STM32_I2C_FLTR_OFFSET)
# define STM32_I2C1_FLTR (STM32_I2C1_BASE+STM32_I2C_FLTR_OFFSET)
# endif
#endif
@ -86,7 +86,7 @@
# define STM32_I2C2_CCR (STM32_I2C2_BASE+STM32_I2C_CCR_OFFSET)
# define STM32_I2C2_TRISE (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET)
# ifdef STM32_I2C_FLTR_OFFSET
# define STM32_I2C2_FLTR (STM32_I2C2_BASE+STM32_I2C_FLTR_OFFSET)
# define STM32_I2C2_FLTR (STM32_I2C2_BASE+STM32_I2C_FLTR_OFFSET)
# endif
#endif
@ -101,7 +101,7 @@
# define STM32_I2C3_CCR (STM32_I2C3_BASE+STM32_I2C_CCR_OFFSET)
# define STM32_I2C3_TRISE (STM32_I2C3_BASE+STM32_I2C_TRISE_OFFSET)
# ifdef STM32_I2C_FLTR_OFFSET
# define STM32_I2C3_FLTR (STM32_I2C3_BASE+STM32_I2C_FLTR_OFFSET)
# define STM32_I2C3_FLTR (STM32_I2C3_BASE+STM32_I2C_FLTR_OFFSET)
# endif
#endif
@ -212,3 +212,4 @@
#endif
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_V1_H */

1
arch/arm/src/stm32/chip/stm32_i2c_v2.h
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@ -251,3 +251,4 @@
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_V2_H */