diff --git a/arch/mips/src/pic32mz/pic32mz_ethernet.c b/arch/mips/src/pic32mz/pic32mz_ethernet.c
index b8dd95ec34..e3b2c84c7e 100644
--- a/arch/mips/src/pic32mz/pic32mz_ethernet.c
+++ b/arch/mips/src/pic32mz/pic32mz_ethernet.c
@@ -241,6 +241,11 @@
 #  define PIC32MZ_PHYID1       MII_PHYID1_LAN8720
 #  define PIC32MZ_PHYID2       MII_PHYID2_LAN8720
 #  define PIC32MZ_HAVE_PHY     1
+#elif defined(CONFIG_ETH0_PHY_LAN8740)
+#  define PIC32MZ_PHYNAME      "LAN8740"
+#  define PIC32MZ_PHYID1       MII_PHYID1_LAN8740
+#  define PIC32MZ_PHYID2       MII_PHYID2_LAN8740
+#  define PIC32MZ_HAVE_PHY     1
 #else
 #  warning "No PHY specified!"
 #  undef PIC32MZ_HAVE_PHY
@@ -2952,7 +2957,7 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv)
         ndbg("Unrecognized mode: %04x\n", phyreg);
         return -ENODEV;
     }
-#elif defined(CONFIG_ETH0_PHY_LAN8720)
+#elif defined(CONFIG_ETH0_PHY_LAN8720) || defined(CONFIG_ETH0_PHY_LAN8740)
   {
     uint16_t advertise;
     uint16_t lpa;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 134acc68f3..3745c47f80 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -311,6 +311,9 @@ config ETH0_PHY_DP83848C
 config ETH0_PHY_LAN8720
 	bool "SMSC LAN8720 PHY"
 
+config ETH0_PHY_LAN8740
+	bool "SMSC LAN8740 PHY"
+
 config ETH0_PHY_DM9161
 	bool "Davicom DM9161 PHY"
 
diff --git a/include/nuttx/net/mii.h b/include/nuttx/net/mii.h
index 7dfeb7f240..993f74c837 100644
--- a/include/nuttx/net/mii.h
+++ b/include/nuttx/net/mii.h
@@ -1,7 +1,7 @@
 /****************************************************************************
  * include/nuttx/net/mii.h
  *
- *   Copyright (C) 2008-2010, 2012-2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2008-2010, 2012-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -162,6 +162,20 @@
 #define MII_LAN8720_IMR              0x1e      /* Interrupt Mask Register */
 #define MII_LAN8720_SCSR             0x1f      /* PHY Special Control/Status Register */
 
+/* SMSC LAN8740 PHY Extended Registers */
+
+#define MII_LAN8740_CONFIG           0x10      /* EDPD NDL/Crossover Timer/EEE Configuration */
+#define MII_LAN8740_MCSR             0x11      /* Mode Control/Status Register */
+#define MII_LAN8740_MODES            0x12      /* Special modes */
+#define MII_LAN8740_TDRPAT           0x18      /* TDR Patterns/Delay Control Register */
+#define MII_LAN8740_TDRCTL           0x19      /* TDR Control/Status Register */
+#define MII_LAN8740_SECR             0x1a      /* Symbol Error Counter Register */
+#define MII_LAN8740_CSIR             0x1b      /* Control/Status Indicator Register */
+#define MII_LAN8740_CBLEN            0x1c      /* Cable Length Register */
+#define MII_LAN8740_ISR              0x1d      /* Interrupt Source Register */
+#define MII_LAN8740_IMR              0x1e      /* Interrupt Mask Register */
+#define MII_LAN8740_SCSR             0x1f      /* PHY Special Control/Status Register */
+
 /* MII register bit settings ************************************************/
 
 /* MII Control register bit definitions */
@@ -330,6 +344,11 @@
 #define MII_PHYID1_LAN8720           0x0007    /* ID1 value for LAN8720 */
 #define MII_PHYID2_LAN8720           0xc0f1    /* ID2 value for LAN8720 */
 
+/* SMSC LAN8740 MII ID1/2 register bits */
+
+#define MII_PHYID1_LAN8740           0x0007    /* ID1 value for LAN8740 */
+#define MII_PHYID2_LAN8740           0xc110    /* ID2 value for LAN8740 */
+
 /* Am79c874-specific register bit settings **********************************/
 /* Am79c874 MII ID1/2 register bits */