Adds support for TM4C123G timers; integrates with the TM4C123G Launchpad. From Calvin Maguranis
This commit is contained in:
Gregory Nutt
parent
ee8d792737
commit
46a153aa3e
@ -173,6 +173,9 @@ config ARCH_CHIP_TM4C
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bool
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select ARCH_CORTEXM4
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select ARCH_HAVE_FPU
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select TIVA_HAVE_ADC0
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select TIVA_HAVE_ADC1
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select TIVA_HAVE_GPIOP_IRQS
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select TIVA_HAVE_I2C1
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select TIVA_HAVE_I2C2
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select TIVA_HAVE_I2C3
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@ -185,6 +188,9 @@ config ARCH_CHIP_TM4C
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select TIVA_HAVE_SSI1
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select TIVA_HAVE_SSI2
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select TIVA_HAVE_SSI3
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select TIVA_HAVE_TIMER0
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select TIVA_HAVE_TIMER1
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select TIVA_HAVE_TIMER2
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select TIVA_HAVE_TIMER3
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select TIVA_HAVE_TIMER4
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select TIVA_HAVE_TIMER5
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@ -203,6 +209,18 @@ config TIVA_BOARD_EARLYINIT
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menu "Tiva/Stellaris Peripheral Support"
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config TIVA_ADC
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bool
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default n
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config TIVA_HAVE_ADC0
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bool
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default n
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config TIVA_HAVE_ADC1
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bool
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default n
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config TIVA_I2C
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bool
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default n
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@ -291,6 +309,18 @@ config TIVA_TIMER
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bool
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default n
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config TIVA_HAVE_TIMER0
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bool
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default n
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config TIVA_HAVE_TIMER1
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bool
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default n
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config TIVA_HAVE_TIMER2
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bool
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default n
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config TIVA_HAVE_TIMER3
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bool
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default n
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@ -311,6 +341,17 @@ config TIVA_HAVE_TIMER7
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bool
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default n
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config TIVA_ADC0
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bool "ADC0"
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default n
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select TIVA_ADC
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config TIVA_ADC1
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bool "ADC1"
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default n
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depends on TIVA_HAVE_ADC0
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select TIVA_ADC
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config TIVA_I2C0
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bool "I2C0"
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default n
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@ -441,16 +482,19 @@ config TIVA_SSI3
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config TIVA_TIMER0
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bool "16-/32-bit Timer 0"
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default n
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depends on TIVA_HAVE_TIMER0
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select TIVA_TIMER
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config TIVA_TIMER1
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bool "16-/32-bit Timer 1"
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default n
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depends on TIVA_HAVE_TIMER1
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select TIVA_TIMER
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config TIVA_TIMER2
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bool "16-/32-bit Timer 2"
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default n
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depends on TIVA_HAVE_TIMER2
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select TIVA_TIMER
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config TIVA_TIMER3
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@ -792,7 +836,6 @@ endif # TIVA_TIMER_16BIT
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config TIVA_TIMER_REGDEBUG
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bool "Register level debug"
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default n
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depends on DEBUG
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---help---
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Enables extremely detailed register access debug output.
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@ -1084,3 +1127,4 @@ config TIVA_FLASH_STARTPAGE
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endmenu
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endif
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@ -53,6 +53,7 @@
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#include "chip/tiva_ssi.h" /* SSI modules */
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#include "chip/tiva_ethernet.h" /* Ethernet MAC and PHY */
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#include "chip/tiva_flash.h" /* FLASH */
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#include "chip/tiva_timer.h" /* Timer */
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/************************************************************************************
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* Pre-processor Definitions
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@ -122,31 +122,31 @@ static void tiva_putreg(struct tiva_gptmstate_s *priv, unsigned int offset,
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#ifdef CONFIG_TIVA_TIMER_32BIT
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static int tiva_timer32_interrupt(struct tiva_gptmstate_s *priv);
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#ifdef CONFIG_TIVA_TIMER0
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# ifdef CONFIG_TIVA_TIMER0
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static int tiva_gptm0_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_TIVA_TIMER1
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# endif
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# ifdef CONFIG_TIVA_TIMER1
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static int tiva_gptm1_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_TIVA_TIMER2
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# endif
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# ifdef CONFIG_TIVA_TIMER2
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static int tiva_gptm2_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_TIVA_TIMER3
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# endif
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# ifdef CONFIG_TIVA_TIMER3
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static int tiva_gptm3_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_TIVA_TIMER4
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# endif
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# ifdef CONFIG_TIVA_TIMER4
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static int tiva_gptm4_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_TIVA_TIMER5
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# endif
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# ifdef CONFIG_TIVA_TIMER5
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static int tiva_gptm5_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_TIVA_TIMER6
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# endif
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# ifdef CONFIG_TIVA_TIMER6
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static int tiva_gptm6_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_TIVA_TIMER7
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# endif
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# ifdef CONFIG_TIVA_TIMER7
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static int tiva_gptm7_interrupt(int irq, FAR void *context);
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#endif
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#endif
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#endif /* CONFIG_TIVA_TIMER_32BIT */
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#ifdef CONFIG_TIVA_TIMER_16BIT
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static int tiva_timer16_interrupt(struct tiva_gptmstate_s *priv,
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@ -183,14 +183,14 @@ static int tiva_timer6b_interrupt(int irq, FAR void *context);
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static int tiva_timer7a_interrupt(int irq, FAR void *context);
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static int tiva_timer7b_interrupt(int irq, FAR void *context);
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#endif
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#endif
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#endif /* CONFIG_TIVA_TIMER_16BIT */
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/* Timer initialization and configuration */
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#ifdef CONFIG_TIVA_TIMER32_PERIODIC
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static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
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const struct tiva_timer32config_s *timer);
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#endif
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#endif /* CONFIG_TIVA_TIMER32_PERIODIC */
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#ifdef CONFIG_TIVA_TIMER16_PERIODIC
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static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv,
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const struct tiva_timer16config_s *timer, int tmndx);
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@ -213,7 +213,7 @@ static int tiva_pwm_mode16(struct tiva_gptmstate_s *priv,
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#endif
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#ifdef CONFIG_TIVA_TIMER_32BIT
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static int tiva_timer32_configure(struct tiva_gptmstate_s *priv,
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static int tiva_timer32_configure(struct tiva_gptmstate_s *priv,
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const struct tiva_timer32config_s *timer);
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#endif
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#ifdef CONFIG_TIVA_TIMER_16BIT
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@ -780,7 +780,7 @@ static int tiva_timer7b_interrupt(int irq, FAR void *context)
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* Name: tiva_oneshot_periodic_mode32
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*
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* Description:
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* Configure a 32-bit timer to operate in one-short or periodic mode
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* Configure a 32-bit timer to operate in one-shot or periodic mode
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*
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****************************************************************************/
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@ -863,7 +863,9 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
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/* Setup defaults */
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regval &= (TIMER_TnMR_TnCDIR | TIMER_TnMR_TnWOT | TIMER_TnMR_TnCDIR);
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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regval |= TIMER_TnMR_TnCINTD;
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#endif
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/* Enable snapshot mode?
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*
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@ -897,7 +899,6 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
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tiva_putreg(priv, TIVA_TIMER_TAMR_OFFSET, regval);
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/* Enable and configure ADC trigger outputs */
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if (TIMER_ISADCTIMEOUT(timer) || TIMER_ISADCMATCH(timer))
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{
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/* Enable ADC trigger outputs by setting the TAOTE bit in the
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@ -908,6 +909,7 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
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regval |= TIMER_CTL_TAOTE;
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tiva_putreg(priv, TIVA_TIMER_CTL_OFFSET, regval);
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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/* Enable timeout triggers now (match triggers will be
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* enabled when the first match value is set).
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*/
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@ -916,6 +918,7 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
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{
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tiva_putreg(priv, TIVA_TIMER_ADCEV_OFFSET, TIMER_ADCEV_TATOADCEN);
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}
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#endif /* CONFIG_ARCH_CHIP_TM4C129 */
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}
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/* In addition, if using CCP pins, the TCACT field can be programmed to
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@ -1068,7 +1071,9 @@ static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv,
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/* Setup defaults */
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regval &= (TIMER_TnMR_TnCDIR | TIMER_TnMR_TnWOT | TIMER_TnMR_TnCDIR);
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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regval |= TIMER_TnMR_TnCINTD;
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#endif
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/* Enable snapshot mode?
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*
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@ -1113,6 +1118,7 @@ static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv,
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regval |= tmndx ? TIMER_CTL_TBOTE : TIMER_CTL_TAOTE;
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tiva_putreg(priv, TIVA_TIMER_CTL_OFFSET, regval);
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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/* Enable timeout triggers now (match triggers will be
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* enabled when the first match value is set).
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*/
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@ -1122,6 +1128,7 @@ static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv,
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regval = tmndx ? TIMER_ADCEV_TBTOADCEN : TIMER_ADCEV_TATOADCEN;
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tiva_putreg(priv, TIVA_TIMER_ADCEV_OFFSET, regval);
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}
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#endif /* CONFIG_ARCH_CHIP_TM4C129 */
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}
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/* TODO: Enable and configure uDMA trigger outputs */
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@ -1519,13 +1526,12 @@ static int tiva_pwm_mode16(struct tiva_gptmstate_s *priv,
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#endif
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/****************************************************************************
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* Name: tiva_timer16_configure
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* Name: tiva_timer32_configure
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*
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* Description:
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* Configure the 32-bit timer to operate in the provided mode.
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*
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****************************************************************************/
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#ifdef CONFIG_TIVA_TIMER_32BIT
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static int tiva_timer32_configure(struct tiva_gptmstate_s *priv,
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const struct tiva_timer32config_s *timer)
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@ -1536,7 +1542,7 @@ static int tiva_timer32_configure(struct tiva_gptmstate_s *priv,
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case TIMER32_MODE_ONESHOT: /* 32-bit programmable one-shot timer */
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case TIMER32_MODE_PERIODIC: /* 32-bit programmable periodic timer */
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return tiva_oneshot_periodic_mode32(priv, timer);
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#endif
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#endif /* CONFIG_TIVA_TIMER32_PERIODIC */
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#ifdef CONFIG_TIVA_TIMER32_RTC
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case TIMER32_MODE_RTC: /* 32-bit RTC with external 32.768-KHz
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@ -1761,6 +1767,7 @@ TIMER_HANDLE tiva_gptm_configure(const struct tiva_gptmconfig_s *config)
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if (config->alternate)
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{
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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/* Enable the alternate clock source */
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regval = tiva_getreg(priv, TIVA_TIMER_CC_OFFSET);
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@ -1770,6 +1777,10 @@ TIMER_HANDLE tiva_gptm_configure(const struct tiva_gptmconfig_s *config)
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/* Remember the frequency of the input clock */
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priv->clkin = ALTCLK_FREQUENCY;
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#else
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timvdbg("tiva_gptm_configure: Error: alternate clock only available on TM4C129 devices\n");
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return (TIMER_HANDLE)NULL;
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#endif /* CONFIG_ARCH_CHIP_TM4C129 */
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}
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else
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{
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@ -2301,11 +2312,13 @@ void tiva_timer32_setinterval(TIMER_HANDLE handle, uint32_t interval)
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const struct tiva_timer32config_s *timer;
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irqstate_t flags;
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uintptr_t base;
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uintptr_t moder;
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uintptr_t loadr;
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uintptr_t imrr;
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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uintptr_t moder;
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uint32_t modev1;
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uint32_t modev2;
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#endif /* CONFIG_ARCH_CHIP_TM4C129 */
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bool toints;
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DEBUGASSERT(priv && priv->attr && priv->config &&
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@ -2329,7 +2342,6 @@ void tiva_timer32_setinterval(TIMER_HANDLE handle, uint32_t interval)
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}
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loadr = base + TIVA_TIMER_TAILR_OFFSET;
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moder = base + TIVA_TIMER_TAMR_OFFSET;
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imrr = base + TIVA_TIMER_IMR_OFFSET;
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/* Make the following atomic */
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@ -2344,13 +2356,15 @@ void tiva_timer32_setinterval(TIMER_HANDLE handle, uint32_t interval)
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if (toints)
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{
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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/* Clearing the TACINTD bit allows the time-out interrupt to be
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* generated as normal
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*/
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moder = base + TIVA_TIMER_TAMR_OFFSET;
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modev1 = getreg32(moder);
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modev2 = modev1 & ~TIMER_TnMR_TnCINTD;
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putreg32(modev2, moder);
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#endif /* CONFIG_ARCH_CHIP_TM4C129 */
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/* Set the new interrupt mask */
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@ -2366,8 +2380,10 @@ void tiva_timer32_setinterval(TIMER_HANDLE handle, uint32_t interval)
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lldbg("%08x<-%08x\n", loadr, interval);
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if (toints)
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{
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# ifdef CONFIG_ARCH_CHIP_TM4C129
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lldbg("%08x->%08x\n", moder, modev1);
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lldbg("%08x<-%08x\n", moder, modev2);
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# endif /* CONFIG_ARCH_CHIP_TM4C129 */
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lldbg("%08x<-%08x\n", imrr, priv->imr);
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}
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#endif
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@ -2421,12 +2437,14 @@ void tiva_timer16_setinterval(TIMER_HANDLE handle, uint16_t interval, int tmndx)
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const struct tiva_timer16config_s *timer;
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irqstate_t flags;
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uintptr_t base;
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uintptr_t moder;
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uintptr_t loadr;
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uintptr_t imrr;
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uint32_t intbit;
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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uintptr_t moder;
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uint32_t modev1;
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uint32_t modev2;
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#endif /* CONFIG_ARCH_CHIP_TM4C129 */
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uint32_t intbit;
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bool toints;
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DEBUGASSERT(priv && priv->attr && priv->config &&
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@ -2441,13 +2459,11 @@ void tiva_timer16_setinterval(TIMER_HANDLE handle, uint16_t interval, int tmndx)
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{
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intbit = TIMER_INT_TBTO;
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loadr = base + TIVA_TIMER_TBILR_OFFSET;
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moder = base + TIVA_TIMER_TBMR_OFFSET;
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}
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else
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{
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intbit = TIMER_INT_TATO;
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loadr = base + TIVA_TIMER_TAILR_OFFSET;
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moder = base + TIVA_TIMER_TAMR_OFFSET;
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}
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imrr = base + TIVA_TIMER_IMR_OFFSET;
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@ -2478,6 +2494,16 @@ void tiva_timer16_setinterval(TIMER_HANDLE handle, uint16_t interval, int tmndx)
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if (toints)
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{
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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if (tmndx)
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{
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moder = base + TIVA_TIMER_TBMR_OFFSET;
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}
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else
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{
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moder = base + TIVA_TIMER_TAMR_OFFSET;
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}
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/* Clearing the TACINTD bit allows the time-out interrupt to be
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* generated as normal
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*/
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@ -2485,6 +2511,7 @@ void tiva_timer16_setinterval(TIMER_HANDLE handle, uint16_t interval, int tmndx)
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modev1 = getreg32(moder);
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modev2 = modev1 & ~TIMER_TnMR_TnCINTD;
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putreg32(modev2, moder);
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#endif /* CONFIG_ARCH_CHIP_TM4C129 */
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/* Set the new interrupt mask */
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@ -2500,8 +2527,10 @@ void tiva_timer16_setinterval(TIMER_HANDLE handle, uint16_t interval, int tmndx)
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lldbg("%08x<-%08x\n", loadr, interval);
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if (toints)
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{
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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lldbg("%08x->%08x\n", moder, modev1);
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lldbg("%08x<-%08x\n", moder, modev2);
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#endif
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lldbg("%08x<-%08x\n", imrr, priv->imr);
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}
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#endif
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@ -2613,7 +2642,7 @@ uint32_t tiva_timer32_remaining(TIMER_HANDLE handle)
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irqrestore(flags);
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return remaining;
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}
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#endif
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#endif /* CONFIG_TIVA_TIMER32_PERIODIC */
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/****************************************************************************
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* Name: tiva_rtc_setalarm
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@ -2644,8 +2673,10 @@ void tiva_rtc_setalarm(TIMER_HANDLE handle, uint32_t delay)
|
||||
uintptr_t base;
|
||||
uint32_t counter;
|
||||
uint32_t match;
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
uint32_t adcev;
|
||||
uint32_t adcbits;
|
||||
#endif
|
||||
|
||||
DEBUGASSERT(priv && priv->attr && priv->config &&
|
||||
priv->config->mode == TIMER32_MODE_RTC);
|
||||
@ -2667,7 +2698,6 @@ void tiva_rtc_setalarm(TIMER_HANDLE handle, uint32_t delay)
|
||||
*/
|
||||
|
||||
base = priv->attr->base;
|
||||
adcbits = TIMER_ISADCRTCM(config) ? TIMER_ADCEV_RTCADCEN : 0;
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
@ -2679,12 +2709,15 @@ void tiva_rtc_setalarm(TIMER_HANDLE handle, uint32_t delay)
|
||||
match = counter + delay;
|
||||
putreg32(match, base + TIVA_TIMER_TAMATCHR_OFFSET);
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
/* Enable ADC trigger (if selected). NOTE the TAOTE bit was already
|
||||
* selected in the GPTMCTL register when the timer was configured.
|
||||
*/
|
||||
|
||||
adcev = getreg32(base + TIVA_TIMER_ADCEV_OFFSET);
|
||||
adcbits = TIMER_ISADCRTCM(config) ? TIMER_ADCEV_RTCADCEN : 0;
|
||||
putreg32(adcev | adcbits, base + TIVA_TIMER_ADCEV_OFFSET);
|
||||
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
||||
|
||||
/* TODO: Set uDMA trigger in the same manner */
|
||||
|
||||
@ -2698,8 +2731,10 @@ void tiva_rtc_setalarm(TIMER_HANDLE handle, uint32_t delay)
|
||||
|
||||
lldbg("%08x->%08x\n", base + TIVA_TIMER_TAR_OFFSET, counter);
|
||||
lldbg("%08x<-%08x\n", base + TIVA_TIMER_TAMATCHR_OFFSET, match);
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
lldbg("%08x->%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev);
|
||||
lldbg("%08x<-%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev | adcbits);
|
||||
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
||||
lldbg("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr);
|
||||
#endif
|
||||
}
|
||||
@ -2743,8 +2778,10 @@ void tiva_timer32_relmatch(TIMER_HANDLE handle, uint32_t relmatch)
|
||||
irqstate_t flags;
|
||||
uint32_t counter;
|
||||
uint32_t match;
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
uint32_t adcev;
|
||||
uint32_t adcbits;
|
||||
#endif
|
||||
|
||||
DEBUGASSERT(priv && priv->attr && priv->config &&
|
||||
priv->config->mode != TIMER16_MODE);
|
||||
@ -2766,8 +2803,6 @@ void tiva_timer32_relmatch(TIMER_HANDLE handle, uint32_t relmatch)
|
||||
*/
|
||||
|
||||
base = priv->attr->base;
|
||||
adcbits = TIMER_ISADCMATCH(config) ? TIMER_ADCEV_CAMADCEN : 0;
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
/* Set the match register to the current value of the timer counter plus
|
||||
@ -2780,12 +2815,15 @@ void tiva_timer32_relmatch(TIMER_HANDLE handle, uint32_t relmatch)
|
||||
match = counter + relmatch;
|
||||
putreg32(match, base + TIVA_TIMER_TAMATCHR_OFFSET);
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
/* Enable ADC trigger (if selected). NOTE the TAOTE bit was already
|
||||
* selected in the GPTMCTL register when the timer was configured.
|
||||
*/
|
||||
|
||||
adcev = getreg32(base + TIVA_TIMER_ADCEV_OFFSET);
|
||||
adcev = getreg32(base + TIVA_TIMER_ADCEV_OFFSET);
|
||||
adcbits = TIMER_ISADCMATCH(config) ? TIMER_ADCEV_CAMADCEN : 0;
|
||||
putreg32(adcev | adcbits, base + TIVA_TIMER_ADCEV_OFFSET);
|
||||
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
||||
|
||||
/* Enable interrupts as necessary */
|
||||
|
||||
@ -2797,12 +2835,15 @@ void tiva_timer32_relmatch(TIMER_HANDLE handle, uint32_t relmatch)
|
||||
|
||||
lldbg("%08x->%08x\n", base + TIVA_TIMER_TAR_OFFSET, counter);
|
||||
lldbg("%08x<-%08x\n", base + TIVA_TIMER_TAMATCHR_OFFSET, match);
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
lldbg("%08x->%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev);
|
||||
lldbg("%08x<-%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev | adcbits);
|
||||
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
||||
lldbg("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr);
|
||||
#endif
|
||||
#endif /* CONFIG_TIVA_TIMER_REGDEBUG */
|
||||
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_TIVA_TIMER32_PERIODIC */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer16_relmatch
|
||||
@ -2856,15 +2897,17 @@ void tiva_timer16_relmatch(TIMER_HANDLE handle, uint32_t relmatch, int tmndx)
|
||||
uintptr_t prescr;
|
||||
uintptr_t matchr;
|
||||
uintptr_t prematchr;
|
||||
uintptr_t adcevr;
|
||||
uintptr_t imr;
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
uintptr_t adcevr;
|
||||
uint32_t adcevv;
|
||||
uint32_t adcbits;
|
||||
#endif
|
||||
uint32_t timerv;
|
||||
uint32_t prescv;
|
||||
uint32_t matchv;
|
||||
uint32_t prematchv;
|
||||
uint32_t adcevv;
|
||||
uint32_t counter;
|
||||
uint32_t adcbits;
|
||||
bool countup;
|
||||
|
||||
DEBUGASSERT(priv && priv->attr && priv->config &&
|
||||
@ -2894,9 +2937,11 @@ void tiva_timer16_relmatch(TIMER_HANDLE handle, uint32_t relmatch, int tmndx)
|
||||
matchr = base + TIVA_TIMER_TBMATCHR_OFFSET;
|
||||
prematchr = base + TIVA_TIMER_TBPMR_OFFSET;
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
/* Do we need to enable ADC trigger on the match? */
|
||||
|
||||
adcbits = TIMER_ISADCMATCH(config) ? TIMER_ADCEV_CBMADCEN : 0;
|
||||
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -2917,12 +2962,17 @@ void tiva_timer16_relmatch(TIMER_HANDLE handle, uint32_t relmatch, int tmndx)
|
||||
matchr = base + TIVA_TIMER_TAMATCHR_OFFSET;
|
||||
prematchr = base + TIVA_TIMER_TAPMR_OFFSET;
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
/* Do we need to enable ADC trigger on the match? */
|
||||
|
||||
adcbits = TIMER_ISADCMATCH(config) ? TIMER_ADCEV_CAMADCEN : 0;
|
||||
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
adcevr = base + TIVA_TIMER_ADCEV_OFFSET;
|
||||
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
||||
|
||||
imr = base + TIVA_TIMER_IMR_OFFSET;
|
||||
countup = TIMER_ISCOUNTUP(config);
|
||||
|
||||
@ -2968,12 +3018,14 @@ void tiva_timer16_relmatch(TIMER_HANDLE handle, uint32_t relmatch, int tmndx)
|
||||
putreg32(matchv, matchr);
|
||||
putreg32(prematchv, prematchr);
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
/* Enable ADC trigger (if selected). NOTE the TnOTE bit was already
|
||||
* selected in the GPTMCTL register when the timer was configured.
|
||||
*/
|
||||
|
||||
adcevv = getreg32(adcevr);
|
||||
putreg32(adcevv | adcbits, adcevr);
|
||||
#endif
|
||||
|
||||
/* Enable interrupts as necessary */
|
||||
|
||||
@ -2987,8 +3039,10 @@ void tiva_timer16_relmatch(TIMER_HANDLE handle, uint32_t relmatch, int tmndx)
|
||||
lldbg("%08x->%08x\n", prescr, prescv);
|
||||
lldbg("%08x<-%08x\n", matchr, matchv);
|
||||
lldbg("%08x<-%08x\n", prematchr, prematchv);
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
lldbg("%08x->%08x\n", adcevr, adcevv);
|
||||
lldbg("%08x<-%08x\n", adcevr, adcevv | adcbits);
|
||||
#endif
|
||||
lldbg("%08x<-%08x\n", imr, priv->imr);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -572,7 +572,19 @@ int tiva_timer_register(FAR const char *devpath, int gptm, bool altclk)
|
||||
/* Initialize the non-zero elements of lower half state structure */
|
||||
|
||||
priv->ops = &g_timer_ops;
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
priv->clkin = altclk ? ALTCLK_FREQUENCY : SYSCLK_FREQUENCY;
|
||||
#else
|
||||
if (altclk)
|
||||
{
|
||||
timdbg("ERROR: Alternate clock unsupported on TM4C123 architecture\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
else
|
||||
{
|
||||
priv->clkin = SYSCLK_FREQUENCY;
|
||||
}
|
||||
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
||||
|
||||
config = &priv->config;
|
||||
config->cmn.gptm = gptm;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user