EMAC/PHY headers
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3271 42af7a65-404d-4744-a932-0658087f49c3
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arch/hc/src/mc9s12ne64/mc9s12ne64_emacv1.h
Executable file
188
arch/hc/src/mc9s12ne64/mc9s12ne64_emacv1.h
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_emacv1.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_EMACV1_H
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#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_EMACV1_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define HCS12_EMAC_NETCTL_OFFSET 0x0000 /* Network Control (8-bit) */
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#define HCS12_EMAC_RXCTS_OFFSET 0x0003 /* Receive Control and Status (8-bit) */
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#define HCS12_EMAC_TXCTS_OFFSET 0x0004 /* Transmit Control and Status (8-bit) */
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#define HCS12_EMAC_ETCTL_OFFSET 0x0005 /* Ethertype Control (8-bit) */
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#define HCS12_EMAC_ETYPE_OFFSET 0x0006 /* Programmable Ethertype (16-bit) */
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#define HCS12_EMAC_PTIME_OFFSET 0x0008 /* PAUSE Timer Value and Counter (16-bit) */
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#define HCS12_EMAC_IEVENT_OFFSET 0x000a /* Interrupt Event (16-bit) */
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#define HCS12_EMAC_IMASK_OFFSET 0x000c /* Interrupt Mask (16-bit) */
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#define HCS12_EMAC_SWRST_OFFSET 0x000e /* Software Reset (8-bit) */
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#define HCS12_EMAC_MPADR_OFFSET 0x0010 /* MII Management PHY Address (8-bit) */
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#define HCS12_EMAC_MRADR_OFFSET 0x0011 /* MII Management Register Address (8-bit) */
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#define HCS12_EMAC_MWDATA_OFFSET 0x0012 /* MII Management Write Data (16-bit) */
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#define HCS12_EMAC_MRDATA_OFFSET 0x0014 /* MII Management Read Data (16-bit) */
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#define HCS12_EMAC_MCMST_OFFSET 0x0016 /* MII Management Command and Status (8-bit) */
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#define HCS12_EMAC_BUFCFG_OFFSET 0x0018 /* Ethernet Buffer Configuration (16-bit) */
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#define HCS12_EMAC_RXAEFP_OFFSET 0x001a /* Receive A End-of-Frame Pointer (16-bit) */
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#define HCS12_EMAC_RXBEFP_OFFSET 0x001c /* Receive B End-of-Frame Pointer (16-bit) */
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#define HCS12_EMAC_TXEFP_OFFSET 0x001e /* Transmit End-of-Frame Pointer (16-bit) */
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#define HCS12_EMAC_MCHASH48_OFFSET 0x0020 /* Multicast Hash Table 48-63 (16-bit) */
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#define HCS12_EMAC_MCHASH32_OFFSET 0x0022 /* Multicast Hash Table 32-47 (16-bit) */
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#define HCS12_EMAC_MCHASH16_OFFSET 0x0024 /* Multicast Hash Table 16-31 (16-bit) */
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#define HCS12_EMAC_MCHASH0_OFFSET 0x0026 /* Multicast Hash Table 0:15 (16-bit) */
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#define HCS12_EMAC_MACAD32_OFFSET 0x0028 /* MAC Unicast AAddress 32-47 (16-bit) */
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#define HCS12_EMAC_MACAD16_OFFSET 0x002a /* MAC Unicast AAddress 16-31 (16-bit) */
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#define HCS12_EMAC_MACAD0_OFFSET 0x002c /* MAC Unicast AAddress 0-15 (16-bit) */
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#define HCS12_EMAC_EMISC _OFFSET 0x002e /* Miscellaneous (16-bit) */
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/* Register Addresses ***************************************************************/
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#define HCS12_EMAC_NETCTL (HCS12_EMAC_BASE+HCS12_EMAC_NETCTL_OFFSET)
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#define HCS12_EMAC_RXCTS (HCS12_EMAC_BASE+HCS12_EMAC_RXCTS_OFFSET)
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#define HCS12_EMAC_TXCTS (HCS12_EMAC_BASE+HCS12_EMAC_TXCTS_OFFSET)
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#define HCS12_EMAC_ETCTL (HCS12_EMAC_BASE+HCS12_EMAC_ETCTL_OFFSET)
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#define HCS12_EMAC_ETYPE (HCS12_EMAC_BASE+HCS12_EMAC_ETYPE_OFFSET)
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#define HCS12_EMAC_PTIME (HCS12_EMAC_BASE+HCS12_EMAC_PTIME_OFFSET)
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#define HCS12_EMAC_IEVENT (HCS12_EMAC_BASE+HCS12_EMAC_IEVENT_OFFSET)
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#define HCS12_EMAC_IMASK (HCS12_EMAC_BASE+HCS12_EMAC_IMASK_OFFSET)
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#define HCS12_EMAC_SWRST (HCS12_EMAC_BASE+HCS12_EMAC_SWRST_OFFSET)
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#define HCS12_EMAC_MPADR (HCS12_EMAC_BASE+HCS12_EMAC_MPADR_OFFSET)
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#define HCS12_EMAC_MRADR (HCS12_EMAC_BASE+HCS12_EMAC_MRADR_OFFSET)
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#define HCS12_EMAC_MWDATA (HCS12_EMAC_BASE+HCS12_EMAC_MWDATA_OFFSET)
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#define HCS12_EMAC_MRDATA (HCS12_EMAC_BASE+HCS12_EMAC_MRDATA_OFFSET)
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#define HCS12_EMAC_MCMST (HCS12_EMAC_BASE+HCS12_EMAC_MCMST_OFFSET)
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#define HCS12_EMAC_BUFCFG (HCS12_EMAC_BASE+HCS12_EMAC_BUFCFG_OFFSET)
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#define HCS12_EMAC_RXAEFP (HCS12_EMAC_BASE+HCS12_EMAC_RXAEFP_OFFSET)
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#define HCS12_EMAC_RXBEFP (HCS12_EMAC_BASE+HCS12_EMAC_RXBEFP_OFFSET)
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#define HCS12_EMAC_TXEFP (HCS12_EMAC_BASE+HCS12_EMAC_TXEFP_OFFSET)
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#define HCS12_EMAC_MCHASH48 (HCS12_EMAC_BASE+HCS12_EMAC_MCHASH48_OFFSET)
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#define HCS12_EMAC_MCHASH32 (HCS12_EMAC_BASE+HCS12_EMAC_MCHASH32_OFFSET)
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#define HCS12_EMAC_MCHASH16 (HCS12_EMAC_BASE+HCS12_EMAC_MCHASH16_OFFSET)
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#define HCS12_EMAC_MCHASH0 (HCS12_EMAC_BASE+HCS12_EMAC_MCHASH0_OFFSET)
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#define HCS12_EMAC_MACAD32 (HCS12_EMAC_BASE+HCS12_EMAC_MACAD32_OFFSET)
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#define HCS12_EMAC_MACAD16 (HCS12_EMAC_BASE+HCS12_EMAC_MACAD16_OFFSET)
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#define HCS12_EMAC_MACAD0 (HCS12_EMAC_BASE+HCS12_EMAC_MACAD0_OFFSET)
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#define HCS12_EMAC_EMISC (HCS12_EMAC_BASE+HCS12_EMAC_EMISC_OFFSET)
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/* Register Bit-Field Definitions ***************************************************/
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/* Network Control (8-bit) */
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#define EMAC_NETCTL_
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/* Receive Control and Status (8-bit) */
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#define EMAC_RXCTS_
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/* Transmit Control and Status (8-bit) */
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#define EMAC_TXCTS_
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/* Ethertype Control (8-bit) */
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#define EMAC_ETCTL_
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/* Programmable Ethertype (16-bit) -- 16-bit Ethernet type data */
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/* PAUSE Timer Value and Counter (16-bit) -- 16-bit PAUSER timer value */
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/* Interrupt Event (16-bit) */
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#define EMAC_IEVENT_
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/* Interrupt Mask (16-bit) */
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#define EMAC_IMASK_
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/* Software Reset (8-bit) */
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#define EMAC_SWRST_MACRST (1<< 7) /* Bit 7: EMAC is reset */
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/* MII Management PHY Address (8-bit) */
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#define EMAC_MPADR_MASK (0x1f)
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/* MII Management Register Address (8-bit) */
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#define EMAC_MRADR_MASK (0x1f)
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/* MII Management Write Data (16-bit) -- 16-bit write data */
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/* MII Management Read Data (16-bit) -- 16-bit read data */
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/* MII Management Command and Status (8-bit) */
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#define EMAC_MCMST_
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/* Ethernet Buffer Configuration (16-bit) */
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#define EMAC_BUFCFG_
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/* Receive A End-of-Frame Pointer (16-bit) */
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#define EMAC_RXAEFP_MASK (0x07ff)
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/* Receive B End-of-Frame Pointer (16-bit) */
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#define EMAC_RXBEFP_MASK (0x07ff)
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/* Transmit End-of-Frame Pointer (16-bit) */
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#define EMAC_TXEFP_MASK (0x07ff)
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/* Multicast Hash Table 48-63 (16-bit) -- 16-bits of MAC address */
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/* Multicast Hash Table 32-47 (16-bit) -- 16-bits of MAC address */
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/* Multicast Hash Table 16-31 (16-bit) -- 16-bits of MAC address */
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/* Multicast Hash Table 0:15 (16-bit) -- 16-bits of MAC address */
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/* MAC Unicast Address 32-47 (16-bit) -- 16-bits of address */
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/* MAC Unicast AAddress 16-31 (16-bit) -- 16-bits of address */
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/* MAC Unicast AAddress 0-15 (16-bit) -- 16-bits of address */
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/* Miscellaneous (16-bit) */
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#define EMAC_EMISC_
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_EMACV1_H */
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85
arch/hc/src/mc9s12ne64/mc9s12ne64_phyv2.h
Executable file
85
arch/hc/src/mc9s12ne64/mc9s12ne64_phyv2.h
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_phyv2.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_PHYV2_H
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#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_PHYV2_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define HCS12_PHY_EPHYCTL0_OFFSET 0x0000 /* Ethernet Physical Transceiver Control Register 0 */
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#define HCS12_PHY_EPHYCTL1_OFFSET 0x0001 /* Ethernet Physical Transceiver Control Register 1 */
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#define HCS12_PHY_EPHYSR_OFFSET 0x0002 /* Ethernet Physical Transceiver Status Register */
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/* Register Addresses ***************************************************************/
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#define HCS12_PHY_EPHYCTL0 (HCS12_EPHY_BASE+HCS12_PHY_EPHYCTL0_OFFSET)
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#define HCS12_PHY_EPHYCTL1 (HCS12_EPHY_BASE+HCS12_PHY_EPHYCTL1_OFFSET)
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#define HCS12_PHY_EPHYSR (HCS12_EPHY_BASE+HCS12_PHY_EPHYSR_OFFSET)
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/* Register Bit-Field Definitions ***************************************************/
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/* Ethernet Physical Transceiver Control Register 0 */
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#define PHY_EPHYCTL0_
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/* Ethernet Physical Transceiver Control Register 1 */
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#define PHY_EPHYCTL1_
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/* Ethernet Physical Transceiver Status Register */
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#define PHY_EPHYSR_
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_PHYV2_H */
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