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arch/arm: Add the initial cortex-a7 archtiecture support

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This commit is contained in:
zhangyuan7 2019-03-19 11:51:29 -06:00 committed by Gregory Nutt
parent cc1595f232
commit 471a18ee4d
10 changed files with 55 additions and 74 deletions
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12
arch/arm/include/irq.h
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@ -1,7 +1,8 @@
/****************************************************************************
* arch/arm/include/irq.h
*
* Copyright (C) 2007-2009, 2011, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009, 2011, 2015, 2019 Gregory Nutt. All rights
* reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -56,14 +57,11 @@
* save structure and up_irq_save()/up_irq_restore() functions)
*/
#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \
defined(CONFIG_ARCH_CORTEXA9)
#if defined(CONFIG_ARCH_ARMV7A)
# include <arch/armv7-a/irq.h>
#elif defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR5) || \
defined(CONFIG_ARCH_CORTEXR7)
#elif defined(CONFIG_ARCH_ARMV7R)
# include <arch/armv7-r/irq.h>
#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
defined(CONFIG_ARCH_CORTEXM7)
#elif defined(CONFIG_ARCH_ARMV7M)
# include <arch/armv7-m/irq.h>
#elif defined(CONFIG_ARCH_CORTEXM0)
# include <arch/armv6-m/irq.h>

11
arch/arm/include/spinlock.h
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/include/spinlock.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -48,14 +48,11 @@
* save structure and up_irq_save()/up_irq_restore() functions)
*/
#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \
defined(CONFIG_ARCH_CORTEXA9)
#if defined(CONFIG_ARCH_ARMV7A)
# include <arch/armv7-a/spinlock.h>
#elif defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR5) || \
defined(CONFIG_ARCH_CORTEXR7)
#elif defined(CONFIG_ARCH_ARMV7R)
# include <arch/armv7-r/spinlock.h>
#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
defined(CONFIG_ARCH_CORTEXM7)
#elif defined(CONFIG_ARCH_ARMV7M)
# include <arch/armv7-m/spinlock.h>
#elif defined(CONFIG_ARCH_CORTEXM0)
# include <arch/armv6-m/spinlock.h>

11
arch/arm/include/syscall.h
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/include/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -46,14 +46,11 @@
/* Include ARM architecture-specific syscall macros */
#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \
defined(CONFIG_ARCH_CORTEXA9)
#if defined(CONFIG_ARCH_ARMV7A)
# include <arch/armv7-a/syscall.h>
#elif defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR5) || \
defined(CONFIG_ARCH_CORTEXR7)
#elif defined(CONFIG_ARCH_ARMV7R)
# include <arch/armv7-r/syscall.h>
#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
defined(CONFIG_ARCH_CORTEXM7)
#elif defined(CONFIG_ARCH_ARMV7M)
# include <arch/armv7-m/syscall.h>
#elif defined(CONFIG_ARCH_CORTEXM0)
# include <arch/armv6-m/syscall.h>

24
arch/arm/src/Makefile
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@ -1,8 +1,8 @@
############################################################################
# arch/arm/src/Makefile
#
# Copyright (C) 2007-2009, 2011-2012, 2014-2016 Gregory Nutt. All rights
# reserved.
# Copyright (C) 2007-2009, 2011-2012, 2014-2016, 2019 Gregory Nutt. All
# rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
@ -37,27 +37,15 @@
-include $(TOPDIR)/Make.defs
-include chip$(DELIM)Make.defs
ifeq ($(CONFIG_ARCH_CORTEXA5),y) # Cortex-A5 is ARMv7-A
ifeq ($(CONFIG_ARCH_ARMV7A),y) # ARMv7-A
ARCH_SUBDIR = armv7-a
else ifeq ($(CONFIG_ARCH_CORTEXA8),y) # Cortex-A8 is ARMv7-A
ARCH_SUBDIR = armv7-a
else ifeq ($(CONFIG_ARCH_CORTEXA9),y) # Cortex-A9 is ARMv7-A
ARCH_SUBDIR = armv7-a
else ifeq ($(CONFIG_ARCH_CORTEXR4),y) # Cortex-R4 is ARMv7-R
else ifeq ($(CONFIG_ARCH_ARMV7R),y) # ARMv7-R
ARCH_SUBDIR = armv7-r
else ifeq ($(CONFIG_ARCH_CORTEXR5),y) # Cortex-R5 is ARMv7-R
ARCH_SUBDIR = armv7-r
else ifeq ($(CONFIG_ARCH_CORTEXR7),y) # Cortex-R7 is ARMv7-R
ARCH_SUBDIR = armv7-r
else ifeq ($(CONFIG_ARCH_CORTEXM3),y) # Cortex-M3 is ARMv7-M
ARCH_SUBDIR = armv7-m
else ifeq ($(CONFIG_ARCH_CORTEXM4),y) # Cortex-M4 is ARMv7E-M
ARCH_SUBDIR = armv7-m
else ifeq ($(CONFIG_ARCH_CORTEXM7),y) # Cortex-M4 is ARMv7E-M
else ifeq ($(CONFIG_ARCH_ARMV7M),y) # ARMv7-M
ARCH_SUBDIR = armv7-m
else ifeq ($(CONFIG_ARCH_CORTEXM0),y) # Cortex-M0 is ARMv6-M
ARCH_SUBDIR = armv6-m
else # ARM9, ARM7TDMI
else # ARM9, ARM7TDMI, etc.
ARCH_SUBDIR = arm
endif

17
arch/arm/src/armv7-a/Toolchain.defs
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@ -90,6 +90,23 @@ endif
# reliable code generation.
#
ARCHCPUFLAGS += -march=armv7-a
ifeq ($(CONFIG_ARM_THUMB),y)
ARCHCPUFLAGS += -mthumb
endif
ifeq ($(CONFIG_ARCH_FPU),y)
ARCHCPUFLAGS += -mfloat-abi=hard
endif
ifeq ($(CONFIG_ARCH_CORTEXA5),y)
ARCHCPUFLAGS += -mcpu=cortex-a5
elif ($(CONFIG_ARCH_CORTEXA7),y)
ARCHCPUFLAGS += -mcpu=cortex-a7
elif ($(CONFIG_ARCH_CORTEXA8),y)
ARCHCPUFLAGS += -mcpu=cortex-a8
elif ($(CONFIG_ARCH_CORTEXA9),y)
ARCHCPUFLAGS += -mcpu=cortex-a9
endif
ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL)
endif

3
arch/arm/src/armv7-a/mmu.h
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@ -596,6 +596,9 @@
#define MMU_L2_UALLOCFLAGS (PTE_TYPE_SMALL | PTE_WRITE_BACK | PTE_AP_RW01)
#define MMU_L2_KALLOCFLAGS (PTE_TYPE_SMALL | PTE_WRITE_BACK | PTE_AP_RW1)
#define MMU_L2_IOFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_RW1)
#define MMU_L2_STRONGLY_ORDER (PTE_TYPE_SMALL | PTE_STRONGLY_ORDER | PTE_AP_RW1)
#define MMU_L1_PGTABFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PTE_WRITE_THROUGH | \
PMD_PTE_DOM(0))
#define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1)

4
arch/arm/src/armv7-a/mpcore.h
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@ -60,7 +60,11 @@
/* Peripheral Base Offsets **************************************************/
#define MPCORE_SCU_OFFSET 0x0000 /* 0x0000-0x00fc SCU registers */
#ifdef CONFIG_ARCH_CORTEXA7
#define MPCORE_ICC_OFFSET 0x2000 /* 0x0000-0x00FC Interrupt conroller interface */
#else
#define MPCORE_ICC_OFFSET 0x0100 /* 0x0000-0x00FC Interrupt conroller interface */
#endif
#define MPCORE_GTM_OFFSET 0x0200 /* 0x0200-0x02ff Global timer */
/* 0x0300-0x05ff Reserved */
#define MPCORE_PTM_OFFSET 0x0600 /* 0x0600-0x06ff Private timers and watchdogs */

26
arch/arm/src/common/up_internal.h
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@ -1,7 +1,7 @@
/****************************************************************************
* common/up_internal.h
*
* Copyright (C) 2007-2015, 2018 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2015, 2018-2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -100,8 +100,7 @@
* some configurations.
*/
#if defined(CONFIG_ARCH_CORTEXM0) || defined(CONFIG_ARCH_CORTEXM3) || \
defined(CONFIG_ARCH_CORTEXM4) || defined(CONFIG_ARCH_CORTEXM7)
#if defined(CONFIG_ARCH_CORTEXM0) || defined(CONFIG_ARCH_ARMV7M)
/* If the floating point unit is present and enabled, then save the
* floating point registers as well as normal ARM registers. This only
@ -115,14 +114,11 @@
# endif
# define up_restorestate(regs) (CURRENT_REGS = regs)
/* The Cortex-A and Cortex-R supports the same mechanism, but only lazy
/* The Cortex-A and Cortex-R support the same mechanism, but only lazy
* floating point register save/restore.
*/
#elif defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \
defined(CONFIG_ARCH_CORTEXA9) || \
defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR5) || \
defined(CONFIG_ARCH_CORTEXR7)
#elif defined(CONFIG_ARCH_ARMV7A) || defined(CONFIG_ARCH_ARMV7R)
/* If the floating point unit is present and enabled, then save the
* floating point registers as well as normal ARM registers.
@ -335,8 +331,7 @@ void up_pminitialize(void);
# define up_pminitialize()
#endif
#if defined(CONFIG_ARCH_CORTEXM0) || defined(CONFIG_ARCH_CORTEXM3) || \
defined(CONFIG_ARCH_CORTEXM4) || defined(CONFIG_ARCH_CORTEXM7)
#if defined(CONFIG_ARCH_CORTEXM0) || defined(CONFIG_ARCH_ARMV7M)
void up_systemreset(void) noreturn_function;
#endif
@ -346,8 +341,7 @@ void up_irqinitialize(void);
/* Exception handling logic unique to the Cortex-M family */
#if defined(CONFIG_ARCH_CORTEXM0) || defined(CONFIG_ARCH_CORTEXM3) || \
defined(CONFIG_ARCH_CORTEXM4) || defined(CONFIG_ARCH_CORTEXM7)
#if defined(CONFIG_ARCH_CORTEXM0) || defined(CONFIG_ARCH_ARMV7M)
/* Interrupt acknowledge and dispatch */
@ -359,8 +353,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs);
int up_svcall(int irq, FAR void *context, FAR void *arg);
int up_hardfault(int irq, FAR void *context, FAR void *arg);
# if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
defined(CONFIG_ARCH_CORTEXM7)
# if defined(CONFIG_ARCH_ARMV7M)
int up_memfault(int irq, FAR void *context, FAR void *arg);
@ -370,10 +363,7 @@ int up_memfault(int irq, FAR void *context, FAR void *arg);
* (but should be back-ported to the ARM7 and ARM9 families).
*/
#elif defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \
defined(CONFIG_ARCH_CORTEXA9) || \
defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR5) || \
defined(CONFIG_ARCH_CORTEXR7)
#elif defined(CONFIG_ARCH_ARMV7A) || defined(CONFIG_ARCH_ARMV7R)
/* Interrupt acknowledge and dispatch */

3
arch/arm/src/common/up_vfork.c
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@ -234,8 +234,7 @@ pid_t up_vfork(const struct vfork_s *context)
/* REVISIT: This logic is *not* common. */
#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \
defined(CONFIG_ARCH_CORTEXA9)
#if defined(CONFIG_ARCH_ARMV7A)
# ifdef CONFIG_BUILD_KERNEL
child->cmn.xcp.syscall[index].cpsr =

18
libs/libc/machine/arm/Make.defs
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@ -39,26 +39,14 @@ else ifeq ($(CONFIG_ARCH_ARM920T),y) # ARM920T is ARMv4T
include ${TOPDIR}/libs/libc/machine/arm/arm/Make.defs
else ifeq ($(CONFIG_ARCH_ARM926EJS),y) # ARM926EJS is ARMv5TE
include ${TOPDIR}/libs/libc/machine/arm/arm/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXA5),y) # Cortex-A5 is ARMv7-A
else ifeq ($(CONFIG_ARCH_ARMV7A),y) # All ARMv7-A
include ${TOPDIR}/libs/libc/machine/arm/armv7-a/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXA8),y) # Cortex-A8 is ARMv7-A
include ${TOPDIR}/libs/libc/machine/arm/armv7-a/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXA9),y) # Cortex-A9 is ARMv7-A
include ${TOPDIR}/libs/libc/machine/arm/armv7-a/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXR4),y) # Cortex-R4 is ARMv7-R
include ${TOPDIR}/libs/libc/machine/arm/armv7-r/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXR5),y) # Cortex-R5 is ARMv7-R
include ${TOPDIR}/libs/libc/machine/arm/armv7-r/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXR7),y) # Cortex-R7 is ARMv7-R
else ifeq ($(CONFIG_ARCH_ARMV7R),y) # All ARMv7-R
include ${TOPDIR}/libs/libc/machine/arm/armv7-r/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXM0),y) # Cortex-M0 is ARMv6-M
include ${TOPDIR}/libs/libc/machine/arm/armv6-m/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXM3),y) # Cortex-M3 is ARMv7-M
else ifeq ($(CONFIG_ARCH_ARMV7M),y) # All ARMv7-M
include ${TOPDIR}/libs/libc/machine/arm/armv7-m/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXM33),y) # Cortex-M33 is ARMv8-M
include ${TOPDIR}/libs/libc/machine/arm/armv8/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXM4),y) # Cortex-M4 is ARMv7E-M
include ${TOPDIR}/libs/libc/machine/arm/armv7-m/Make.defs
else ifeq ($(CONFIG_ARCH_CORTEXM7),y) # Cortex-M4 is ARMv7E-M
include ${TOPDIR}/libs/libc/machine/arm/armv7-m/Make.defs
endif