arch/arm/src/tiva/hardware/tiva_wdt.h: Add WDT register definition header file for all LM, Tiva, and CC13xx parts.
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Gregory Nutt
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arch/arm/src/tiva/hardware/tiva_wdt.h
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arch/arm/src/tiva/hardware/tiva_wdt.h
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/********************************************************************************************
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* arch/arm/src/tiva/hardware/tiva_wdt.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_WDT_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include <hardware/tiva_memorymap.h>
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* WDT register offsets *********************************************************************/
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#define TIVA_WDT_LOAD_OFFSET 0x0000 /* Configuration */
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#define TIVA_WDT_VALUE_OFFSET 0x0004 /* Current Count Value */
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#define TIVA_WDT_CTL_OFFSET 0x0008 /* Control */
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#define TIVA_WDT_ICR_OFFSET 0x000c /* Interrupt Clear */
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#define TIVA_WDT_RIS_OFFSET 0x0010 /* Raw Interrupt Status */
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#define TIVA_WDT_MIS_OFFSET 0x0014 /* Masked Interrupt Status */
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#define TIVA_WDT_TEST_OFFSET 0x0418 /* Test Mode */
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#if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
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# define TIVA_WDT_INT_CAUSE_OFFSET 0x041c /* Interrupt Cause Test Mode */
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#endif
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#define TIVA_WDT_LOCK_OFFSET 0x0c00 /* Lock */
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#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_WDT_PERIPHID4_OFFSET 0x0fd0 /* Watchdog Peripheral Identification 4 */
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# define TIVA_WDT_PERIPHID5_OFFSET 0x0fd4 /* Watchdog Peripheral Identification 5 */
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# define TIVA_WDT_PERIPHID6_OFFSET 0x0fd5 /* Watchdog Peripheral Identification 6 */
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# define TIVA_WDT_PERIPHID7_OFFSET 0x0fdc /* Watchdog Peripheral Identification 7 */
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# define TIVA_WDT_PERIPHID0_OFFSET 0x0fe0 /* Watchdog Peripheral Identification 0 */
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# define TIVA_WDT_PERIPHID1_OFFSET 0x0fe4 /* Watchdog Peripheral Identification 1 */
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# define TIVA_WDT_PERIPHID2_OFFSET 0x0fe8 /* Watchdog Peripheral Identification 2 */
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# define TIVA_WDT_PERIPHID3_OFFSET 0x0fec /* Watchdog Peripheral Identification 3 */
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# define TIVA_WDT_CELLID0_OFFSET 0x0ff0 /* Watchdog PrimeCell Identification 0 */
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# define TIVA_WDT_CELLID1_OFFSET 0x0ff4 /* Watchdog PrimeCell Identification 1 */
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# define TIVA_WDT_CELLID2_OFFSET 0x0ff8 /* Watchdog PrimeCell Identification 2 */
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# define TIVA_WDT_CELLID3_OFFSET 0x0ffc /* Watchdog PrimeCell Identification 3 */
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#endif
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/* WDT register addresses *******************************************************************/
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#define TIVA_WDT_LOAD (TIVA_WDT_BASE + TIVA_WDT_LOAD_OFFSET)
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#define TIVA_WDT_VALUE (TIVA_WDT_BASE + TIVA_WDT_VALUE_OFFSET)
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#define TIVA_WDT_CTL (TIVA_WDT_BASE + TIVA_WDT_CTL_OFFSET)
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#define TIVA_WDT_ICR (TIVA_WDT_BASE + TIVA_WDT_ICR_OFFSET)
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#define TIVA_WDT_RIS (TIVA_WDT_BASE + TIVA_WDT_RIS_OFFSET)
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#define TIVA_WDT_MIS (TIVA_WDT_BASE + TIVA_WDT_MIS_OFFSET)
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#define TIVA_WDT_TEST (TIVA_WDT_BASE + TIVA_WDT_TEST_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
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# define TIVA_WDT_INT_CAUSE (TIVA_WDT_BASE + TIVA_WDT_INT_CAUSE_OFFSET)
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#endif
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#define TIVA_WDT_LOCK (TIVA_WDT_BASE + TIVA_WDT_LOCK_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_WDT_PERIPHID4 (TIVA_WDT_BASE + TIVA_WDT_PERIPHID4_OFFSET)
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# define TIVA_WDT_PERIPHID5 (TIVA_WDT_BASE + TIVA_WDT_PERIPHID5_OFFSET)
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# define TIVA_WDT_PERIPHID6 (TIVA_WDT_BASE + TIVA_WDT_PERIPHID6_OFFSET)
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# define TIVA_WDT_PERIPHID7 (TIVA_WDT_BASE + TIVA_WDT_PERIPHID7_OFFSET)
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# define TIVA_WDT_PERIPHID0 (TIVA_WDT_BASE + TIVA_WDT_PERIPHID0_OFFSET)
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# define TIVA_WDT_PERIPHID1 (TIVA_WDT_BASE + TIVA_WDT_PERIPHID1_OFFSET)
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# define TIVA_WDT_PERIPHID2 (TIVA_WDT_BASE + TIVA_WDT_PERIPHID2_OFFSET)
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# define TIVA_WDT_PERIPHID3 (TIVA_WDT_BASE + TIVA_WDT_PERIPHID3_OFFSET)
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# define TIVA_WDT_CELLID0 (TIVA_WDT_BASE + TIVA_WDT_CELLID0_OFFSET)
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# define TIVA_WDT_CELLID1 (TIVA_WDT_BASE + TIVA_WDT_CELLID1_OFFSET)
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# define TIVA_WDT_CELLID2 (TIVA_WDT_BASE + TIVA_WDT_CELLID2_OFFSET)
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# define TIVA_WDT_CELLID3 (TIVA_WDT_BASE + TIVA_WDT_CELLID3_OFFSET)
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#endif
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/* WDT register bitfield definitions ********************************************************/
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/* Configuration (32-bit interval value) */
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/* Current Count Value (32-bit timer counter value) */
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/* Control */
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#define WDT_CTL_INTEN (1 << 0) /* Bit 0: WDT Interrupt Enable */
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#define WDT_CTL_RESEN (1 << 1) /* Bit 1: WDT Reset Enable */
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#if defined(CONFIG_ARCH_CHIP_LM4F) || defined(CONFIG_ARCH_CHIP_TM4C) || \
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defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
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# define WDT_CTL_INTTYPE (1 << 2) /* Bit 2: WDT Interrupt Type */
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# define WDT_CTL_INTTYPE_MASKABLE 0
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# define WDT_CTL_INTTYPE_NONMASKABLE WDT_CTL_INTTYPE
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#endif
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#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C)
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# define WDT_CTL_WRC (1 << 31) /* Bit 31: Write Complete */
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#endif
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/* Interrupt Clear.
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*
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* A write of any value to this register clears the WDT interrupt and reloads the 32-bit
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* counter from the LOAD register.
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*/
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/* Raw Interrupt Status */
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#define WDT_RIS_WDTRIS (1 << 0) /* Bit 0: Raw interrupt status */
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/* Masked Interrupt Status */
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#define WDT_MIS_WDTMIS (1 << 0) /* Bit 0: Masked interrupt status */
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/* Test Mode */
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#if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
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# define WDT_TEST_TEST_EN (1 << 0) /* Bit 0: Test enable */
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#endif
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#define WDT_TEST_STALL (1 << 8) /* Bit 8: WDT Stall Enable */
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/* Interrupt Cause Test Mode */
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#if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2)
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# define WDT_INT_CAUSE_CAUSE_INTR (1 << 0) /* Bit 0: Replica of RIS.WDTRIS */
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# define WDT_INT_CAUSE_CAUSE_RESET (1 << 1) /* Bit 1: Csuse of interrupt was a reset */
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#endif
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/* Lock (32-bit register unlock value) */
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#define WDT_LOCK_WDTLOCK_UNLOCK 0x1acce551
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#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C)
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/* Watchdog Peripheral Identification 0-7 */
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# define WDT_PERIPHID_PID_MASK (0xff) /* Bits 0-7: Watchdog peripheral ID n */
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/* Watchdog PrimeCell Identification 0-3 */
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# define WDT_CELLID0_CID_MASK (0xff) /* Bits 0-7: Watchdog PrimeCell ID n */
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#endif
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#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_V2_WDT_H */
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