Mirtoo differences from Konstantin; File system fix from Lorenz Meier
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5360 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
parent
ed622c80ce
commit
476db17b51
@ -10,4 +10,9 @@ config ARCH_LEDS
|
|||||||
---help---
|
---help---
|
||||||
"Support control of board LEDs by NuttX to indicate system state"
|
"Support control of board LEDs by NuttX to indicate system state"
|
||||||
|
|
||||||
|
config MIRTOO_RELEASE
|
||||||
|
int "Mirtoo Release 1 (R1)"
|
||||||
|
default 2
|
||||||
|
---help---
|
||||||
|
Select the Mirtoo release number
|
||||||
endif
|
endif
|
||||||
|
@ -199,19 +199,19 @@ PIN PIC32 SIGNAL(s) BOARD SIGNAL/USAGE
|
|||||||
--- ------------------------------------------------ ---------------------------------- ----------------------------------
|
--- ------------------------------------------------ ---------------------------------- ----------------------------------
|
||||||
29 VSS VSS Not available off module
|
29 VSS VSS Not available off module
|
||||||
--- ------------------------------------------------ ---------------------------------- ----------------------------------
|
--- ------------------------------------------------ ---------------------------------- ----------------------------------
|
||||||
30 OSC1/CLKI/RPA2/RA2 SO Not available off module
|
30 OSC1/CLKI/RPA2/RA2 SO (R1) DIN0 (R2) Not available off module
|
||||||
OSC1 Oscillator crystal input Not available
|
OSC1 Oscillator crystal input Not available
|
||||||
CLKI External clock source input Not available
|
CLKI External clock source input Not available
|
||||||
RPRA2 Peripheral Selection PORTA, Pin 2 Used for SO
|
RPRA2 Peripheral Selection PORTA, Pin 2 Used for SO
|
||||||
RA2 PORTA, Pin 2 Not available
|
RA2 PORTA, Pin 2 Not available
|
||||||
--- ------------------------------------------------ ---------------------------------- ----------------------------------
|
--- ------------------------------------------------ ---------------------------------- ----------------------------------
|
||||||
31 OSC2/CLKO/RPA3/RA3 DIN0 PORT0, to X1, pin 2
|
31 OSC2/CLKO/RPA3/RA3 DIN0 (R1) DIN3 (R2) PORT0, to X1, pin 2
|
||||||
OSC2 Oscillator crystal output Not available (also X13, pin1)
|
OSC2 Oscillator crystal output Not available (also X13, pin1)
|
||||||
CLKO Oscillator crystal output Not available
|
CLKO Oscillator crystal output Not available
|
||||||
RPA3 Peripheral Selection for PORTA, Pin 3 May be used for peripheral input
|
RPA3 Peripheral Selection for PORTA, Pin 3 May be used for peripheral input
|
||||||
RA3 PORTA, Pin 3 May be used for GPIO input
|
RA3 PORTA, Pin 3 May be used for GPIO input
|
||||||
--- ------------------------------------------------ ---------------------------------- ----------------------------------
|
--- ------------------------------------------------ ---------------------------------- ----------------------------------
|
||||||
32 TDO/RPA8/PMA8/RA8 DIN3 PORT3, to X5, pin 2
|
32 TDO/RPA8/PMA8/RA8 DIN3 (R1) S0 (R2) PORT3, to X5, pin 2
|
||||||
TDO JTAG test data output pin Not available (also X13, pin7)
|
TDO JTAG test data output pin Not available (also X13, pin7)
|
||||||
RPA8 PORTA, Pin 8 May be used for peripheral input
|
RPA8 PORTA, Pin 8 May be used for peripheral input
|
||||||
PMA8 Parallel Master Port Address bit 8 Not available
|
PMA8 Parallel Master Port Address bit 8 Not available
|
||||||
|
@ -74,7 +74,8 @@
|
|||||||
* PIN SIGNAL BOARD CONNECTION NOTES
|
* PIN SIGNAL BOARD CONNECTION NOTES
|
||||||
* ------ -------- ------------------------- --------------------------------
|
* ------ -------- ------------------------- --------------------------------
|
||||||
* RPA1 SI PGA117 and SST25VF032B SPI2 data OUT (SDO2)
|
* RPA1 SI PGA117 and SST25VF032B SPI2 data OUT (SDO2)
|
||||||
* RPA2 SO PGA117 and SST25VF032B SPI2 data IN (SDI2)
|
* RPA2 SO PGA117 and SST25VF032B R1, SPI2 data IN (SDI2)
|
||||||
|
* RPA3 SO PGA117 and SST25VF032B R0, SPI2 data IN (SDI2)
|
||||||
* SCK2 SCK PGA117 and SST25VF032B SPI2 clock
|
* SCK2 SCK PGA117 and SST25VF032B SPI2 clock
|
||||||
*
|
*
|
||||||
* RB7 ~CSAI PGA117 PGA117 chip select (active low)
|
* RB7 ~CSAI PGA117 PGA117 chip select (active low)
|
||||||
@ -82,8 +83,12 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#define GPIO_SI (GPIO_OUTPUT|GPIO_PORTA|GPIO_PIN1)
|
#define GPIO_SI (GPIO_OUTPUT|GPIO_PORTA|GPIO_PIN1)
|
||||||
#define GPIO_SO (GPIO_INPUT|GPIO_PORTA|GPIO_PIN1)
|
#ifdef CONFIG_MIRTOO_RELEASE == 1
|
||||||
#define GPIO_SCK (GPIO_OUTPUT|GPIO_PORTA|GPIO_PIN1)
|
# define GPIO_SO (GPIO_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||||
|
#else
|
||||||
|
# define GPIO_SO (GPIO_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||||
|
#endif
|
||||||
|
#define GPIO_SCK (GPIO_OUTPUT|GPIO_PORTB|GPIO_PIN15)
|
||||||
|
|
||||||
#define GPIO_PGA117_CS (GPIO_OUTPUT|GPIO_VALUE_ONE|GPIO_PORTB|GPIO_PIN7)
|
#define GPIO_PGA117_CS (GPIO_OUTPUT|GPIO_VALUE_ONE|GPIO_PORTB|GPIO_PIN7)
|
||||||
#define GPIO_SST25VF032B_CS (GPIO_OUTPUT|GPIO_VALUE_ONE|GPIO_PORTB|GPIO_PIN13)
|
#define GPIO_SST25VF032B_CS (GPIO_OUTPUT|GPIO_VALUE_ONE|GPIO_PORTB|GPIO_PIN13)
|
||||||
|
Loading…
Reference in New Issue
Block a user