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XMC4xxxx: Final clean-up of SCU heder file

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This commit is contained in:
Gregory Nutt 2017-03-18 16:41:33 -06:00
parent e82a3b3ca7
commit 47cd105e32
1 changed files with 190 additions and 211 deletions
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93
arch/arm/src/xmc4/chip/xmc4_scu.h
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@ -79,14 +79,11 @@
#define XMC4_SCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */
#define XMC4_SCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */
#define XMC4_SCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */
#define XMC4_SCU_SDMMCCON_OFFSET 0x00b4 /* SDMMC Configuration */
#define XMC4_SCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */
#define XMC4_SCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */
#define XMC4_SCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */
/* Ethernet Control SCU Resters */
#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */
/* Interrupt Control SCU Registers */
#define XMC4_SCU_SRSTAT_OFFSET 0x0000 /* Service Request Status */
@ -96,10 +93,6 @@
#define XMC4_SCU_SRSET_OFFSET 0x0010 /* Service Request Set */
#define XMC4_SCU_NMIREQEN_OFFSET 0x0014 /* Enable Promoting Events to NMI Request */
/* SDMMC Control SCU Registers */
#define XMC4_SCU_SDMMCCON_OFFSET 0x0000 /* SDMMC Configuration */
/* Parity Control Registers */
#define XMC4_SCU_PEEN_OFFSET 0x0000 /* Parity Error Enable Register */
@ -215,14 +208,11 @@
#define XMC4_SCU_SDMMCDEL (XMC4_SCU_GENERAL_BASE+XMC4_SCU_SDMMCDEL_OFFSET)
#define XMC4_SCU_G0ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G0ORCEN_OFFSET)
#define XMC4_SCU_G1ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G1ORCEN_OFFSET)
#define XMC4_SCU_SDMMCCON (XMC4_SDMMC_CON_BASE+XMC4_SCU_SDMMCCON_OFFSET)
#define XMC4_SCU_MIRRSTS (XMC4_SCU_GENERAL_BASE+XMC4_SCU_MIRRSTS_OFFSET)
#define XMC4_SCU_RMACR (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMACR_OFFSET)
#define XMC4_SCU_RMADATA (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMADATA_OFFSET)
/* Ethernet Control SCU Registers */
#define XMC4_SCU_ETHCON (XMC4_ETH0_CON_BASE+XMC4_SCU_ETHCON_OFFSET)
/* Parity Control Registers */
#define XMC4_SCU_PEEN (XMC4_SCU_PARITY_BASE+XMC4_SCU_PEEN_OFFSET)
@ -241,11 +231,6 @@
#define XMC4_SCU_TRAPCLR (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPCLR_OFFSET)
#define XMC4_SCU_TRAPSET (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPSET_OFFSET)
/* Ethernet Control SCU Resters */
#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */
#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */
/* Interrupt Control SCU Registers */
#define XMC4_SCU_SRSTAT (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSTAT_OFFSET)
@ -255,10 +240,6 @@
#define XMC4_SCU_SRSET (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSET_OFFSET)
#define XMC4_SCU_NMIREQEN (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_NMIREQEN_OFFSET)
/* SDMMC Control SCU Registers */
#define XMC4_SCU_SDMMCCON (XMC4_SDMMC_CON_BASE+XMC4_SCU_SDMMCCON_OFFSET)
/* Power control SCU Registers */
#define XMC4_SCU_PWRSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRSTAT_OFFSET)
@ -500,6 +481,13 @@
#define SCU_GORCEN_ENORC6 (1 << 6) /* Bit 6: Enable Out of Range Comparator, Channel 6 */
#define SCU_GORCEN_ENORC7 (1 << 7) /* Bit 7: Enable Out of Range Comparator, Channel 7 */
/* SDMMC Configuration */
#define SCU_SDMMCCON_WPSEL (1 << 0) /* Bit 0: SDMMC Write Protection Input Multiplexer Control */
#define SCU_SDMMCCON_WPSVAL (1 << 4) /* Bit 4: SDMMC Write Protect Software Control */
#define SCU_SDMMCCON_CDSEL (1 << 16) /* Bit 16: SDMMC Card Detection Control */
#define SCU_SDMMCCON_CDSVAL (1 << 20) /* Bit 20: SDMMC Write Protect Software Control */
/* Mirror Update Status Register */
#define SCU_MIRRSTS_HDCLR (1 << 1) /* Bit 1: HDCLR Mirror Register Write Status */
@ -517,11 +505,6 @@
#define SCU_MIRRSTS_RTC_MSKSR (1 << 14) /* Bit 14: RTC MSKSSR Mirror Register Write Status */
#define SCU_MIRRSTS_RTC_CLRSR (1 << 15) /* Bit 15: RTC CLRSR Mirror Register Write Status */
/* Ethernet Control SCU Resters */
/* Ethernet 0 Port Control Register */
#define SCU_ETHCON_
/* Interrupt Control SCU Registers */
/* Service Request Status, RAW Service Request Status, Service Request Mask, Service
@ -565,11 +548,6 @@
/* Retention Memory Access Data Register (32-bit data) */
/* SDMMC Control SCU Registers */
/* SDMMC Configuration */
#define SCU_SDMMCCON_
/* Parity Control Registers */
/* Parity Error Enable Register */
@ -981,41 +959,42 @@
/* Peripheral 0 Clock Gating Status, Peripheral 0 Clock Gating Set, Peripheral 0 Clock Gating Clear */
#define SCU_CGAT0_VADC (1 << 0) /* Bit 0: */
#define SCU_CGAT0_DSD (1 << 1) /* Bit 1: */
#define SCU_CGAT0_CCU40 (1 << 2) /* Bit 2: */
#define SCU_CGAT0_CCU41 (1 << 3) /* Bit 3: */
#define SCU_CGAT0_CCU42 (1 << 4) /* Bit 4: */
#define SCU_CGAT0_CCU80 (1 << 7) /* Bit 7: */
#define SCU_CGAT0_CCU81 (1 << 8) /* Bit 8: */
#define SCU_CGAT0_POSIF0 (1 << 9) /* Bit 9: */
#define SCU_CGAT0_POSIF1 (1 << 10) /* Bit 10: */
#define SCU_CGAT0_USIC0 (1 << 11) /* Bit 11: */
#define SCU_CGAT0_ERU1_ (1 << 16) /* Bit 16: */
#define SCU_CGAT0_VADC (1 << 0) /* Bit 0: VADC Gating Status */
#define SCU_CGAT0_DSD (1 << 1) /* Bit 1: DSD Gating Status */
#define SCU_CGAT0_CCU40 (1 << 2) /* Bit 2: CCU40 Gating Status */
#define SCU_CGAT0_CCU41 (1 << 3) /* Bit 3: CCU41 Gating Status */
#define SCU_CGAT0_CCU42 (1 << 4) /* Bit 4: CCU42 Gating Status */
#define SCU_CGAT0_CCU80 (1 << 7) /* Bit 7: CCU80 Gating Status */
#define SCU_CGAT0_CCU81 (1 << 8) /* Bit 8: CCU81 Gating Status */
#define SCU_CGAT0_POSIF0 (1 << 9) /* Bit 9: POSIF0 Gating Status */
#define SCU_CGAT0_POSIF1 (1 << 10) /* Bit 10: POSIF1 Gating Status */
#define SCU_CGAT0_USIC0 (1 << 11) /* Bit 11: USIC0 Gating Status */
#define SCU_CGAT0_ERU1_ (1 << 16) /* Bit 16: ERU1 Gating Status */
/* Peripheral 1 Clock Gating Status, Peripheral 1 Clock Gating Set, Peripheral 1 Clock Gating Clear */
#define SCU_CGATSTAT1_CCU43 (1 << 0) /* Bit 0: */
#define SCU_CGATSTAT1_LEDTSCU0 (1 << 3) /* Bit 3: */
#define SCU_CGATSTAT1_MCAN0 (1 << 4) /* Bit 4: */
#define SCU_CGATSTAT1_DAC (1 << 5) /* Bit 5: */
#define SCU_CGATSTAT1_MMCI (1 << 6) /* Bit 6: */
#define SCU_CGATSTAT1_USIC1 (1 << 7) /* Bit 7: */
#define SCU_CGATSTAT1_USIC2 (1 << 8) /* Bit 8: */
#define SCU_CGATSTAT1_PPORTS (1 << 9) /* Bit 9: */
#define SCU_CGATSTAT1_CCU43 (1 << 0) /* Bit 0: CCU43 Gating Status */
#define SCU_CGATSTAT1_LEDTSCU0 (1 << 3) /* Bit 3: LEDTS Gating Status */
#define SCU_CGATSTAT1_MCAN0 (1 << 4) /* Bit 4: MultiCAN Gating Status */
#define SCU_CGATSTAT1_DAC (1 << 5) /* Bit 5: DAC Gating Status */
#define SCU_CGATSTAT1_MMCI (1 << 6) /* Bit 6: MMC Interface Gating Status */
#define SCU_CGATSTAT1_USIC1 (1 << 7) /* Bit 7: USIC1 Gating Status */
#define SCU_CGATSTAT1_USIC2 (1 << 8) /* Bit 8: USIC1 Gating Status */
#define SCU_CGATSTAT1_PPORTS (1 << 9) /* Bit 9: PORTS Gating Status */
/* Peripheral 2 Clock Gating Status, Peripheral 2 Clock Gating Set, Peripheral 2 Clock Gating Clear */
#define SCU_CGATSTAT2_WDT (1 << 1) /* Bit 1: */
#define SCU_CGATSTAT2_ETH0 (1 << 2) /* Bit 2: */
#define SCU_CGATSTAT2_DMA0 (1 << 4) /* Bit 4: */
#define SCU_CGATSTAT2_DMA1 (1 << 5) /* Bit 5: */
#define SCU_CGATSTAT2_FCE (1 << 6) /* Bit 6: */
#define SCU_CGATSTAT2_USB (1 << 7) /* Bit 7: */
#define SCU_CGATSTAT2_WDT (1 << 1) /* Bit 1: WDT Gating Status */
#define SCU_CGATSTAT2_ETH0 (1 << 2) /* Bit 2: ETH0 Gating Status */
#define SCU_CGATSTAT2_DMA0 (1 << 4) /* Bit 4: DMA0 Gating Status */
#define SCU_CGATSTAT2_DMA1 (1 << 5) /* Bit 5: DMA1 Gating Status */
#define SCU_CGATSTAT2_FCE (1 << 6) /* Bit 6: FCE Gating Status */
#define SCU_CGATSTAT2_USB (1 << 7) /* Bit 7: USB Gating Status */
#define SCU_CGATSTAT2_USB (1 << 10) /* Bit 10: ECAT Gating Status */
/* Peripheral 3 Clock Gating Status, Peripheral 3 Clock Gating Set, Peripheral 3 Clock Gating Clear */
#define SCU_CGATSTAT3_EBU (1 << 2) /* Bit 2: */
#define SCU_CGATSTAT3_EBU (1 << 2) /* Bit 2: EBU Gating Status */
/* Oscillator Control SCU Registers */