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STM32 I2C: Cosmetic changes in preparation to merge a change

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This commit is contained in:
Gregory Nutt 2014-05-13 13:11:10 -06:00
parent c50fc79798
commit 47dad8d7cf
1 changed files with 55 additions and 42 deletions
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29
arch/arm/src/stm32/stm32_i2c.c
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@ -8,7 +8,7 @@
* With extensions, modifications by: * With extensions, modifications by:
* *
* Copyright (C) 2011-2014 Gregory Nutt. All rights reserved. * Copyright (C) 2011-2014 Gregory Nutt. All rights reserved.
* Author: Gregroy Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -57,7 +57,7 @@
* - SMBus support (hardware layer timings are already supported) and add SMBA gpio pin * - SMBus support (hardware layer timings are already supported) and add SMBA gpio pin
* - Slave support with multiple addresses (on multiple instances): * - Slave support with multiple addresses (on multiple instances):
* - 2 x 7-bit address or * - 2 x 7-bit address or
* - 1 x 10 bit adresses + 1 x 7 bit address (?) * - 1 x 10 bit addresses + 1 x 7 bit address (?)
* - plus the broadcast address (general call) * - plus the broadcast address (general call)
* - Multi-master support * - Multi-master support
* - DMA (to get rid of too many CPU wake-ups and interventions) * - DMA (to get rid of too many CPU wake-ups and interventions)
@ -97,6 +97,7 @@
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ #if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \
defined(CONFIG_STM32_I2C3) defined(CONFIG_STM32_I2C3)
/* This implementation is for the STM32 F1, F2, and F4 only */ /* This implementation is for the STM32 F1, F2, and F4 only */
/* Experimentally enabled for STM32L15XX */ /* Experimentally enabled for STM32L15XX */
@ -297,14 +298,17 @@ static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset, uint16_t clearbits, uint8_t offset, uint16_t clearbits,
uint16_t setbits); uint16_t setbits);
static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev); static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev);
#ifdef CONFIG_STM32_I2C_DYNTIMEO #ifdef CONFIG_STM32_I2C_DYNTIMEO
static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs); static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
#endif /* CONFIG_STM32_I2C_DYNTIMEO */ #endif /* CONFIG_STM32_I2C_DYNTIMEO */
static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv); static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_sem_post(FAR struct i2c_dev_s *dev); static inline void stm32_i2c_sem_post(FAR struct i2c_dev_s *dev);
static inline void stm32_i2c_sem_init(FAR struct i2c_dev_s *dev); static inline void stm32_i2c_sem_init(FAR struct i2c_dev_s *dev);
static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev); static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev);
#ifdef CONFIG_I2C_TRACE #ifdef CONFIG_I2C_TRACE
static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv); static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv);
static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status); static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status);
@ -312,17 +316,21 @@ static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
enum stm32_trace_e event, uint32_t parm); enum stm32_trace_e event, uint32_t parm);
static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv); static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
#endif /* CONFIG_I2C_TRACE */ #endif /* CONFIG_I2C_TRACE */
static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
uint32_t frequency); uint32_t frequency);
static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv);
static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv); static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
#ifdef I2C1_FSMC_CONFLICT #ifdef I2C1_FSMC_CONFLICT
static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv); static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_enablefsmc(uint32_t ahbenr); static inline void stm32_i2c_enablefsmc(uint32_t ahbenr);
#endif /* I2C1_FSMC_CONFLICT */ #endif /* I2C1_FSMC_CONFLICT */
static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv); static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
#ifndef CONFIG_I2C_POLLED #ifndef CONFIG_I2C_POLLED
#ifdef CONFIG_STM32_I2C1 #ifdef CONFIG_STM32_I2C1
static int stm32_i2c1_isr(int irq, void *context); static int stm32_i2c1_isr(int irq, void *context);
@ -333,7 +341,8 @@ static int stm32_i2c2_isr(int irq, void *context);
#ifdef CONFIG_STM32_I2C3 #ifdef CONFIG_STM32_I2C3
static int stm32_i2c3_isr(int irq, void *context); static int stm32_i2c3_isr(int irq, void *context);
#endif #endif
#endif #endif /* !CONFIG_I2C_POLLED */
static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv); static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv); static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
static uint32_t stm32_i2c_setfrequency(FAR struct i2c_dev_s *dev, static uint32_t stm32_i2c_setfrequency(FAR struct i2c_dev_s *dev,
@ -344,15 +353,17 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
static int stm32_i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, static int stm32_i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer,
int buflen); int buflen);
static int stm32_i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen); static int stm32_i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen);
#ifdef CONFIG_I2C_WRITEREAD #ifdef CONFIG_I2C_WRITEREAD
static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev, static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev,
const uint8_t *wbuffer, int wbuflen, const uint8_t *wbuffer, int wbuflen,
uint8_t *buffer, int buflen); uint8_t *buffer, int buflen);
#endif #endif /* CONFIG_I2C_WRITEREAD */
#ifdef CONFIG_I2C_TRANSFER #ifdef CONFIG_I2C_TRANSFER
static int stm32_i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, static int stm32_i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs,
int count); int count);
#endif #endif /* CONFIG_I2C_TRANSFER */
/************************************************************************************ /************************************************************************************
* Private Data * Private Data
@ -963,6 +974,7 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
speed = 4; speed = 4;
} }
ccr |= speed; ccr |= speed;
/* Set Maximum Rise Time for standard mode */ /* Set Maximum Rise Time for standard mode */
@ -1000,6 +1012,7 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
speed = 1; speed = 1;
} }
ccr |= speed; ccr |= speed;
/* Set Maximum Rise Time for fast mode */ /* Set Maximum Rise Time for fast mode */
@ -1655,7 +1668,7 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
status = stm32_i2c_getstatus(priv); status = stm32_i2c_getstatus(priv);
errval = ETIMEDOUT; errval = ETIMEDOUT;
i2cdbg("Timed out: CR1: %04x status: %08x\n", i2cdbg("Timed out: CR1: 0x%04x status: 0x%08x\n",
stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status);
/* "Note: When the STOP, START or PEC bit is set, the software must /* "Note: When the STOP, START or PEC bit is set, the software must
@ -1734,7 +1747,7 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
/* This is not an error, but should not happen. The BUSY signal can hang, /* This is not an error, but should not happen. The BUSY signal can hang,
* however, if there are unhealthy devices on the bus that need to be reset. * however, if there are unhealthy devices on the bus that need to be reset.
* NOTE: We will only see this buy indication if stm32_i2c_sem_waitdone() * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone()
* fails above; Otherwise it is cleared. * fails above; Otherwise it is cleared.
*/ */
@ -1884,7 +1897,7 @@ static int stm32_i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *m
FAR struct i2c_dev_s *up_i2cinitialize(int port) FAR struct i2c_dev_s *up_i2cinitialize(int port)
{ {
struct stm32_i2c_priv_s * priv = NULL; /* Private data of device with multiple instances */ struct stm32_i2c_priv_s * priv = NULL; /* Private data of device with multiple instances */
struct stm32_i2c_inst_s * inst = NULL; /* Eevice, single instance */ struct stm32_i2c_inst_s * inst = NULL; /* Device, single instance */
int irqs; int irqs;
#if STM32_PCLK1_FREQUENCY < 4000000 #if STM32_PCLK1_FREQUENCY < 4000000