Merged in extent3d/nuttx (pull request #568)
SAMD External Interrupt Controller (EIC) support * SAMD External Interrupt Controller (EIC) support * removed comment Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Matt Thompson
Gregory Nutt
parent
f7bfa38b94
commit
48355b32dc
@ -86,9 +86,9 @@
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#define SAM_IRQ_NINTS (28) /* Total number of interrupts */
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#define SAM_IRQ_NIRQS (SAM_IRQ_INTERRUPT+28) /* The number of real interrupts */
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/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
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/* EIC interrupts. Up to 16 pins may be configured to support interrupts */
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#ifdef CONFIG_SAMDL_GPIOIRQ
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#ifdef CONFIG_SAMDL_EIC
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# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
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# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
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# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
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@ -572,6 +572,10 @@ config SAMDL_USB
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default n
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depends on SAMDL_HAVE_USB
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config SAMDL_EIC
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bool "External Interrupt Controller"
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default n
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config SAMDL_WDT
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bool "Watchdog Timer"
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default n
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@ -102,3 +102,7 @@ endif
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ifeq ($(CONFIG_SAMDL_USB),y)
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CHIP_CSRCS += sam_usb.c
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endif
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ifeq ($(CONFIG_SAMDL_EIC),y)
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CHIP_CSRCS += sam_eic.c
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endif
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191
arch/arm/src/samdl/chip/samd_eic.h
Normal file
191
arch/arm/src/samdl/chip/samd_eic.h
Normal file
@ -0,0 +1,191 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/samd_eic.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Matt Thompson <matt@extent3d.com>
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*
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* References:
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* "Microchip SAMD21 datasheet"
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_EIC_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_EIC_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* EIC register offsets *********************************************************************/
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#define SAM_EIC_CTRLA_OFFSET 0x0000 /* Control A register */
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#define SAM_EIC_STATUS_OFFSET 0x0001 /* Status register */
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#define SAM_EIC_NMICTRL_OFFSET 0x0002 /* Non-maskable interrupt control register */
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#define SAM_EIC_NMIFLAG_OFFSET 0x0003 /* Non-maskable interrupt flag register */
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#define SAM_EIC_EVCTRL_OFFSET 0x0004 /* Event control register */
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#define SAM_EIC_INTENCLR_OFFSET 0x0008 /* Interrupt enable clear register */
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#define SAM_EIC_INTENSET_OFFSET 0x000c /* Interrupt enable set register */
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#define SAM_EIC_INTFLAG_OFFSET 0x0010 /* Interrupt flag and status clear register */
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#define SAM_EIC_WAKEUP_OFFSET 0x0014 /* Wakeup register */
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#define SAM_EIC_CONFIG0_OFFSET 0x0018 /* Configuration 0 register */
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#define SAM_EIC_CONFIG1_OFFSET 0x001c /* Configuration 1 register */
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#define SAM_EIC_CONFIG2_OFFSET 0x0020 /* Configuration 2 register */
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/* EIC register addresses *******************************************************************/
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#define SAM_EIC_CTRLA (SAM_EIC_BASE+SAM_EIC_CTRLA_OFFSET)
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#define SAM_EIC_STATUS (SAM_EIC_BASE+SAM_EIC_STATUS_OFFSET)
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#define SAM_EIC_NMICTRL (SAM_EIC_BASE+SAM_EIC_NMICTRL_OFFSET)
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#define SAM_EIC_NMIFLAG (SAM_EIC_BASE+SAM_EIC_NMIFLAG_OFFSET)
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#define SAM_EIC_EVCTRL (SAM_EIC_BASE+SAM_EIC_EVCTRL_OFFSET)
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#define SAM_EIC_INTENCLR (SAM_EIC_BASE+SAM_EIC_INTENCLR_OFFSET)
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#define SAM_EIC_INTENSET (SAM_EIC_BASE+SAM_EIC_INTENSET_OFFSET)
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#define SAM_EIC_INTFLAG (SAM_EIC_BASE+SAM_EIC_INTFLAG_OFFSET)
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#define SAM_EIC_WAKEUP (SAM_EIC_BASE+SAM_EIC_WAKEUP_OFFSET)
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#define SAM_EIC_CONFIG0 (SAM_EIC_BASE+SAM_EIC_CONFIG0_OFFSET)
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#define SAM_EIC_CONFIG1 (SAM_EIC_BASE+SAM_EIC_CONFIG1_OFFSET)
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#define SAM_EIC_CONFIG2 (SAM_EIC_BASE+SAM_EIC_CONFIG2_OFFSET)
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/* EIC register bit definitions *************************************************************/
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/* Control A register */
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#define EIC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
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#define EIC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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/* Status register */
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#define EIC_STATUS_SYNCBUSY (1 << 7) /* Bit 7: Syncronization busy */
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/* Non-maskable interrupt control register */
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#define EIC_NMICTRL_NMISENSE_SHIFT (0) /* Bits 0-2: Non-maskable interrupt sense */
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#define EIC_NMICTRL_NMISENSE_MASK (7 << EIC_NVMICTRL_NMISENSE_SHIFT)
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# define EIC_NMICTRL_NMISENSE_NONE (0 << EIC_NVMICTRL_NMISENSE_SHIFT) /* No detection */
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# define EIC_NMICTRL_NMISENSE_RISE (1 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Rising edge detection */
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# define EIC_NMICTRL_NMISENSE_FALL (2 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Falling edge detection */
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# define EIC_NMICTRL_NMISENSE_BOTH (3 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Both edge detection */
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# define EIC_NMICTRL_NMISENSE_HIGH (4 << EIC_NVMICTRL_NMISENSE_SHIFT) /* High level detection */
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# define EIC_NMICTRL_NMISENSE_LOW (5 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Low level detection */
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#define EIC_NMICTRL_NMIFLTEN (1 << 3) /* Bit 3: Non-maskable interrupt filter enable */
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/* Non-maskable interrupt flas status and clear register */
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#define EIC_NMIFLAG_NMI (1 << 0) /* Non-maskable interrupt */
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/* Event control, Interrupt enable clear, interrupt enable set register, interrupt flag
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* status and clear, and external interrupt wakeup registers.
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*/
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#define EIC_EXTINT_SHIFT (0) /* Bits 0-15: External interrupt n */
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#define EIC_EXTINT_MASK (0x3ffff << EIC_EXTINT_SHIFT)
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//# define EIC_EXTINT(n) ((uint32_t)(n) << EIC_EXTINT_SHIFT)
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# define EIC_EXTINT(n) (1 << (n))
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# define EIC_EXTINT_0 (1 << 0) /* Bit 0: External interrupt 0 */
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# define EIC_EXTINT_1 (1 << 1) /* Bit 1: External interrupt 1 */
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# define EIC_EXTINT_2 (1 << 2) /* Bit 2: External interrupt 2 */
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# define EIC_EXTINT_3 (1 << 3) /* Bit 3: External interrupt 3 */
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# define EIC_EXTINT_4 (1 << 4) /* Bit 4: External interrupt 4 */
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# define EIC_EXTINT_5 (1 << 5) /* Bit 5: External interrupt 5 */
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# define EIC_EXTINT_6 (1 << 6) /* Bit 6: External interrupt 6 */
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# define EIC_EXTINT_7 (1 << 7) /* Bit 7: External interrupt 7 */
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# define EIC_EXTINT_8 (1 << 8) /* Bit 8: External interrupt 8 */
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# define EIC_EXTINT_9 (1 << 9) /* Bit 9: External interrupt 9 */
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# define EIC_EXTINT_10 (1 << 10) /* Bit 10: External interrupt 10 */
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# define EIC_EXTINT_11 (1 << 11) /* Bit 11: External interrupt 11 */
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# define EIC_EXTINT_12 (1 << 12) /* Bit 12: External interrupt 12 */
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# define EIC_EXTINT_13 (1 << 13) /* Bit 13: External interrupt 13 */
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# define EIC_EXTINT_14 (1 << 14) /* Bit 14: External interrupt 14 */
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# define EIC_EXTINT_15 (1 << 15) /* Bit 15: External interrupt 15 */
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# define EIC_EXTINT_16 (1 << 16) /* Bit 16: External interrupt 16 */
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# define EIC_EXTINT_17 (1 << 17) /* Bit 17: External interrupt 17 */
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#define EIC_EXTINT_ALL EIC_EXTINT_MASK
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/* Configuration 0 register */
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#define EIC_CONFIG0_FILTEN(n) (0x8 << ((n) << 2)) /* Filter n enable, n=0-7 */
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#define EIC_CONFIG0_SENSE_SHIFT(n) ((n) << 2) /* Filter n input sense, n=0-7 */
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#define EIC_CONFIG0_SENSE_MASK(n) (7 << EIC_CONFIG0_SENSE_SHIFT(n))
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# define EIC_CONFIG0_SENSE_NONE(n) (0 << EIC_CONFIG0_SENSE_SHIFT(n)) /* No detection */
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# define EIC_CONFIG0_SENSE_RISE(n) (1 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Rising edge detection */
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# define EIC_CONFIG0_SENSE_FALL(n) (2 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Falling edge detection */
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# define EIC_CONFIG0_SENSE_BOTH(n) (3 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Both edge detection */
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# define EIC_CONFIG0_SENSE_HIGH(n) (4 << EIC_CONFIG0_SENSE_SHIFT(n)) /* High level detection */
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# define EIC_CONFIG0_SENSE_LOW(n) (5 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Low level detection */
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/* Configuration 1 register */
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#define EIC_CONFIG1_FILTEN(n) (0x8 << (((n) - 8) << 2)) /* Filter n enable, n=8-15 */
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#define EIC_CONFIG1_SENSE_SHIFT(n) (((n) - 8) << 2) /* Filter n input sense, n=8-17 */
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#define EIC_CONFIG1_SENSE_MASK(n) (7 << EIC_CONFIG1_SENSE_SHIFT(n))
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# define EIC_CONFIG1_SENSE_NONE(n) (0 << EIC_CONFIG1_SENSE_SHIFT(n)) /* No detection */
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# define EIC_CONFIG1_SENSE_RISE(n) (1 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Rising edge detection */
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# define EIC_CONFIG1_SENSE_FALL(n) (2 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Falling edge detection */
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# define EIC_CONFIG1_SENSE_BOTH(n) (3 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Both edge detection */
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# define EIC_CONFIG1_SENSE_HIGH(n) (4 << EIC_CONFIG1_SENSE_SHIFT(n)) /* High level detection */
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# define EIC_CONFIG1_SENSE_LOW(n) (5 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Low level detection */
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/* Configuration 2 register */
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#define EIC_CONFIG2_FILTEN(n) (0x8 << (((n) - 16) << 2)) /* Filter n enable, n=16-23 */
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#define EIC_CONFIG2_SENSE_SHIFT(n) (((n) - 16) << 2) /* Filter n input sense, n=16-23 */
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#define EIC_CONFIG2_SENSE_MASK(n) (7 << EIC_CONFIG2_SENSE_SHIFT(n))
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# define EIC_CONFIG2_SENSE_NONE(n) (0 << EIC_CONFIG2_SENSE_SHIFT(n)) /* No detection */
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# define EIC_CONFIG2_SENSE_RISE(n) (1 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Rising edge detection */
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# define EIC_CONFIG2_SENSE_FALL(n) (2 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Falling edge detection */
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# define EIC_CONFIG2_SENSE_BOTH(n) (3 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Both edge detection */
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# define EIC_CONFIG2_SENSE_HIGH(n) (4 << EIC_CONFIG2_SENSE_SHIFT(n)) /* High level detection */
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# define EIC_CONFIG2_SENSE_LOW(n) (5 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Low level detection */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_EIC_H */
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211
arch/arm/src/samdl/sam_eic.c
Normal file
211
arch/arm/src/samdl/sam_eic.c
Normal file
@ -0,0 +1,211 @@
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/****************************************************************************
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* arch/arm/src/samdl/sam_eic.c
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Matt Thompson <matt@extent3d.com>
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*
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* References:
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* 1. "Microchip SAM D21E / SAM D21G / SAM D21J Datasheet"
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
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* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <assert.h>
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#include "up_arch.h"
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#include "sam_config.h"
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#include "sam_pm.h"
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#include "sam_gclk.h"
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#include "sam_periphclks.h"
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#include "sam_eic.h"
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#include "sam_port.h"
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include <arch/board/board.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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static int sam_eic_isr(int irq, FAR void *context, FAR void *arg)
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{
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uint32_t intflag;
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int bit;
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/* Get the pending interrupt flag register */
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intflag = getreg32(SAM_EIC_INTFLAG);
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/* Dispatch the IRQ to the SAM_IRQ_EXTINTn handlers */
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for(bit=0;bit<SAM_IRQ_NEXTINTS;bit++)
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{
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if(intflag >> bit & 0x1)
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{
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irq_dispatch(SAM_IRQ_EXTINT0 + bit, context);
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}
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}
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/* Clear the pending interrupt flags */
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putreg32(EIC_EXTINT_ALL, SAM_EIC_INTFLAG);
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return 0;
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}
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static void sam_eic_syncwait(void)
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{
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while ((getreg8(SAM_EIC_STATUS) & EIC_STATUS_SYNCBUSY) != 0);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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void sam_eic_dumpregs(void)
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{
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irqinfo("EIC:\n");
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irqinfo(" CTRLA: %02x\n", getreg8(SAM_EIC_CTRLA));
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irqinfo(" STATUS: %02x\n", getreg8(SAM_EIC_STATUS));
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irqinfo(" NMICTRL: %02x\n", getreg8(SAM_EIC_NMICTRL));
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irqinfo(" NMIFLAG: %02x\n", getreg8(SAM_EIC_NMIFLAG));
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irqinfo(" EVCTRL: %08x\n", getreg32(SAM_EIC_EVCTRL));
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irqinfo(" INTENCLR: %08x\n", getreg32(SAM_EIC_INTENCLR));
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irqinfo(" INTENSET: %08x\n", getreg32(SAM_EIC_INTENSET));
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irqinfo(" INTFLAG: %08x\n", getreg32(SAM_EIC_INTFLAG));
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irqinfo(" WAKEUP: %08x\n", getreg32(SAM_EIC_WAKEUP));
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irqinfo(" CONFIG0: %08x\n", getreg32(SAM_EIC_CONFIG0));
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irqinfo(" CONFIG1: %08x\n", getreg32(SAM_EIC_CONFIG1));
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irqinfo(" CONFIG2: %08x\n", getreg32(SAM_EIC_CONFIG2));
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}
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/****************************************************************************
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* Name: sam_eic_initialize
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*
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* Description:
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* Configure the external interrupt controller.
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*
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****************************************************************************/
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int sam_eic_initialize(uint8_t gclkgen)
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{
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uint16_t regval;
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sam_eic_enableperiph();
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regval = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN(gclkgen) | GCLK_CLKCTRL_CLKEN;
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putreg16(regval, SAM_GCLK_CLKCTRL);
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putreg8(EIC_CTRLA_ENABLE, SAM_EIC_CTRLA);
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sam_eic_syncwait();
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irq_attach(SAM_IRQ_EIC, sam_eic_isr, NULL);
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sam_eic_dumpregs();
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up_enable_irq(SAM_IRQ_EIC);
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return OK;
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}
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|
||||
int sam_eic_irq_enable(int irq)
|
||||
{
|
||||
uint32_t config;
|
||||
int eirq = irq - SAM_IRQ_EXTINT0;
|
||||
|
||||
config = getreg32(SAM_EIC_CONFIG0);
|
||||
config |= EIC_CONFIG0_FILTEN(eirq) | EIC_CONFIG0_SENSE_FALL(eirq);
|
||||
putreg32(config, SAM_EIC_CONFIG0);
|
||||
|
||||
putreg32(EIC_EXTINT(eirq), SAM_EIC_INTENSET);
|
||||
sam_eic_dumpregs();
|
||||
return OK;
|
||||
}
|
||||
|
||||
int sam_eic_config(uint8_t eirq, port_pinset_t pinset)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t val;
|
||||
uint32_t config;
|
||||
|
||||
/* Determine which of the CONFIG[0:2] registers to write to */
|
||||
|
||||
if(eirq < 8)
|
||||
{
|
||||
reg = SAM_EIC_CONFIG0;
|
||||
|
||||
val = EIC_CONFIG0_SENSE_BOTH(eirq);
|
||||
if(pinset & PORT_INT_RISING)
|
||||
val = EIC_CONFIG0_SENSE_RISE(eirq);
|
||||
if(pinset & PORT_INT_FALLING)
|
||||
val = EIC_CONFIG0_SENSE_FALL(eirq);
|
||||
val |= EIC_CONFIG0_FILTEN(eirq);
|
||||
}
|
||||
else if(eirq < 16)
|
||||
{
|
||||
reg = SAM_EIC_CONFIG1;
|
||||
val = EIC_CONFIG1_FILTEN(eirq) | EIC_CONFIG1_SENSE_FALL(eirq);
|
||||
}
|
||||
else
|
||||
{
|
||||
reg = SAM_EIC_CONFIG2;
|
||||
val = EIC_CONFIG2_FILTEN(eirq) | EIC_CONFIG2_SENSE_FALL(eirq);
|
||||
}
|
||||
|
||||
/* Write the new config to the CONFIGn register */
|
||||
|
||||
config = getreg32(reg);
|
||||
config |= val;
|
||||
putreg32(config, reg);
|
||||
|
||||
/* Enable interrupt generation for this pin */
|
||||
|
||||
putreg32(EIC_EXTINT(eirq), SAM_EIC_INTENSET);
|
||||
|
||||
sam_eic_dumpregs();
|
||||
|
||||
return OK;
|
||||
}
|
||||
109
arch/arm/src/samdl/sam_eic.h
Normal file
109
arch/arm/src/samdl/sam_eic.h
Normal file
@ -0,0 +1,109 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/samdl/sam_eic.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Matt Thompson <matt@extent3d.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMDL_SAM_EIC_H
|
||||
#define __ARCH_ARM_SRC_SAMDL_SAM_EIC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "sam_config.h"
|
||||
#include "sam_port.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
|
||||
# include "chip/samd_eic.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
|
||||
# include "chip/saml_eic.h"
|
||||
#else
|
||||
# error Unrecognized SAMD/L architecture
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_eic_configure
|
||||
*
|
||||
* Description:
|
||||
* Configure the EIC
|
||||
*
|
||||
* Input Parameters:
|
||||
* gclkgen - GCLK Generator
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int sam_eic_initialize(uint8_t gclkgen);
|
||||
int sam_eic_config(uint8_t eirq, port_pinset_t pinset);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_SAM_EIC_H */
|
||||
@ -57,6 +57,7 @@
|
||||
|
||||
#include "chip.h"
|
||||
#include "sam_port.h"
|
||||
#include "sam_eic.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
@ -189,7 +190,27 @@ static inline void sam_configinput(uintptr_t base, port_pinset_t pinset)
|
||||
|
||||
static inline void sam_configinterrupt(uintptr_t base, port_pinset_t pinset)
|
||||
{
|
||||
#warning Missing logic
|
||||
uint32_t func;
|
||||
uint32_t regval;
|
||||
int pin;
|
||||
|
||||
pin = (pinset & PORT_PIN_MASK) >> PORT_PIN_SHIFT;
|
||||
|
||||
regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_PMUXEN | PORT_WRCONFIG_INEN);
|
||||
regval |= PORT_WRCONFIG_PINMASK(pin);
|
||||
|
||||
func = (pinset & PORT_FUNC_MASK) >> PORT_FUNC_SHIFT;
|
||||
regval |= (func << PORT_WRCONFIG_PMUX_SHIFT);
|
||||
|
||||
putreg32(regval, base + SAM_PORT_WRCONFIG_OFFSET);
|
||||
|
||||
/* Configure the interrupt edge sensitivity in CONFIGn register of the EIC */
|
||||
|
||||
sam_eic_config(pin, pinset);
|
||||
|
||||
#ifdef CONFIG_DEBUG_GPIO_INFO
|
||||
sam_dumpport(pinset, "extint");
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -531,7 +552,7 @@ int sam_dumpport(uint32_t pinset, const char *msg)
|
||||
|
||||
/* Get the base address associated with the PIO port */
|
||||
|
||||
pin = sam_portpin(pinset);
|
||||
pin = (pinset & PORT_PIN_MASK) >> PORT_PIN_SHIFT;
|
||||
port = (pinset & PORT_MASK) >> PORT_SHIFT;
|
||||
base = SAM_PORTN_BASE(port);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user