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SAM3/4: Integrate the SPI DMA interface with the existing code. Does not yet work.

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This commit is contained in:
Gregory Nutt 2014-03-13 15:54:09 -06:00
parent d32b85a938
commit 483fcdca03
8 changed files with 154 additions and 80 deletions
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68
arch/arm/include/sam34/chip.h
View File

@ -90,6 +90,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -110,6 +111,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -130,6 +132,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -150,6 +153,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -170,6 +174,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -190,6 +195,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -235,6 +241,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 6 /* 6 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -255,6 +262,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -275,6 +283,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 6 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -295,6 +304,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 15 /* 15 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -315,6 +325,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 15 /* 15 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -335,6 +346,7 @@
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 15 /* 15 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -404,7 +416,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 16 /* 16 PDC Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM34_NSLCD 1 /* 1 segment LCD interface */
# define SAM34_NAESA 1 /* 1 advanced encryption standard */
@ -425,7 +438,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 16 /* 16 PDC Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM34_NSLCD 1 /* 1 segment LCD interface */
# define SAM34_NAESA 1 /* 1 advanced encryption standard */
@ -446,7 +460,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 16 /* 16 PDC Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -467,7 +482,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 16 /* 16 PDC Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -505,7 +521,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -524,7 +541,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -543,7 +561,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -562,7 +581,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -581,7 +601,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -600,7 +621,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -619,7 +641,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -638,7 +661,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -657,7 +681,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -676,7 +701,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -700,7 +726,7 @@
* CAN 2 2 1 1
* EBI Yes Yes No No
* EBI data 8 8 --- ---
* EBI ch 4 4 --- ---
* EBI ch 4 4 --- ---
* EBI addr 24 24 --- ---
* SDRAM --- --- --- ---
* DMA 4 4 4 4
@ -725,7 +751,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 24 /* 24 PDC Channels */
# define SAM34_NDMACHAN 4 /* 4 DMAC Channels */
# define SAM34_NPDCCHAN 24 /* 24 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -744,7 +771,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 24 /* 24 PDC Channels */
# define SAM34_NDMACHAN 4 /* 4 DMAC Channels */
# define SAM34_NPDCCHAN 24 /* 24 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -763,7 +791,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 21 /* 21 PDC Channels */
# define SAM34_NDMACHAN 4 /* 4 DMAC Channels */
# define SAM34_NPDCCHAN 21 /* 21 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
@ -782,7 +811,8 @@
/* Peripherals */
# define SAM34_NDMACHAN 21 /* 21 PDC Channels */
# define SAM34_NDMACHAN 4 /* 4 DMAC Channels */
# define SAM34_NPDCCHAN 21 /* 21 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */

2
arch/arm/src/sam34/Kconfig
View File

@ -339,7 +339,7 @@ config SAM34_EIC
default n
depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4E
config SAM34_DMAC
config SAM34_DMAC0
bool "DMA controller (DMAC)"
default n
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E

2
arch/arm/src/sam34/Make.defs
View File

@ -96,7 +96,7 @@ ifeq ($(CONFIG_SAM34_CMCC),y)
CHIP_CSRCS += sam_cmcc.c
endif
ifeq ($(CONFIG_SAM34_DMAC),y)
ifeq ($(CONFIG_SAM34_DMAC0),y)
CHIP_CSRCS += sam_dmac.c
endif

32
arch/arm/src/sam34/chip/sam_dmac.h
View File

@ -1,6 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_dmac.h
* DMA Controller (DMAC) definitions for the SAM3U, SAM3X, SAM3A, and RCH_CHIP_SAM4E
* DMA Controller (DMAC) definitions for the SAM3U, SAM3X, SAM3A, and SAM4E
*
* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -456,28 +456,26 @@
# define DMAC_WPSR_WPVSRC_MASK (0xffff << DMAC_WPSR_WPVSRC_SHIFT)
#endif
/* DMA Peripheral IDs *******************************************************************/
/* DMA Hardware interface numbers *******************************************************/
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define DMACHAN_PID_MCI0 0
# define DMACHAN_PID_SSC 3
# define DMACHAN_PID_MCI1 13
# define DMACHAN_INTF_MCI0 0
# define DMACHAN_INTF_SSC 3
# define DMACHAN_INTF_MCI1 13
#endif
/* Hardware interface numbers */
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define DMAC_INTF_HSMCI 0 /* HSMCI Transmit/Receive */
# define DMAC_INTF_SPI0TX 1 /* SPI Transmit */
# define DMAC_INTF_SPI0RX 2 /* SPI Receive */
# define DMAC_INTF_USART0TX 3 /* USART0 Transmit */
# define DMAC_INTF_USART0RX 4 /* USART0 Receive */
# define DMAC_INTF_USART1TX 5 /* USART1 Transmit */
# define DMAC_INTF_USART1RX 6 /* USART1 Receive */
# define DMAC_INTF_AESTX 11 /* AES Transmit */
# define DMAC_INTF_AESRX 12 /* AES Receive */
# define DMAC_INTF_PWMTX 13 /* PWM Transmit */
# define DMACHAN_INTF_HSMCI 0 /* HSMCI Transmit/Receive */
# define DMACHAN_INTF_SPI0TX 1 /* SPI Transmit */
# define DMACHAN_INTF_SPI0RX 2 /* SPI Receive */
# define DMACHAN_INTF_USART0TX 3 /* USART0 Transmit */
# define DMACHAN_INTF_USART0RX 4 /* USART0 Receive */
# define DMACHAN_INTF_USART1TX 5 /* USART1 Transmit */
# define DMACHAN_INTF_USART1RX 6 /* USART1 Receive */
# define DMACHAN_INTF_AESTX 11 /* AES Transmit */
# define DMACHAN_INTF_AESRX 12 /* AES Receive */
# define DMACHAN_INTF_PWMTX 13 /* PWM Transmit */
#endif
/****************************************************************************************

54
arch/arm/src/sam34/sam_dmac.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/sam34/sam_dmac.c
*
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2010, 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -68,7 +68,7 @@
/* Condition out the whole file unless DMA is selected in the configuration */
#ifdef CONFIG_SAM34_DMAC
#ifdef CONFIG_SAM34_DMAC0
/* If AT90SAM3U support is enabled, then OS DMA support should also be enabled */
@ -153,7 +153,7 @@ static struct dma_linklist_s g_linklist[CONFIG_SAM34_NLLDESC];
static struct sam_dma_s g_dma[SAM34_NDMACHAN] =
{
#ifdef CONFIG_ARCH_CHIP_ATSAM3U4E
#if defined(CONFIG_ARCH_CHIP_ATSAM3U4E)
/* the AT91SAM3U4E has four DMA channels. The FIFOs for channels 0-2 are
* 8 bytes in size; channel 3 is 32 bytes.
*/
@ -182,6 +182,40 @@ static struct sam_dma_s g_dma[SAM34_NDMACHAN] =
.flags = (DMACH_FLAG_FIFO_32BYTES | DMACH_FLAG_FLOWCONTROL),
.base = SAM_DMACHAN3_BASE,
}
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
/* The SAM4E16E, SAM4E8E, SAM4E16C, and SAM4E8C have four DMA channels.
*
* REVISIT: I have not yet found any documentation for the per-channel
* FIFO depth. Here I am assuming that the FIFO characteristics are
* the same as for the SAM3U.
*/
#if SAM34_NDMACHAN != 4
# error "Logic here assumes SAM34_NDMACHAN is 4"
#endif
{
.chan = 0,
.flags = DMACH_FLAG_FIFO_8BYTES,
.base = SAM_DMACHAN0_BASE,
},
{
.chan = 1,
.flags = DMACH_FLAG_FIFO_8BYTES,
.base = SAM_DMACHAN1_BASE,
},
{
.chan = 2,
.flags = DMACH_FLAG_FIFO_8BYTES,
.base = SAM_DMACHAN2_BASE,
},
{
.chan = 3,
.flags = (DMACH_FLAG_FIFO_32BYTES | DMACH_FLAG_FLOWCONTROL),
.base = SAM_DMACHAN3_BASE,
}
#else
# error "Nothing is known about the DMA channels for this device"
#endif
@ -369,6 +403,8 @@ sam_txctrlabits(struct sam_dma_s *dmach)
DEBUGASSERT(ndx < 3);
regval = g_srcwidth[ndx];
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
/* Set the source chunk size (memory chunk size) */
if ((dmach->flags & DMACH_FLAG_MEMCHUNKSIZE) == DMACH_FLAG_MEMCHUNKSIZE_4)
@ -380,6 +416,7 @@ sam_txctrlabits(struct sam_dma_s *dmach)
{
regval |= DMACHAN_CTRLA_SCSIZE_1;
}
#endif
#endif
/* Since this is a transmit, the destination is described by the peripheral selections.
@ -390,6 +427,8 @@ sam_txctrlabits(struct sam_dma_s *dmach)
DEBUGASSERT(ndx < 3);
regval |= g_destwidth[ndx];
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
/* Set the destination chunk size (peripheral chunk size) */
if ((dmach->flags & DMACH_FLAG_PERIPHCHUNKSIZE) == DMACH_FLAG_PERIPHCHUNKSIZE_4)
@ -401,6 +440,7 @@ sam_txctrlabits(struct sam_dma_s *dmach)
{
regval |= DMACHAN_CTRLA_DCSIZE_1;
}
#endif
#endif
return regval;
@ -514,6 +554,8 @@ static inline uint32_t sam_rxctrlabits(struct sam_dma_s *dmach)
DEBUGASSERT(ndx < 3);
regval = g_srcwidth[ndx];
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
/* Set the source chunk size (peripheral chunk size) */
if ((dmach->flags & DMACH_FLAG_PERIPHCHUNKSIZE) == DMACH_FLAG_PERIPHCHUNKSIZE_4)
@ -525,6 +567,7 @@ static inline uint32_t sam_rxctrlabits(struct sam_dma_s *dmach)
{
regval |= DMACHAN_CTRLA_SCSIZE_1;
}
#endif
#endif
/* Since this is a receive, the destination is described by the memory selections.
@ -535,6 +578,8 @@ static inline uint32_t sam_rxctrlabits(struct sam_dma_s *dmach)
DEBUGASSERT(ndx < 3);
regval |= g_destwidth[ndx];
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
/* Set the destination chunk size (memory chunk size) */
if ((dmach->flags & DMACH_FLAG_MEMCHUNKSIZE) == DMACH_FLAG_MEMCHUNKSIZE_4)
@ -546,6 +591,7 @@ static inline uint32_t sam_rxctrlabits(struct sam_dma_s *dmach)
{
regval |= DMACHAN_CTRLA_DCSIZE_1;
}
#endif
#endif
return regval;
@ -1715,4 +1761,4 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
dmadbg(" CFG[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CFG_OFFSET, regs->cfg);
}
#endif /* CONFIG_DEBUG_DMA */
#endif /* CONFIG_SAM34_DMAC */
#endif /* CONFIG_SAM34_DMAC0 */

6
arch/arm/src/sam34/sam_hsmci.c
View File

@ -77,8 +77,8 @@
/* Configuration ************************************************************/
#ifndef CONFIG_SAM34_DMAC
# warning "HSMCI driver requires CONFIG_SAM34_DMAC"
#ifndef CONFIG_SAM34_DMAC0
# warning "HSMCI driver requires CONFIG_SAM34_DMAC0"
#endif
#ifndef CONFIG_SCHED_WORKQUEUE
@ -125,7 +125,7 @@
#define DMA_FLAGS \
(DMACH_FLAG_FIFO_8BYTES | DMACH_FLAG_FIFOCFG_LARGEST | \
(DMACHAN_PID_MCI0 << DMACH_FLAG_PERIPHPID_SHIFT) | \
(DMACHAN_INTF_MCI0 << DMACH_FLAG_PERIPHPID_SHIFT) | \
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \
DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
DMACH_FLAG_MEMWIDTH_32BITS | DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_4)

68
arch/arm/src/sam34/sam_spi.c
View File

@ -65,13 +65,14 @@
#include "sam_periphclks.h"
#include "sam_spi.h"
#include "chip/sam_pmc.h"
#include "chip/sam_dmac.h"
#include "chip/sam_spi.h"
#include "chip/sam_pinmap.h"
#if defined(CONFIG_SAM34_SPI0) || defined(CONFIG_SAM34_SPI1)
/****************************************************************************
* Definitions
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* When SPI DMA is enabled, small DMA transfers will still be performed by
@ -217,7 +218,8 @@ struct sam_spidev_s
select_t select; /* SPI select callout */
bool initialized; /* TRUE: Controller has been initialized */
#ifdef CONFIG_SAM34_SPI_DMA
uint8_t pid; /* Peripheral ID */
uint8_t rxintf; /* RX hardware interface number */
uint8_t txintf; /* TX hardware interface number */
#endif
/* Debug stuff */
@ -278,7 +280,7 @@ static void spi_dma_sampledone(struct sam_spics_s *spics);
static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result);
static void spi_txcallback(DMA_HANDLE handle, void *arg, int result);
static inline uintptr_t spi_physregaddr(struct sam_spics_s *spics,
static inline uintptr_t spi_regaddr(struct sam_spics_s *spics,
unsigned int offset);
#endif
@ -348,10 +350,11 @@ static const struct spi_ops_s g_spi0ops =
static struct sam_spidev_s g_spi0dev =
{
.base = SAM_SPI0_BASE,
.select = sam_spi0select,
.base = SAM_SPI0_BASE,
.select = sam_spi0select,
#ifdef CONFIG_SAM34_SPI_DMA
.pid = SAM_PID_SPI0,
.rxintf = DMACHAN_INTF_SPI0RX,
.txintf = DMACHAN_INTF_SPI0TX,
#endif
};
#endif
@ -386,10 +389,11 @@ static const struct spi_ops_s g_spi1ops =
static struct sam_spidev_s g_spi1dev =
{
.base = SAM_SPI1_BASE,
.select = sam_spi1select,
.base = SAM_SPI1_BASE,
.select = sam_spi1select,
#ifdef CONFIG_SAM34_SPI_DMA
.pid = SAM_PID_SPI1,
.rxintf = DMACHAN_INTF_SPI1RX,
.txintf = DMACHAN_INTF_SPI1TX,
#endif
};
#endif
@ -849,19 +853,19 @@ static void spi_txcallback(DMA_HANDLE handle, void *arg, int result)
#endif
/****************************************************************************
* Name: spi_physregaddr
* Name: spi_regaddr
*
* Description:
* Return the physical address of an HSMCI register
* Return the address of an SPI register
*
****************************************************************************/
#ifdef CONFIG_SAM34_SPI_DMA
static inline uintptr_t spi_physregaddr(struct sam_spics_s *spics,
unsigned int offset)
static inline uintptr_t spi_regaddr(struct sam_spics_s *spics,
unsigned int offset)
{
struct sam_spidev_s *spi = spi_device(spics);
return sam_physregaddr(spi->base + offset);
return spi->base + offset;
}
#endif
@ -1399,8 +1403,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
uint32_t txflags;
uint32_t txdummy;
uint32_t rxdummy;
uint32_t paddr;
uint32_t maddr;
uint32_t regaddr;
uint32_t memaddr;
int ret;
/* If we cannot do DMA -OR- if this is a small SPI transfer, then let
@ -1442,13 +1446,11 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
*/
rxflags = DMACH_FLAG_FIFOCFG_LARGEST |
((uint32_t)spi->pid << DMACH_FLAG_PERIPHPID_SHIFT) |
((uint32_t)spi->rxintf << DMACH_FLAG_PERIPHPID_SHIFT) |
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH |
DMACH_FLAG_PERIPHAHB_AHB_IF2 | DMACH_FLAG_PERIPHWIDTH_8BITS |
DMACH_FLAG_PERIPHCHUNKSIZE_1 |
DMACH_FLAG_PERIPHWIDTH_8BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 |
((uint32_t)(0x3f) << DMACH_FLAG_MEMPID_SHIFT) |
DMACH_FLAG_MEMAHB_AHB_IF0 | DMACH_FLAG_MEMWIDTH_8BITS |
DMACH_FLAG_MEMCHUNKSIZE_1;
DMACH_FLAG_MEMWIDTH_8BITS | DMACH_FLAG_MEMCHUNKSIZE_1;
if (!rxbuffer)
{
@ -1466,13 +1468,11 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
}
txflags = DMACH_FLAG_FIFOCFG_LARGEST |
((uint32_t)spi->pid << DMACH_FLAG_PERIPHPID_SHIFT) |
((uint32_t)spi->txintf << DMACH_FLAG_PERIPHPID_SHIFT) |
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH |
DMACH_FLAG_PERIPHAHB_AHB_IF2 | DMACH_FLAG_PERIPHWIDTH_8BITS |
DMACH_FLAG_PERIPHCHUNKSIZE_1 |
DMACH_FLAG_PERIPHWIDTH_8BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 |
((uint32_t)(0x3f) << DMACH_FLAG_MEMPID_SHIFT) |
DMACH_FLAG_MEMAHB_AHB_IF0 | DMACH_FLAG_MEMWIDTH_8BITS |
DMACH_FLAG_MEMCHUNKSIZE_1;
DMACH_FLAG_MEMWIDTH_8BITS | DMACH_FLAG_MEMCHUNKSIZE_1;
if (!txbuffer)
{
@ -1497,10 +1497,10 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Configure the exchange transfers */
paddr = spi_physregaddr(spics, SAM_SPI_RDR_OFFSET);
maddr = sam_physramaddr((uintptr_t)rxbuffer);
regaddr = spi_regaddr(spics, SAM_SPI_RDR_OFFSET);
memaddr = (uintptr_t)rxbuffer;
ret = sam_dmarxsetup(spics->rxdma, paddr, maddr, nwords);
ret = sam_dmarxsetup(spics->rxdma, regaddr, memaddr, nwords);
if (ret < 0)
{
dmadbg("ERROR: sam_dmarxsetup failed: %d\n", ret);
@ -1509,10 +1509,10 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
spi_rxdma_sample(spics, DMA_AFTER_SETUP);
paddr = spi_physregaddr(spics, SAM_SPI_TDR_OFFSET);
maddr = sam_physramaddr((uintptr_t)txbuffer);
regaddr = spi_regaddr(spics, SAM_SPI_TDR_OFFSET);
memaddr = (uintptr_t)txbuffer;
ret = sam_dmatxsetup(spics->txdma, paddr, maddr, nwords);
ret = sam_dmatxsetup(spics->txdma, regaddr, memaddr, nwords);
if (ret < 0)
{
dmadbg("ERROR: sam_dmatxsetup failed: %d\n", ret);
@ -1741,7 +1741,7 @@ struct spi_dev_s *up_spiinitialize(int port)
if (spics->candma)
{
spics->rxdma = sam_dmachannel(spino, 0);
spics->rxdma = sam_dmachannel(0);
if (!spics->rxdma)
{
spidbg("ERROR: Failed to allocate the RX DMA channel\n");
@ -1751,7 +1751,7 @@ struct spi_dev_s *up_spiinitialize(int port)
if (spics->candma)
{
spics->txdma = sam_dmachannel(spino, 0);
spics->txdma = sam_dmachannel(0);
if (!spics->txdma)
{
spidbg("ERROR: Failed to allocate the TX DMA channel\n");

2
arch/arm/src/sama5/sam_spi.c
View File

@ -847,7 +847,7 @@ static void spi_txcallback(DMA_HANDLE handle, void *arg, int result)
* Name: spi_physregaddr
*
* Description:
* Return the physical address of an HSMCI register
* Return the physical address of an SPI register
*
****************************************************************************/