[FlexCAN] Fix TX drop #2792 and correctly set CAN timings to non-zeroed registers
This commit is contained in:
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2c7faade49
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4842868be2
@ -125,6 +125,7 @@
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#define KINETIS_CAN0_RXIMR13 (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR13_OFFSET)
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#define KINETIS_CAN0_RXIMR14 (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR14_OFFSET)
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#define KINETIS_CAN0_RXIMR15 (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR15_OFFSET)
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#define KINETIS_CAN0_RXIMR_COUNT 16 /* Individual Mask Registers Count */
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/* Register Bit Definitions *************************************************************************/
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@ -178,6 +179,8 @@
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#define CAN_CTRL1_CLKSRC (1 << 13) /* Bit 13: CAN Engine Clock Source */
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#define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Mask */
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#define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Mask */
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#define CAN_CTRL1_TIMINGMSK (0xFFFF << 16)
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/* Bits 16-31: Timing Mask */
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#define CAN_CTRL1_PSEG2_SHIFT (16) /* Bits 16-18: Phase Segment 2 */
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#define CAN_CTRL1_PSEG2_MASK (7 << CAN_CTRL1_PSEG2_SHIFT)
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#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x70000)
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@ -76,8 +76,8 @@
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#define FLAGEFF (1 << 31) /* Extended frame format */
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#define FLAGRTR (1 << 30) /* Remote transmission request */
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#define RXMBCOUNT 5
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#define TXMBCOUNT 2
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#define RXMBCOUNT 11
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#define TXMBCOUNT 5
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#define TOTALMBCOUNT RXMBCOUNT + TXMBCOUNT
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#define IFLAG1_RX ((1 << RXMBCOUNT)-1)
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@ -506,12 +506,16 @@ static void kinetis_setfreeze(uint32_t base, uint32_t freeze);
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static uint32_t kinetis_waitmcr_change(uint32_t base,
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uint32_t mask,
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uint32_t target_state);
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static uint32_t kinetis_waitesr2_change(uint32_t base,
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uint32_t mask,
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uint32_t target_state);
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/* Interrupt handling */
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static void kinetis_receive(FAR struct kinetis_driver_s *priv,
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uint32_t flags);
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static void kinetis_txdone(FAR void *arg);
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static void kinetis_txdone_work(FAR void *arg);
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static void kinetis_txdone(FAR struct kinetis_driver_s *priv);
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static int kinetis_flexcan_interrupt(int irq, FAR void *context,
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FAR void *arg);
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@ -637,6 +641,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
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if (mbi == TXMBCOUNT)
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{
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nwarn("No TX MB available mbi %i\r\n", mbi);
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NETDEV_TXERRORS(&priv->dev);
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return 0; /* No transmission for you! */
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}
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@ -797,6 +802,8 @@ static int kinetis_txpoll(struct net_driver_s *dev)
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{
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if (!devif_loopback(&priv->dev))
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{
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kinetis_txdone(priv);
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/* Send the packet */
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kinetis_transmit(priv);
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@ -805,9 +812,14 @@ static int kinetis_txpoll(struct net_driver_s *dev)
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* not, return a non-zero value to terminate the poll.
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*/
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if (kinetis_txringfull(priv))
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if ((getreg32(priv->base + KINETIS_CAN_ESR2_OFFSET) &
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(CAN_ESR2_IMB | CAN_ESR2_VPS)) ==
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(CAN_ESR2_IMB | CAN_ESR2_VPS))
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{
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return -EBUSY;
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if (kinetis_txringfull(priv))
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{
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return -EBUSY;
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}
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}
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}
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}
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@ -962,7 +974,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv,
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* Function: kinetis_txdone
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*
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* Description:
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* An interrupt was received indicating that the last TX packet(s) is done
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* Check transmit interrupt flags and clear them
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*
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* Input Parameters:
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* priv - Reference to the driver state structure
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@ -971,14 +983,12 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv,
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* None
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*
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* Assumptions:
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* Global interrupts are disabled by the watchdog logic.
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* We are not in an interrupt context so that we can lock the network.
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* None
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*
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****************************************************************************/
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static void kinetis_txdone(FAR void *arg)
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static void kinetis_txdone(FAR struct kinetis_driver_s *priv)
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{
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FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg;
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uint32_t flags;
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uint32_t mbi;
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uint32_t mb_bit;
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@ -1009,13 +1019,38 @@ static void kinetis_txdone(FAR void *arg)
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mb_bit <<= 1;
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}
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}
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/****************************************************************************
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* Function: kinetis_txdone_work
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*
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* Description:
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* An interrupt was received indicating that the last TX packet(s) is done
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*
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* Input Parameters:
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* priv - Reference to the driver state structure
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* Global interrupts are disabled by the watchdog logic.
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* We are not in an interrupt context so that we can lock the network.
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*
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****************************************************************************/
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static void kinetis_txdone_work(FAR void *arg)
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{
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FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg;
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kinetis_txdone(priv);
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/* There should be space for a new TX in any event. Poll the network for
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* new XMIT data
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*/
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net_lock();
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devif_poll(&priv->dev, kinetis_txpoll);
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devif_timer(&priv->dev, 0, kinetis_txpoll);
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net_unlock();
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}
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@ -1071,7 +1106,7 @@ static int kinetis_flexcan_interrupt(int irq, FAR void *context,
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flags = getreg32(priv->base + KINETIS_CAN_IMASK1_OFFSET);
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flags &= ~(IFLAG1_TX);
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putreg32(flags, priv->base + KINETIS_CAN_IMASK1_OFFSET);
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work_queue(CANWORK, &priv->irqwork, kinetis_txdone, priv, 0);
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work_queue(CANWORK, &priv->irqwork, kinetis_txdone_work, priv, 0);
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}
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}
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@ -1172,6 +1207,26 @@ static void kinetis_setenable(uint32_t base, uint32_t enable)
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kinetis_waitmcr_change(base, CAN_MCR_LPMACK, 1);
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}
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static uint32_t kinetis_waitesr2_change(uint32_t base, uint32_t mask,
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uint32_t target_state)
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{
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const uint32_t timeout = 1000;
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uint32_t wait_ack;
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for (wait_ack = 0; wait_ack < timeout; wait_ack++)
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{
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uint32_t state = (getreg32(base + KINETIS_CAN_ESR2_OFFSET) & mask);
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if (state == target_state)
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{
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return true;
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}
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up_udelay(10);
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}
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return false;
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}
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static void kinetis_setfreeze(uint32_t base, uint32_t freeze)
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{
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uint32_t regval;
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@ -1331,7 +1386,9 @@ static void kinetis_txavail_work(FAR void *arg)
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* packet.
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*/
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if (!kinetis_txringfull(priv))
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if (kinetis_waitesr2_change(priv->base,
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(CAN_ESR2_IMB | CAN_ESR2_VPS),
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(CAN_ESR2_IMB | CAN_ESR2_VPS)))
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{
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/* No, there is space for another transfer. Poll the network for
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* new XMIT data.
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@ -1485,7 +1542,7 @@ static int kinetis_ioctl(struct net_driver_s *dev, int cmd,
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#endif /* CONFIG_NETDEV_IOCTL */
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/****************************************************************************
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* Function: kinetis_initalize
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* Function: kinetis_initialize
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*
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* Description:
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* Initialize FLEXCAN device
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@ -1530,6 +1587,9 @@ static int kinetis_initialize(struct kinetis_driver_s *priv)
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#ifndef CONFIG_NET_CAN_CANFD
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regval = getreg32(priv->base + KINETIS_CAN_CTRL1_OFFSET);
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regval &= ~(CAN_CTRL1_TIMINGMSK); /* Reset timings */
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regval |= CAN_CTRL1_PRESDIV(priv->arbi_timing.presdiv) | /* Prescaler divisor factor */
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CAN_CTRL1_PROPSEG(priv->arbi_timing.propseg) | /* Propagation segment */
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CAN_CTRL1_PSEG1(priv->arbi_timing.pseg1) | /* Phase buffer segment 1 */
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@ -1538,8 +1598,7 @@ static int kinetis_initialize(struct kinetis_driver_s *priv)
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putreg32(regval, priv->base + KINETIS_CAN_CTRL1_OFFSET);
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#else
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regval = getreg32(priv->base + KINETIS_CAN_CBT_OFFSET);
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regval |= CAN_CBT_BTF | /* Enable extended bit timing
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regval = CAN_CBT_BTF | /* Enable extended bit timing
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* configurations for CAN-FD for setting up
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* separately nominal and data phase */
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CAN_CBT_EPRESDIV(priv->arbi_timing.presdiv) | /* Prescaler divisor factor */
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@ -1555,8 +1614,7 @@ static int kinetis_initialize(struct kinetis_driver_s *priv)
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regval |= CAN_MCR_FDEN;
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putreg32(regval, priv->base + KINETIS_CAN_MCR_OFFSET);
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regval = getreg32(priv->base + KINETIS_CAN_FDCBT_OFFSET);
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regval |= CAN_FDCBT_FPRESDIV(priv->data_timing.presdiv) | /* Prescaler divisor factor of 1 */
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regval = CAN_FDCBT_FPRESDIV(priv->data_timing.presdiv) | /* Prescaler divisor factor of 1 */
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CAN_FDCBT_FPROPSEG(priv->data_timing.propseg) | /* Propagation
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* segment (only register that doesn't add 1) */
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CAN_FDCBT_FPSEG1(priv->data_timing.pseg1) | /* Phase buffer segment 1 */
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@ -1566,9 +1624,7 @@ static int kinetis_initialize(struct kinetis_driver_s *priv)
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/* Additional CAN-FD configurations */
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regval = getreg32(priv->base + KINETIS_CAN_FDCTRL_OFFSET);
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regval |= CAN_FDCTRL_FDRATE | /* Enable bit rate switch in data phase of frame */
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regval = CAN_FDCTRL_FDRATE | /* Enable bit rate switch in data phase of frame */
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CAN_FDCTRL_TDCEN | /* Enable transceiver delay compensation */
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CAN_FDCTRL_TDCOFF(5) | /* Setup 5 cycles for data phase sampling delay */
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CAN_FDCTRL_MBDSR0(3); /* Setup 64 bytes per message buffer (7 MB's) */
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@ -1588,7 +1644,7 @@ static int kinetis_initialize(struct kinetis_driver_s *priv)
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putreg32(0x0, priv->base + KINETIS_CAN_RXFGMASK_OFFSET);
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for (i = 0; i < TOTALMBCOUNT; i++)
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for (i = 0; i < KINETIS_CAN0_RXIMR_COUNT; i++)
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{
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putreg32(0, priv->base + KINETIS_CAN_RXIMR_OFFSET(i));
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}
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@ -1873,6 +1929,8 @@ int kinetis_caninitialize(int intf)
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ninfo("callbacks done\r\n");
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kinetis_initialize(priv);
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kinetis_ifdown(&priv->dev);
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/* Register the device with the OS so that socket IOCTLs can be performed */
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@ -103,6 +103,7 @@
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# define S32K1XX_CAN_RXIMR29_OFFSET 0x08f4 /* R29 Individual Mask Registers */
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# define S32K1XX_CAN_RXIMR30_OFFSET 0x08f8 /* R30 Individual Mask Registers */
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# define S32K1XX_CAN_RXIMR31_OFFSET 0x08fc /* R31 Individual Mask Registers */
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#define S32K1XX_CAN_RXIMR_COUNT 32 /* Individual Mask Registers Count */
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#define S32K1XX_CAN_CTRL1_PN_OFFSET 0x0b00 /* Pretended Networking Control 1 register */
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#define S32K1XX_CAN_CTRL2_PN_OFFSET 0x0b04 /* Pretended Networking Control 2 register */
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@ -387,6 +388,7 @@
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#define CAN_CTRL1_CLKSRC (1 << 13) /* Bit 13: CAN Engine Clock Source */
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#define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Mask */
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#define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Mask */
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#define CAN_CTRL1_TIMINGMSK (0xFFFF << 16)
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#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0x70000)
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#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << 19)) & 0x380000)
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#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << 22)) & 0xC00000)
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@ -508,12 +508,16 @@ static void s32k1xx_setfreeze(uint32_t base, uint32_t freeze);
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static uint32_t s32k1xx_waitmcr_change(uint32_t base,
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uint32_t mask,
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uint32_t target_state);
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static uint32_t s32k1xx_waitesr2_change(uint32_t base,
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uint32_t mask,
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uint32_t target_state);
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/* Interrupt handling */
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static void s32k1xx_receive(FAR struct s32k1xx_driver_s *priv,
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uint32_t flags);
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static void s32k1xx_txdone(FAR void *arg);
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static void s32k1xx_txdone_work(FAR void *arg);
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static void s32k1xx_txdone(FAR struct s32k1xx_driver_s *priv);
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static int s32k1xx_flexcan_interrupt(int irq, FAR void *context,
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FAR void *arg);
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@ -639,6 +643,7 @@ static int s32k1xx_transmit(FAR struct s32k1xx_driver_s *priv)
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if (mbi == TXMBCOUNT)
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{
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nwarn("No TX MB available mbi %" PRIi32 "\r\n", mbi);
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NETDEV_TXERRORS(&priv->dev);
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return 0; /* No transmission for you! */
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}
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@ -799,6 +804,8 @@ static int s32k1xx_txpoll(struct net_driver_s *dev)
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{
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if (!devif_loopback(&priv->dev))
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{
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s32k1xx_txdone(priv);
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/* Send the packet */
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s32k1xx_transmit(priv);
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@ -807,9 +814,14 @@ static int s32k1xx_txpoll(struct net_driver_s *dev)
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* not, return a non-zero value to terminate the poll.
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*/
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if (s32k1xx_txringfull(priv))
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if ((getreg32(priv->base + S32K1XX_CAN_ESR2_OFFSET) &
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(CAN_ESR2_IMB | CAN_ESR2_VPS)) ==
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(CAN_ESR2_IMB | CAN_ESR2_VPS))
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{
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return -EBUSY;
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if (s32k1xx_txringfull(priv))
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{
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return -EBUSY;
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}
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}
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}
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}
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@ -964,7 +976,7 @@ static void s32k1xx_receive(FAR struct s32k1xx_driver_s *priv,
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* Function: s32k1xx_txdone
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*
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* Description:
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* An interrupt was received indicating that the last TX packet(s) is done
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* Check transmit interrupt flags and clear them
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*
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* Input Parameters:
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* priv - Reference to the driver state structure
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@ -973,14 +985,12 @@ static void s32k1xx_receive(FAR struct s32k1xx_driver_s *priv,
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* None
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*
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* Assumptions:
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* Global interrupts are disabled by the watchdog logic.
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* We are not in an interrupt context so that we can lock the network.
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* None
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*
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****************************************************************************/
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static void s32k1xx_txdone(FAR void *arg)
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static void s32k1xx_txdone(FAR struct s32k1xx_driver_s *priv)
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{
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FAR struct s32k1xx_driver_s *priv = (FAR struct s32k1xx_driver_s *)arg;
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uint32_t flags;
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uint32_t mbi;
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uint32_t mb_bit;
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@ -1011,13 +1021,38 @@ static void s32k1xx_txdone(FAR void *arg)
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mb_bit <<= 1;
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}
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}
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/****************************************************************************
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* Function: s32k1xx_txdone_work
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*
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* Description:
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* An interrupt was received indicating that the last TX packet(s) is done
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*
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* Input Parameters:
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* priv - Reference to the driver state structure
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* Global interrupts are disabled by the watchdog logic.
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* We are not in an interrupt context so that we can lock the network.
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*
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****************************************************************************/
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static void s32k1xx_txdone_work(FAR void *arg)
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{
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FAR struct s32k1xx_driver_s *priv = (FAR struct s32k1xx_driver_s *)arg;
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s32k1xx_txdone(priv);
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/* There should be space for a new TX in any event. Poll the network for
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* new XMIT data
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*/
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net_lock();
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devif_poll(&priv->dev, s32k1xx_txpoll);
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devif_timer(&priv->dev, 0, s32k1xx_txpoll);
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net_unlock();
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}
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@ -1073,7 +1108,7 @@ static int s32k1xx_flexcan_interrupt(int irq, FAR void *context,
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flags = getreg32(priv->base + S32K1XX_CAN_IMASK1_OFFSET);
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flags &= ~(IFLAG1_TX);
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putreg32(flags, priv->base + S32K1XX_CAN_IMASK1_OFFSET);
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work_queue(CANWORK, &priv->irqwork, s32k1xx_txdone, priv, 0);
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work_queue(CANWORK, &priv->irqwork, s32k1xx_txdone_work, priv, 0);
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}
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}
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@ -1175,6 +1210,26 @@ static void s32k1xx_setenable(uint32_t base, uint32_t enable)
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s32k1xx_waitmcr_change(base, CAN_MCR_LPMACK, 1);
|
||||
}
|
||||
|
||||
static uint32_t s32k1xx_waitesr2_change(uint32_t base, uint32_t mask,
|
||||
uint32_t target_state)
|
||||
{
|
||||
const uint32_t timeout = 1000;
|
||||
uint32_t wait_ack;
|
||||
|
||||
for (wait_ack = 0; wait_ack < timeout; wait_ack++)
|
||||
{
|
||||
uint32_t state = (getreg32(base + S32K1XX_CAN_ESR2_OFFSET) & mask);
|
||||
if (state == target_state)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
up_udelay(10);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static void s32k1xx_setfreeze(uint32_t base, uint32_t freeze)
|
||||
{
|
||||
uint32_t regval;
|
||||
@ -1334,7 +1389,9 @@ static void s32k1xx_txavail_work(FAR void *arg)
|
||||
* packet.
|
||||
*/
|
||||
|
||||
if (!s32k1xx_txringfull(priv))
|
||||
if (s32k1xx_waitesr2_change(priv->base,
|
||||
(CAN_ESR2_IMB | CAN_ESR2_VPS),
|
||||
(CAN_ESR2_IMB | CAN_ESR2_VPS)))
|
||||
{
|
||||
/* No, there is space for another transfer. Poll the network for
|
||||
* new XMIT data.
|
||||
@ -1533,6 +1590,9 @@ static int s32k1xx_initialize(struct s32k1xx_driver_s *priv)
|
||||
|
||||
#ifndef CONFIG_NET_CAN_CANFD
|
||||
regval = getreg32(priv->base + S32K1XX_CAN_CTRL1_OFFSET);
|
||||
|
||||
regval &= ~(CAN_CTRL1_TIMINGMSK); /* Reset timings */
|
||||
|
||||
regval |= CAN_CTRL1_PRESDIV(priv->arbi_timing.presdiv) | /* Prescaler divisor factor */
|
||||
CAN_CTRL1_PROPSEG(priv->arbi_timing.propseg) | /* Propagation segment */
|
||||
CAN_CTRL1_PSEG1(priv->arbi_timing.pseg1) | /* Phase buffer segment 1 */
|
||||
@ -1541,8 +1601,8 @@ static int s32k1xx_initialize(struct s32k1xx_driver_s *priv)
|
||||
putreg32(regval, priv->base + S32K1XX_CAN_CTRL1_OFFSET);
|
||||
|
||||
#else
|
||||
regval = getreg32(priv->base + S32K1XX_CAN_CBT_OFFSET);
|
||||
regval |= CAN_CBT_BTF | /* Enable extended bit timing
|
||||
|
||||
regval = CAN_CBT_BTF | /* Enable extended bit timing
|
||||
* configurations for CAN-FD for setting up
|
||||
* separately nominal and data phase */
|
||||
CAN_CBT_EPRESDIV(priv->arbi_timing.presdiv) | /* Prescaler divisor factor */
|
||||
@ -1558,8 +1618,7 @@ static int s32k1xx_initialize(struct s32k1xx_driver_s *priv)
|
||||
regval |= CAN_MCR_FDEN;
|
||||
putreg32(regval, priv->base + S32K1XX_CAN_MCR_OFFSET);
|
||||
|
||||
regval = getreg32(priv->base + S32K1XX_CAN_FDCBT_OFFSET);
|
||||
regval |= CAN_FDCBT_FPRESDIV(priv->data_timing.presdiv) | /* Prescaler divisor factor of 1 */
|
||||
regval = CAN_FDCBT_FPRESDIV(priv->data_timing.presdiv) | /* Prescaler divisor factor of 1 */
|
||||
CAN_FDCBT_FPROPSEG(priv->data_timing.propseg) | /* Propagation
|
||||
* segment (only register that doesn't add 1) */
|
||||
CAN_FDCBT_FPSEG1(priv->data_timing.pseg1) | /* Phase buffer segment 1 */
|
||||
@ -1569,9 +1628,7 @@ static int s32k1xx_initialize(struct s32k1xx_driver_s *priv)
|
||||
|
||||
/* Additional CAN-FD configurations */
|
||||
|
||||
regval = getreg32(priv->base + S32K1XX_CAN_FDCTRL_OFFSET);
|
||||
|
||||
regval |= CAN_FDCTRL_FDRATE | /* Enable bit rate switch in data phase of frame */
|
||||
regval = CAN_FDCTRL_FDRATE | /* Enable bit rate switch in data phase of frame */
|
||||
CAN_FDCTRL_TDCEN | /* Enable transceiver delay compensation */
|
||||
CAN_FDCTRL_TDCOFF(5) | /* Setup 5 cycles for data phase sampling delay */
|
||||
CAN_FDCTRL_MBDSR0(3); /* Setup 64 bytes per message buffer (7 MB's) */
|
||||
@ -1591,7 +1648,7 @@ static int s32k1xx_initialize(struct s32k1xx_driver_s *priv)
|
||||
|
||||
putreg32(0x0, priv->base + S32K1XX_CAN_RXFGMASK_OFFSET);
|
||||
|
||||
for (i = 0; i < TOTALMBCOUNT; i++)
|
||||
for (i = 0; i < S32K1XX_CAN_RXIMR_COUNT; i++)
|
||||
{
|
||||
putreg32(0, priv->base + S32K1XX_CAN_RXIMR_OFFSET(i));
|
||||
}
|
||||
@ -1869,6 +1926,8 @@ int s32k1xx_caninitialize(int intf)
|
||||
|
||||
ninfo("callbacks done\r\n");
|
||||
|
||||
s32k1xx_initialize(priv);
|
||||
|
||||
s32k1xx_ifdown(&priv->dev);
|
||||
|
||||
/* Register the device with the OS so that socket IOCTLs can be performed */
|
||||
|
Loading…
Reference in New Issue
Block a user