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arch/arm/src/lpc43: Add LPC43xx CAN driver

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This commit is contained in:
Alexander Vasiljev 2017-11-15 07:48:39 -06:00 committed by Gregory Nutt
parent ef89207c8d
commit 485f0ebd40
6 changed files with 1426 additions and 53 deletions
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6
arch/arm/src/lpc43xx/Kconfig
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@ -172,11 +172,11 @@ config LPC43_ATIMER
bool "Alarm timer"
default n
config LPC43_CAN1
bool "C_CAN1"
config LPC43_CAN0
bool "C_CAN0"
default n
config LPC43_CAN2
config LPC43_CAN1
bool "C_CAN1"
default n

8
arch/arm/src/lpc43xx/Make.defs
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@ -160,6 +160,14 @@ CHIP_CSRCS += lpc43_i2c.c
endif
endif
ifeq ($(CONFIG_LPC43_CAN0),y)
CHIP_CSRCS += lpc43_can.c
else
ifeq ($(CONFIG_LPC43_CAN1),y)
CHIP_CSRCS += lpc43_can.c
endif
endif
ifeq ($(CONFIG_LPC43_ADC0),y)
CHIP_CSRCS += lpc43_adc.c
else

11
arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h
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@ -41,6 +41,7 @@
****************************************************************************************************/
#include <nuttx/config.h>
#include "lpc43_pinconfig.h"
/****************************************************************************************************
* Pre-processor Definitions
@ -89,14 +90,14 @@
#define PINCONF_ADCTRIG1_1 (PINCONF_FUNC2|PINCONF_PINSE|PINCONF_PIN_3)
#define PINCONF_ADCTRIG1_2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_5)
#define PINCONF_CAN0_RD_1 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_2)
#define PINCONF_CAN0_RD_2 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_1)
#define PINCONF_CAN0_RD_1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_2)
#define PINCONF_CAN0_RD_2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_1)
#define PINCONF_CAN0_TD_1 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_3)
#define PINCONF_CAN0_TD_2 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_2)
#define PINCONF_CAN1_RD_1 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_18)
#define PINCONF_CAN1_RD_2 (PINCONF_FUNC5|PINCONF_PINSE|PINCONF_PIN_1)
#define PINCONF_CAN1_RD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_9)
#define PINCONF_CAN1_RD_1 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_18)
#define PINCONF_CAN1_RD_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_1)
#define PINCONF_CAN1_RD_3 (PINCONF_FUNC6|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_9)
#define PINCONF_CAN1_TD_1 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_17)
#define PINCONF_CAN1_TD_2 (PINCONF_FUNC5|PINCONF_PINSE|PINCONF_PIN_0)
#define PINCONF_CAN1_TD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_8)

90
arch/arm/src/lpc43xx/chip/lpc43_can.h
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@ -93,6 +93,50 @@
/* Register Addresses ***************************************************************/
#define LPC43_CAN0_CNTL (LPC43_CAN0_BASE+LPC43_CAN_CNTL_OFFSET)
#define LPC43_CAN0_STAT (LPC43_CAN0_BASE+LPC43_CAN_STAT_OFFSET)
#define LPC43_CAN0_EC (LPC43_CAN0_BASE+LPC43_CAN_EC_OFFSET)
#define LPC43_CAN0_BT (LPC43_CAN0_BASE+LPC43_CAN_BT_OFFSET)
#define LPC43_CAN0_INT (LPC43_CAN0_BASE+LPC43_CAN_INT_OFFSET)
#define LPC43_CAN0_TEST (LPC43_CAN0_BASE+LPC43_CAN_TEST_OFFSET)
#define LPC43_CAN0_BRPE (LPC43_CAN0_BASE+LPC43_CAN_BRPE_OFFSET)
#define LPC43_CAN0_IF1_CMDREQ (LPC43_CAN0_BASE+LPC43_CAN_IF1_CMDREQ_OFFSET)
#define LPC43_CAN0_IF1_CMDMSKW (LPC43_CAN0_BASE+LPC43_CAN_IF1_CMDMSKW_OFFSET)
#define LPC43_CAN0_IF1_CMDMSKR (LPC43_CAN0_BASE+LPC43_CAN_IF1_CMDMSKR_OFFSET)
#define LPC43_CAN0_IF1_MSK1 (LPC43_CAN0_BASE+LPC43_CAN_IF1_MSK1_OFFSET)
#define LPC43_CAN0_IF1_MSK2 (LPC43_CAN0_BASE+LPC43_CAN_IF1_MSK2_OFFSET)
#define LPC43_CAN0_IF1_ARB1 (LPC43_CAN0_BASE+LPC43_CAN_IF1_ARB1_OFFSET)
#define LPC43_CAN0_IF1_ARB2 (LPC43_CAN0_BASE+LPC43_CAN_IF1_ARB2_OFFSET)
#define LPC43_CAN0_IF1_MCTRL (LPC43_CAN0_BASE+LPC43_CAN_IF1_MCTRL_OFFSET)
#define LPC43_CAN0_IF1_DA1 (LPC43_CAN0_BASE+LPC43_CAN_IF1_DA1_OFFSET)
#define LPC43_CAN0_IF1_DA2 (LPC43_CAN0_BASE+LPC43_CAN_IF1_DA2_OFFSET)
#define LPC43_CAN0_IF1_DB1 (LPC43_CAN0_BASE+LPC43_CAN_IF1_DB1_OFFSET)
#define LPC43_CAN0_IF1_DB2 (LPC43_CAN0_BASE+LPC43_CAN_IF1_DB2_OFFSET)
#define LPC43_CAN0_IF2_CMDREQ (LPC43_CAN0_BASE+LPC43_CAN_IF2_CMDREQ_OFFSET)
#define LPC43_CAN0_IF2_CMDMSKW (LPC43_CAN0_BASE+LPC43_CAN_IF2_CMDMSKW_OFFSET)
#define LPC43_CAN0_IF2_CMDMSKR (LPC43_CAN0_BASE+LPC43_CAN_IF2_CMDMSKR_OFFSET)
#define LPC43_CAN0_IF2_MSK1 (LPC43_CAN0_BASE+LPC43_CAN_IF2_MSK1_OFFSET)
#define LPC43_CAN0_IF2_MSK2 (LPC43_CAN0_BASE+LPC43_CAN_IF2_MSK2_OFFSET)
#define LPC43_CAN0_IF2_ARB1 (LPC43_CAN0_BASE+LPC43_CAN_IF2_ARB1_OFFSET)
#define LPC43_CAN0_IF2_ARB2 (LPC43_CAN0_BASE+LPC43_CAN_IF2_ARB2_OFFSET)
#define LPC43_CAN0_IF2_MCTRL (LPC43_CAN0_BASE+LPC43_CAN_IF2_MCTRL_OFFSET)
#define LPC43_CAN0_IF2_DA1 (LPC43_CAN0_BASE+LPC43_CAN_IF2_DA1_OFFSET)
#define LPC43_CAN0_IF2_DA2 (LPC43_CAN0_BASE+LPC43_CAN_IF2_DA2_OFFSET)
#define LPC43_CAN0_IF2_DB1 (LPC43_CAN0_BASE+LPC43_CAN_IF2_DB1_OFFSET)
#define LPC43_CAN0_IF2_DB2 (LPC43_CAN0_BASE+LPC43_CAN_IF2_DB2_OFFSET)
#define LPC43_CAN0_TXREQ1 (LPC43_CAN0_BASE+LPC43_CAN_TXREQ1_OFFSET)
#define LPC43_CAN0_TXREQ2 (LPC43_CAN0_BASE+LPC43_CAN_TXREQ2_OFFSET)
#define LPC43_CAN0_ND1 (LPC43_CAN0_BASE+LPC43_CAN_ND1_OFFSET)
#define LPC43_CAN0_ND2 (LPC43_CAN0_BASE+LPC43_CAN_ND2_OFFSET)
#define LPC43_CAN0_IR1 (LPC43_CAN0_BASE+LPC43_CAN_IR1_OFFSET)
#define LPC43_CAN0_IR2 (LPC43_CAN0_BASE+LPC43_CAN_IR2_OFFSET)
#define LPC43_CAN0_MSGV1 (LPC43_CAN0_BASE+LPC43_CAN_MSGV1_OFFSET)
#define LPC43_CAN0_MSGV2 (LPC43_CAN0_BASE+LPC43_CAN_MSGV2_OFFSET)
#define LPC43_CAN0_CLKDIV (LPC43_CAN0_BASE+LPC43_CAN_CLKDIV_OFFSET)
#define LPC43_CAN1_CNTL (LPC43_CAN1_BASE+LPC43_CAN_CNTL_OFFSET)
#define LPC43_CAN1_STAT (LPC43_CAN1_BASE+LPC43_CAN_STAT_OFFSET)
#define LPC43_CAN1_EC (LPC43_CAN1_BASE+LPC43_CAN_EC_OFFSET)
@ -137,50 +181,6 @@
#define LPC43_CAN1_MSGV2 (LPC43_CAN1_BASE+LPC43_CAN_MSGV2_OFFSET)
#define LPC43_CAN1_CLKDIV (LPC43_CAN1_BASE+LPC43_CAN_CLKDIV_OFFSET)
#define LPC43_CAN2_CNTL (LPC43_CAN2_BASE+LPC43_CAN_CNTL_OFFSET)
#define LPC43_CAN2_STAT (LPC43_CAN2_BASE+LPC43_CAN_STAT_OFFSET)
#define LPC43_CAN2_EC (LPC43_CAN2_BASE+LPC43_CAN_EC_OFFSET)
#define LPC43_CAN2_BT (LPC43_CAN2_BASE+LPC43_CAN_BT_OFFSET)
#define LPC43_CAN2_INT (LPC43_CAN2_BASE+LPC43_CAN_INT_OFFSET)
#define LPC43_CAN2_TEST (LPC43_CAN2_BASE+LPC43_CAN_TEST_OFFSET)
#define LPC43_CAN2_BRPE (LPC43_CAN2_BASE+LPC43_CAN_BRPE_OFFSET)
#define LPC43_CAN2_IF1_CMDREQ (LPC43_CAN2_BASE+LPC43_CAN_IF1_CMDREQ_OFFSET)
#define LPC43_CAN2_IF1_CMDMSKW (LPC43_CAN2_BASE+LPC43_CAN_IF1_CMDMSKW_OFFSET)
#define LPC43_CAN2_IF1_CMDMSKR (LPC43_CAN2_BASE+LPC43_CAN_IF1_CMDMSKR_OFFSET)
#define LPC43_CAN2_IF1_MSK1 (LPC43_CAN2_BASE+LPC43_CAN_IF1_MSK1_OFFSET)
#define LPC43_CAN2_IF1_MSK2 (LPC43_CAN2_BASE+LPC43_CAN_IF1_MSK2_OFFSET)
#define LPC43_CAN2_IF1_ARB1 (LPC43_CAN2_BASE+LPC43_CAN_IF1_ARB1_OFFSET)
#define LPC43_CAN2_IF1_ARB2 (LPC43_CAN2_BASE+LPC43_CAN_IF1_ARB2_OFFSET)
#define LPC43_CAN2_IF1_MCTRL (LPC43_CAN2_BASE+LPC43_CAN_IF1_MCTRL_OFFSET)
#define LPC43_CAN2_IF1_DA1 (LPC43_CAN2_BASE+LPC43_CAN_IF1_DA1_OFFSET)
#define LPC43_CAN2_IF1_DA2 (LPC43_CAN2_BASE+LPC43_CAN_IF1_DA2_OFFSET)
#define LPC43_CAN2_IF1_DB1 (LPC43_CAN2_BASE+LPC43_CAN_IF1_DB1_OFFSET)
#define LPC43_CAN2_IF1_DB2 (LPC43_CAN2_BASE+LPC43_CAN_IF1_DB2_OFFSET)
#define LPC43_CAN2_IF2_CMDREQ (LPC43_CAN2_BASE+LPC43_CAN_IF2_CMDREQ_OFFSET)
#define LPC43_CAN2_IF2_CMDMSKW (LPC43_CAN2_BASE+LPC43_CAN_IF2_CMDMSKW_OFFSET)
#define LPC43_CAN2_IF2_CMDMSKR (LPC43_CAN2_BASE+LPC43_CAN_IF2_CMDMSKR_OFFSET)
#define LPC43_CAN2_IF2_MSK1 (LPC43_CAN2_BASE+LPC43_CAN_IF2_MSK1_OFFSET)
#define LPC43_CAN2_IF2_MSK2 (LPC43_CAN2_BASE+LPC43_CAN_IF2_MSK2_OFFSET)
#define LPC43_CAN2_IF2_ARB1 (LPC43_CAN2_BASE+LPC43_CAN_IF2_ARB1_OFFSET)
#define LPC43_CAN2_IF2_ARB2 (LPC43_CAN2_BASE+LPC43_CAN_IF2_ARB2_OFFSET)
#define LPC43_CAN2_IF2_MCTRL (LPC43_CAN2_BASE+LPC43_CAN_IF2_MCTRL_OFFSET)
#define LPC43_CAN2_IF2_DA1 (LPC43_CAN2_BASE+LPC43_CAN_IF2_DA1_OFFSET)
#define LPC43_CAN2_IF2_DA2 (LPC43_CAN2_BASE+LPC43_CAN_IF2_DA2_OFFSET)
#define LPC43_CAN2_IF2_DB1 (LPC43_CAN2_BASE+LPC43_CAN_IF2_DB1_OFFSET)
#define LPC43_CAN2_IF2_DB2 (LPC43_CAN2_BASE+LPC43_CAN_IF2_DB2_OFFSET)
#define LPC43_CAN2_TXREQ1 (LPC43_CAN2_BASE+LPC43_CAN_TXREQ1_OFFSET)
#define LPC43_CAN2_TXREQ2 (LPC43_CAN2_BASE+LPC43_CAN_TXREQ2_OFFSET)
#define LPC43_CAN2_ND1 (LPC43_CAN2_BASE+LPC43_CAN_ND1_OFFSET)
#define LPC43_CAN2_ND2 (LPC43_CAN2_BASE+LPC43_CAN_ND2_OFFSET)
#define LPC43_CAN2_IR1 (LPC43_CAN2_BASE+LPC43_CAN_IR1_OFFSET)
#define LPC43_CAN2_IR2 (LPC43_CAN2_BASE+LPC43_CAN_IR2_OFFSET)
#define LPC43_CAN2_MSGV1 (LPC43_CAN2_BASE+LPC43_CAN_MSGV1_OFFSET)
#define LPC43_CAN2_MSGV2 (LPC43_CAN2_BASE+LPC43_CAN_MSGV2_OFFSET)
#define LPC43_CAN2_CLKDIV (LPC43_CAN2_BASE+LPC43_CAN_CLKDIV_OFFSET)
/* Register Bit Definitions *********************************************************/
/* CAN control register */
@ -267,7 +267,7 @@
# define CAN_INT_MSG30 (30 << CAN_INT_SHIFT) /* Message 30 */
# define CAN_INT_MSG31 (31 << CAN_INT_SHIFT) /* Message 31 */
# define CAN_INT_MSG32 (32 << CAN_INT_SHIFT) /* Message 32 */
# define CAN_INT_MSG32 (0x8000 << CAN_INT_SHIFT) /* Status interrupt */
# define CAN_INT_STAT (0x8000 << CAN_INT_SHIFT) /* Status interrupt */
/* Bits 16-31: Reserved */
/* Test register */
/* Bits 0-1: Reserved */

1279
arch/arm/src/lpc43xx/lpc43_can.c Normal file
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File diff suppressed because it is too large Load Diff

85
arch/arm/src/lpc43xx/lpc43_can.h Normal file
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@ -0,0 +1,85 @@
/****************************************************************************
* arch/arm/src/lpc43xx/lpc43_can.h
*
* Copyright(C) 2017 Gregory Nutt. All rights reserved.
*
* Created on: 2 May 2017
* Author: katherine
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_CAN_H_
#define __ARCH_ARM_SRC_LPC43XX_LPC43_CAN_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/can/can.h>
#include "chip/lpc43_can.h"
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
extern "C"
{
#endif
/****************************************************************************
* Name: lpc43_caninitialize
*
* Description:
* Initialize the selected can port
*
* Input Parameter:
* Port number (for hardware that has mutiple can interfaces)
*
* Returned Value:
* Valid can device structure reference on succcess; a NULL on failure
*
****************************************************************************/
#if defined(CONFIG_CAN) && (defined(CONFIG_LPC43_CAN0) || defined(CONFIG_LPC43_CAN1))
struct can_dev_s;
FAR struct can_dev_s *lpc43_caninitialize(int port);
#endif
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_CAN_H_ */